#include <stdint.h>
#include <stdio.h>
#define uint uint32_t

#define WST 8
#define WSU 8
#define WSV 8


#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)

#define WS_MASK  (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)

#include <stdint.h>
#define uint uint32_t

__device__ uint Rng4(uint4& state){
	uint t=state.w;
	t^= t << 11;
	t^= t >> 8;
	state.w=state.z; state.z=state.y; state.y=state.x;
	t ^= state.x;
	t ^= state.x>>19;
	state.x=t;
	return t;
}

__device__ int TUVToIndex(int t, int u, int v){
	int index=0; 
	
	index += (t%3)<<9;
	index += ((u%3)*3)<<9;
	index += ((v%3)*9)<<9;
	
	index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
	return index;
}

__device__ void IndexToTUV(int index, int& t, int& u, int& v){
	t=(index>>9)%3;
	u=((index>>9)/3)%3;
	v=((index>>9)/9);
	
	t+= (index&0x7)*3;
	u+= ((index>>3)&0x7)*3;
	v+= ((index>>6)&0x7)*3;
}

__device__ int AddUnitToIndex(int unit, int index, int& OOB){
	int dt = ((unit>>0)&0x1);
	int du = ((unit>>1)&0x1);
	int dv = ((unit>>2)&0x1);
	int dw =  (unit>>3)&0x1;
	
	int t,u,v;
	IndexToTUV(index, t,u,v);
	
	t+= dt-dw;
	u+= du-dw;
	v+= dv-dw;
	
	OOB  = ((t+WLT)/WLT-1);
	OOB |= ((u+WLU)/WLU-1);
	OOB |= ((v+WLV)/WLV-1);
	int newIndex = TUVToIndex(t,u,v);
	return newIndex;
}

__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
	int valid;
	if((a|b) != 0xf && (a&b))
		return 0;
	c = (((a|b)==0xf)?(a&b):(a|b));
	valid = (c==0x3||c==0xc)?0:1;
	
	return valid;
}

__device__ uint GPUAddUnitVectors(uint a, uint b){
	return (((a|b)==0xf)?(a&b):(a|b));
}

__device__ void TransForw(char* lattice, int index, uint* trans, uint4& rngState){
	int OOB;
	
	int latSiteComplete = lattice[index];
	if(!latSiteComplete) return;
	
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	
	int newIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int newSiteComp = lattice[newIndex];
	int newSl=newSiteComp&0x40;
	if(sl+newSl==0) return;
	
	uint rand = Rng4(rngState);
	int newBond1 = (trans[next/4]>>(4*(2*(next%4)+(rand&0x1))))&0xf;
	int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
	
	int temp = newBond1;
	newBond1 = (rand&0x2)?newBond1:newBond2;
	newBond2 = (rand&0x2)?newBond2:temp;
	
	int destIndex = AddUnitToIndex(newBond1,index, OOB);
	if(OOB) return;
	int destSiteComp = lattice[destIndex];
	if(destSiteComp) return;
	
	int moveFirst;
	if(sl+newSl==0x80){
		moveFirst = (rand&0x4)>>2;
	}
	else if(sl)
		moveFirst = 1;
	else
		moveFirst = 0;
	
// 	int t,u,v, tn, un, vn,td,ud,vd;
// 	IndexToTUV(index, t,u,v);
// 	IndexToTUV(newIndex,tn,un,vn);
// 	IndexToTUV(destIndex,td,ud,vd);

// 	printf("index=%i (%i,%i,%i) [%x], newIndex=%i (%i %i %i) [%x],  destIndex=%i (%i %i %i) [%x]\n", index, t,u,v, latSiteComplete, newIndex, tn,un,vn, newSiteComp, destIndex, td,ud,vd, destSiteComp);

	
	destSiteComp = newBond2;
	if(moveFirst){
		latSiteComplete = newBond1|((label>>1)&0x10);
		destSiteComp |= label&0x10;
	}
	else{
		latSiteComplete = newBond1|label|sl;
		destSiteComp |= (newSiteComp&0x20)>>1;
		newSiteComp = newSiteComp&0x1f;
	}
	
// 	printf("index=%i (%i,%i,%i) [%x], newIndex=%i (%i %i %i) [%x],  destIndex=%i (%i %i %i) [%x]: %x=>%x+%x, %x\n", index, t,u,v, latSiteComplete, newIndex, tn,un,vn, newSiteComp, destIndex, td,ud,vd, destSiteComp, next, newBond1, newBond2, (trans[next/4]>>(4*(2*(next%4))))&0xff);

	lattice[index] = latSiteComplete;
	lattice[destIndex] = destSiteComp;
	if(!moveFirst)
		lattice[newIndex] = newSiteComp;
}

__device__ void TransBack(char* lattice, int index, uint* trans, uint4& rngState){
	int OOB;
	int latSiteComplete = lattice[index];
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	if(!latSiteComplete) return;
	int srcIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int srcSiteComp = lattice[srcIndex];
	int srcNext = srcSiteComp&0xf;
	int srcLabel= srcSiteComp&0x30;
	int srcSl = srcSiteComp&0x40;
	int newNext;
	if(srcSl) return;
	if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
	int newIndex = AddUnitToIndex(newNext, index, OOB);
	if(OOB) return;
	
	int newSiteComp = lattice[newIndex];
	int newSiteSl = newSiteComp&0x40;
	
	if(sl+newSiteSl == 0x80) return;
	
	uint rand = Rng4(rngState);
	
	int moveFirst;
	if(sl+newSiteSl == 0x0){
		moveFirst = rand&0x1;
	}
	else if(sl == 0x40)
		moveFirst = 0;
	else
		moveFirst = 1;
	
	if(moveFirst){
		latSiteComplete = newNext|(label<<1)|srcLabel|0x40;
	}
	else{
		latSiteComplete = newNext|label|sl;
		newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
	}
// 	printf("%x + %x -> %x\n", next, srcNext, newNext);
	lattice[srcIndex]=0;
	lattice[index] = latSiteComplete;
	lattice[newIndex] = newSiteComp;
}

__device__ void DiffuseSL(char* lattice, int index){
	int OOB;
	int latSiteComplete = lattice[index];
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	if(!latSiteComplete) return;
	int newIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int newSiteComp = lattice[newIndex];
	int newSiteLabel = newSiteComp&0x30;
	int newSiteSl = newSiteComp&0x40;
	if(newSiteSl + sl != 0x40) return;
	
	if(sl){
		newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
		latSiteComplete = next|((label>>1)&0x10);
	}
	else{
		latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
		newSiteComp = newSiteComp&0x1f;
	}
// 	if(!sl){
// 	int t,u,v, tn, un, vn;
// 	IndexToTUV(index, t,u,v);
// 	IndexToTUV(newIndex,tn,un,vn);

// 	printf("sl=%i, next=%x, index=%i (%i,%i,%i), newIndex=%i (%i %i %i)\n", sl, next, index, t,u,v, newIndex, tn,un,vn);
	lattice[index] = latSiteComplete;
	lattice[newIndex] = newSiteComp;
// 	}
}


__global__ void polmove(int nStep,  uint4* seeds,  char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
	__shared__ char lattice[BLOCK_SIZE];
	uint trans[4];
	
	int lid = threadIdx.x;
	int wid = blockIdx.x;
	int gid = wid * blockDim.x + lid;
	int widt = wid%NWT;
	int widu = (wid/NWT)%NWU;
	int widv = wid/(NWU*NWT);
	
	uint4 rngl;
	uint4 rngp;
	
	uint site;
		
   int dt = dtuv%WLT;
	int du = (dtuv/WLT)%(WLU);
	int dv = dtuv/(WLT*WLU);
	
	int p=0;
	int dtBlock=WLT-dt;
	int duBlock=WLU-du;
	int dvBlock=WLV-dv;
	int pSwitchNext=dtBlock*duBlock*dvBlock;
	int memOffSet=0;
	
// 	printf("pSwitchNext=%i\n", pSwitchNext);
	
	int src;
	for(src=lid*4; src<BLOCK_SIZE; src += 4*WS){
		for(int i=0; i<4 && i+src<BLOCK_SIZE; i++){
			while(i+src>=pSwitchNext){
				memOffSet = pSwitchNext;
				p++;
				dtBlock = (p&0x1)?dt:(WLT-dt);
				duBlock = (p&0x2)?du:(WLU-du);
				dvBlock = (p&0x4)?dv:(WLV-dv);
				pSwitchNext += dtBlock*duBlock*dvBlock;
			}
			int offSet = src+i-memOffSet;
			int t = ((p&0x1)?(WLT-dt):0) + (offSet%dtBlock);
			int u = ((p&0x2)?(WLU-du):0) + ((offSet/dtBlock)%duBlock);
			int v = ((p&0x4)?(WLV-dv):0) + (offSet/(dtBlock*duBlock));
			int index = TUVToIndex(t,u,v);
			lattice[index]=srcLattice[src+i+wid*BLOCK_SIZE];
		}
	}
	
	for(int i=0; i<4; i++) trans[i] = gTrans[i];
		
	int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
	
	rngp = seeds[gid*2];
	rngl = seeds[gid*2+1];
	
	__syncthreads();
	for(int i=0; i<nStep; i++){
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		DiffuseSL(lattice, site); __syncthreads();
		
		uint randLoc;
		do {
			randLoc = Rng4(rngl);
		}while(randLoc>=4294574721); /// 8081*27^4, so that we are getting good random numbers.
		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransForw(lattice, site, trans, rngp); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		DiffuseSL(lattice, site); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransForw(lattice, site, trans, rngp); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransBack(lattice, site, trans, rngp); __syncthreads();
		
		site = indexStart | ((randLoc%27)<<9);
		TransForw(lattice, site, trans, rngp); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		DiffuseSL(lattice, site); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		TransForw(lattice, site, trans, rngp); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		TransBack(lattice, site, trans, rngp); __syncthreads();
	}
	
   dt = dtuv_next%WLT;
	du = (dtuv_next/WLT)%(WLU);
	dv = dtuv_next/(WLT*WLU);
	
	memOffSet=0;
// 	printf("????\n");
	for(int p=0; p<8; p++){
		int dtBlock = (p&0x1)?dt:(WLT-dt);
		int duBlock = (p&0x2)?du:(WLU-du);
		int dvBlock = (p&0x4)?dv:(WLV-dv);
		int dstWid  =  (widt+NWT-(((p>>0)&0x1)))%NWT;
		    dstWid += ((widu+NWU-(((p>>1)&0x1)))%NWU)*NWT;
		    dstWid += ((widv+NWV-(((p>>2)&0x1)))%NWV)*NWT*NWU;
// 			if(lid==0)
// 				printf("p=%i, wid=(%i,%i,%i), dstWid=(%i,%i,%i)=%i\n", p,widt,widu,widv,(widt+NWT-(((p>>0)&0x1)))%NWT, ((widu+NWU-(((p>>1)&0x1)))%NWU), ((widv+NWV-(((p>>2)&0x1)))%NWV), dstWid);
// 		if(lid==0 && wid==0)
// 			printf("block=(%i,%i,%i), p=%i\n", dtBlock, duBlock, dvBlock, p);
		for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
			int t = i%dtBlock + ((p&0x1)?0:dt);
			int u = (i/dtBlock)%duBlock + ((p&0x2)?0:du);
			int v = i/(dtBlock*duBlock) + ((p&0x4)?0:dv);
			
			int dst = dstWid*BLOCK_SIZE+memOffSet+i;
			int index = TUVToIndex(t, u, v);
// 			if(lid%55==0)
// 				printf("dstWid=%i,%i (p=%i), memOffSet=%i, i=%i, (%i,%i,%i)\n", dstWid, dst, p, memOffSet, i, t,u,v);
			dstLattice[dst] = lattice[index];
		}
		memOffSet += dtBlock*duBlock*dvBlock;
	}
	seeds[gid*2]=rngp;
	seeds[gid*2+1]=rngl;
	__syncthreads();
}

	.file	"tmpxft_003a75b2_00000000-6_ringpol2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4Rng4R5uint4
	.type	_Z4Rng4R5uint4, @function
_Z4Rng4R5uint4:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z4Rng4R5uint4, .-_Z4Rng4R5uint4
	.globl	_Z10TUVToIndexiii
	.type	_Z10TUVToIndexiii, @function
_Z10TUVToIndexiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z10TUVToIndexiii, .-_Z10TUVToIndexiii
	.globl	_Z10IndexToTUViRiS_S_
	.type	_Z10IndexToTUViRiS_S_, @function
_Z10IndexToTUViRiS_S_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z10IndexToTUViRiS_S_, .-_Z10IndexToTUViRiS_S_
	.globl	_Z14AddUnitToIndexiiRi
	.type	_Z14AddUnitToIndexiiRi, @function
_Z14AddUnitToIndexiiRi:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z14AddUnitToIndexiiRi, .-_Z14AddUnitToIndexiiRi
	.globl	_Z25GPUValidateAddUnitVectorsiiRi
	.type	_Z25GPUValidateAddUnitVectorsiiRi, @function
_Z25GPUValidateAddUnitVectorsiiRi:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z25GPUValidateAddUnitVectorsiiRi, .-_Z25GPUValidateAddUnitVectorsiiRi
	.globl	_Z17GPUAddUnitVectorsjj
	.type	_Z17GPUAddUnitVectorsjj, @function
_Z17GPUAddUnitVectorsjj:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2032:
	.size	_Z17GPUAddUnitVectorsjj, .-_Z17GPUAddUnitVectorsjj
	.globl	_Z9TransForwPciPjR5uint4
	.type	_Z9TransForwPciPjR5uint4, @function
_Z9TransForwPciPjR5uint4:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	_Z9TransForwPciPjR5uint4, .-_Z9TransForwPciPjR5uint4
	.globl	_Z9TransBackPciPjR5uint4
	.type	_Z9TransBackPciPjR5uint4, @function
_Z9TransBackPciPjR5uint4:
.LFB2180:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2180:
	.size	_Z9TransBackPciPjR5uint4, .-_Z9TransBackPciPjR5uint4
	.globl	_Z9DiffuseSLPci
	.type	_Z9DiffuseSLPci, @function
_Z9DiffuseSLPci:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	_Z9DiffuseSLPci, .-_Z9DiffuseSLPci
	.globl	_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
	.type	_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, @function
_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L20:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, .-_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
	.globl	_Z7polmoveiP5uint4PcS1_Pjiijjj
	.type	_Z7polmoveiP5uint4PcS1_Pjiijjj, @function
_Z7polmoveiP5uint4PcS1_Pjiijjj:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
	.cfi_endproc
.LFE2061:
	.size	_Z7polmoveiP5uint4PcS1_Pjiijjj, .-_Z7polmoveiP5uint4PcS1_Pjiijjj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7polmoveiP5uint4PcS1_Pjiijjj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#define uint uint32_t

#define WST 8
#define WSU 8
#define WSV 8


#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)

#define WS_MASK  (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)

#include <stdint.h>
#define uint uint32_t

__device__ uint Rng4(uint4& state){
	uint t=state.w;
	t^= t << 11;
	t^= t >> 8;
	state.w=state.z; state.z=state.y; state.y=state.x;
	t ^= state.x;
	t ^= state.x>>19;
	state.x=t;
	return t;
}

__device__ int TUVToIndex(int t, int u, int v){
	int index=0; 
	
	index += (t%3)<<9;
	index += ((u%3)*3)<<9;
	index += ((v%3)*9)<<9;
	
	index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
	return index;
}

__device__ void IndexToTUV(int index, int& t, int& u, int& v){
	t=(index>>9)%3;
	u=((index>>9)/3)%3;
	v=((index>>9)/9);
	
	t+= (index&0x7)*3;
	u+= ((index>>3)&0x7)*3;
	v+= ((index>>6)&0x7)*3;
}

__device__ int AddUnitToIndex(int unit, int index, int& OOB){
	int dt = ((unit>>0)&0x1);
	int du = ((unit>>1)&0x1);
	int dv = ((unit>>2)&0x1);
	int dw =  (unit>>3)&0x1;
	
	int t,u,v;
	IndexToTUV(index, t,u,v);
	
	t+= dt-dw;
	u+= du-dw;
	v+= dv-dw;
	
	OOB  = ((t+WLT)/WLT-1);
	OOB |= ((u+WLU)/WLU-1);
	OOB |= ((v+WLV)/WLV-1);
	int newIndex = TUVToIndex(t,u,v);
	return newIndex;
}

__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
	int valid;
	if((a|b) != 0xf && (a&b))
		return 0;
	c = (((a|b)==0xf)?(a&b):(a|b));
	valid = (c==0x3||c==0xc)?0:1;
	
	return valid;
}

__device__ uint GPUAddUnitVectors(uint a, uint b){
	return (((a|b)==0xf)?(a&b):(a|b));
}

__device__ void TransForw(char* lattice, int index, uint* trans, uint4& rngState){
	int OOB;
	
	int latSiteComplete = lattice[index];
	if(!latSiteComplete) return;
	
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	
	int newIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int newSiteComp = lattice[newIndex];
	int newSl=newSiteComp&0x40;
	if(sl+newSl==0) return;
	
	uint rand = Rng4(rngState);
	int newBond1 = (trans[next/4]>>(4*(2*(next%4)+(rand&0x1))))&0xf;
	int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
	
	int temp = newBond1;
	newBond1 = (rand&0x2)?newBond1:newBond2;
	newBond2 = (rand&0x2)?newBond2:temp;
	
	int destIndex = AddUnitToIndex(newBond1,index, OOB);
	if(OOB) return;
	int destSiteComp = lattice[destIndex];
	if(destSiteComp) return;
	
	int moveFirst;
	if(sl+newSl==0x80){
		moveFirst = (rand&0x4)>>2;
	}
	else if(sl)
		moveFirst = 1;
	else
		moveFirst = 0;
	
// 	int t,u,v, tn, un, vn,td,ud,vd;
// 	IndexToTUV(index, t,u,v);
// 	IndexToTUV(newIndex,tn,un,vn);
// 	IndexToTUV(destIndex,td,ud,vd);

// 	printf("index=%i (%i,%i,%i) [%x], newIndex=%i (%i %i %i) [%x],  destIndex=%i (%i %i %i) [%x]\n", index, t,u,v, latSiteComplete, newIndex, tn,un,vn, newSiteComp, destIndex, td,ud,vd, destSiteComp);

	
	destSiteComp = newBond2;
	if(moveFirst){
		latSiteComplete = newBond1|((label>>1)&0x10);
		destSiteComp |= label&0x10;
	}
	else{
		latSiteComplete = newBond1|label|sl;
		destSiteComp |= (newSiteComp&0x20)>>1;
		newSiteComp = newSiteComp&0x1f;
	}
	
// 	printf("index=%i (%i,%i,%i) [%x], newIndex=%i (%i %i %i) [%x],  destIndex=%i (%i %i %i) [%x]: %x=>%x+%x, %x\n", index, t,u,v, latSiteComplete, newIndex, tn,un,vn, newSiteComp, destIndex, td,ud,vd, destSiteComp, next, newBond1, newBond2, (trans[next/4]>>(4*(2*(next%4))))&0xff);

	lattice[index] = latSiteComplete;
	lattice[destIndex] = destSiteComp;
	if(!moveFirst)
		lattice[newIndex] = newSiteComp;
}

__device__ void TransBack(char* lattice, int index, uint* trans, uint4& rngState){
	int OOB;
	int latSiteComplete = lattice[index];
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	if(!latSiteComplete) return;
	int srcIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int srcSiteComp = lattice[srcIndex];
	int srcNext = srcSiteComp&0xf;
	int srcLabel= srcSiteComp&0x30;
	int srcSl = srcSiteComp&0x40;
	int newNext;
	if(srcSl) return;
	if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
	int newIndex = AddUnitToIndex(newNext, index, OOB);
	if(OOB) return;
	
	int newSiteComp = lattice[newIndex];
	int newSiteSl = newSiteComp&0x40;
	
	if(sl+newSiteSl == 0x80) return;
	
	uint rand = Rng4(rngState);
	
	int moveFirst;
	if(sl+newSiteSl == 0x0){
		moveFirst = rand&0x1;
	}
	else if(sl == 0x40)
		moveFirst = 0;
	else
		moveFirst = 1;
	
	if(moveFirst){
		latSiteComplete = newNext|(label<<1)|srcLabel|0x40;
	}
	else{
		latSiteComplete = newNext|label|sl;
		newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
	}
// 	printf("%x + %x -> %x\n", next, srcNext, newNext);
	lattice[srcIndex]=0;
	lattice[index] = latSiteComplete;
	lattice[newIndex] = newSiteComp;
}

__device__ void DiffuseSL(char* lattice, int index){
	int OOB;
	int latSiteComplete = lattice[index];
	int next = latSiteComplete&0xf;
	int label = latSiteComplete&0x30;
	int sl = latSiteComplete&0x40;
	if(!latSiteComplete) return;
	int newIndex = AddUnitToIndex(next, index, OOB);
	if(OOB) return;
	int newSiteComp = lattice[newIndex];
	int newSiteLabel = newSiteComp&0x30;
	int newSiteSl = newSiteComp&0x40;
	if(newSiteSl + sl != 0x40) return;
	
	if(sl){
		newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
		latSiteComplete = next|((label>>1)&0x10);
	}
	else{
		latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
		newSiteComp = newSiteComp&0x1f;
	}
// 	if(!sl){
// 	int t,u,v, tn, un, vn;
// 	IndexToTUV(index, t,u,v);
// 	IndexToTUV(newIndex,tn,un,vn);

// 	printf("sl=%i, next=%x, index=%i (%i,%i,%i), newIndex=%i (%i %i %i)\n", sl, next, index, t,u,v, newIndex, tn,un,vn);
	lattice[index] = latSiteComplete;
	lattice[newIndex] = newSiteComp;
// 	}
}


__global__ void polmove(int nStep,  uint4* seeds,  char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
	__shared__ char lattice[BLOCK_SIZE];
	uint trans[4];
	
	int lid = threadIdx.x;
	int wid = blockIdx.x;
	int gid = wid * blockDim.x + lid;
	int widt = wid%NWT;
	int widu = (wid/NWT)%NWU;
	int widv = wid/(NWU*NWT);
	
	uint4 rngl;
	uint4 rngp;
	
	uint site;
		
   int dt = dtuv%WLT;
	int du = (dtuv/WLT)%(WLU);
	int dv = dtuv/(WLT*WLU);
	
	int p=0;
	int dtBlock=WLT-dt;
	int duBlock=WLU-du;
	int dvBlock=WLV-dv;
	int pSwitchNext=dtBlock*duBlock*dvBlock;
	int memOffSet=0;
	
// 	printf("pSwitchNext=%i\n", pSwitchNext);
	
	int src;
	for(src=lid*4; src<BLOCK_SIZE; src += 4*WS){
		for(int i=0; i<4 && i+src<BLOCK_SIZE; i++){
			while(i+src>=pSwitchNext){
				memOffSet = pSwitchNext;
				p++;
				dtBlock = (p&0x1)?dt:(WLT-dt);
				duBlock = (p&0x2)?du:(WLU-du);
				dvBlock = (p&0x4)?dv:(WLV-dv);
				pSwitchNext += dtBlock*duBlock*dvBlock;
			}
			int offSet = src+i-memOffSet;
			int t = ((p&0x1)?(WLT-dt):0) + (offSet%dtBlock);
			int u = ((p&0x2)?(WLU-du):0) + ((offSet/dtBlock)%duBlock);
			int v = ((p&0x4)?(WLV-dv):0) + (offSet/(dtBlock*duBlock));
			int index = TUVToIndex(t,u,v);
			lattice[index]=srcLattice[src+i+wid*BLOCK_SIZE];
		}
	}
	
	for(int i=0; i<4; i++) trans[i] = gTrans[i];
		
	int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
	
	rngp = seeds[gid*2];
	rngl = seeds[gid*2+1];
	
	__syncthreads();
	for(int i=0; i<nStep; i++){
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		DiffuseSL(lattice, site); __syncthreads();
		
		uint randLoc;
		do {
			randLoc = Rng4(rngl);
		}while(randLoc>=4294574721); /// 8081*27^4, so that we are getting good random numbers.
		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransForw(lattice, site, trans, rngp); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		DiffuseSL(lattice, site); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransForw(lattice, site, trans, rngp); __syncthreads();
// 		
// 		site = indexStart | ((Rng4(rngl)%27)<<9);
// 		TransBack(lattice, site, trans, rngp); __syncthreads();
		
		site = indexStart | ((randLoc%27)<<9);
		TransForw(lattice, site, trans, rngp); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		DiffuseSL(lattice, site); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		TransForw(lattice, site, trans, rngp); __syncthreads();
		randLoc /= 27;
		site = indexStart | ((randLoc%27)<<9);
		TransBack(lattice, site, trans, rngp); __syncthreads();
	}
	
   dt = dtuv_next%WLT;
	du = (dtuv_next/WLT)%(WLU);
	dv = dtuv_next/(WLT*WLU);
	
	memOffSet=0;
// 	printf("????\n");
	for(int p=0; p<8; p++){
		int dtBlock = (p&0x1)?dt:(WLT-dt);
		int duBlock = (p&0x2)?du:(WLU-du);
		int dvBlock = (p&0x4)?dv:(WLV-dv);
		int dstWid  =  (widt+NWT-(((p>>0)&0x1)))%NWT;
		    dstWid += ((widu+NWU-(((p>>1)&0x1)))%NWU)*NWT;
		    dstWid += ((widv+NWV-(((p>>2)&0x1)))%NWV)*NWT*NWU;
// 			if(lid==0)
// 				printf("p=%i, wid=(%i,%i,%i), dstWid=(%i,%i,%i)=%i\n", p,widt,widu,widv,(widt+NWT-(((p>>0)&0x1)))%NWT, ((widu+NWU-(((p>>1)&0x1)))%NWU), ((widv+NWV-(((p>>2)&0x1)))%NWV), dstWid);
// 		if(lid==0 && wid==0)
// 			printf("block=(%i,%i,%i), p=%i\n", dtBlock, duBlock, dvBlock, p);
		for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
			int t = i%dtBlock + ((p&0x1)?0:dt);
			int u = (i/dtBlock)%duBlock + ((p&0x2)?0:du);
			int v = i/(dtBlock*duBlock) + ((p&0x4)?0:dv);
			
			int dst = dstWid*BLOCK_SIZE+memOffSet+i;
			int index = TUVToIndex(t, u, v);
// 			if(lid%55==0)
// 				printf("dstWid=%i,%i (p=%i), memOffSet=%i, i=%i, (%i,%i,%i)\n", dstWid, dst, p, memOffSet, i, t,u,v);
			dstLattice[dst] = lattice[index];
		}
		memOffSet += dtBlock*duBlock*dvBlock;
	}
	seeds[gid*2]=rngp;
	seeds[gid*2+1]=rngl;
	__syncthreads();
}

	.text
	.file	"ringpol2.hip"
	.globl	_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj # -- Begin function _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.type	_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@function
_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj: # @_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, .Lfunc_end0-_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@object # @_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.section	.rodata,"a",@progbits
	.globl	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.p2align	3, 0x0
_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj:
	.quad	_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.size	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj"
	.size	.L__unnamed_1, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj ; -- Begin function _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.globl	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
	.p2align	8
	.type	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@function
_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj: ; @_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
; %bb.0:                                ; %.preheader289.lr.ph
	s_clause 0x3
	s_load_b128 s[16:19], s[0:1], 0x28
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s12, s[0:1], 0x38
	s_load_b32 s20, s[0:1], 0x4c
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, 0
	s_mul_i32 s24, s15, 0x3600
	s_mov_b32 s23, 0
	s_waitcnt lgkmcnt(0)
	s_mul_hi_i32 s2, s16, 0x2aaaaaab
	s_mul_hi_i32 s3, s16, 0x38e38e39
	s_lshr_b32 s13, s2, 31
	s_ashr_i32 s2, s2, 2
	s_lshr_b32 s14, s3, 31
	s_add_i32 s2, s2, s13
	s_ashr_i32 s3, s3, 7
	s_mul_hi_i32 s13, s2, 0x2aaaaaab
	s_add_i32 s3, s3, s14
	s_lshr_b32 s14, s13, 31
	s_ashr_i32 s13, s13, 2
	s_mul_i32 s21, s2, 24
	s_add_i32 s14, s13, s14
	s_sub_i32 s13, 24, s3
	s_mul_i32 s22, s14, 24
	s_sub_i32 s14, s16, s21
	s_sub_i32 s16, s2, s22
	s_sub_i32 s21, 24, s14
	s_sub_i32 s22, 24, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v8, s22 :: v_dual_lshlrev_b32 v11, 2, v0
	s_mul_i32 s2, s13, s21
	v_mov_b32_e32 v7, s21
	s_mul_i32 s2, s2, s22
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v5, s22
	v_mov_b32_e32 v2, s2
.LBB0_1:                                ; %.preheader289
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v6
	s_mov_b32 s25, 0
	s_mov_b32 s26, 0
.LBB0_2:                                ; %.preheader288
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_i32_e64 v10, v2
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_mov_b32 s27, 0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_2 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v1, v4 :: v_dual_mov_b32 v8, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v3, s14 :: v_dual_add_nc_u32 v4, 1, v1
	v_and_b32_e32 v1, 1, v1
	v_and_b32_e32 v12, 4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_mov_b32_e32 v1, v2
	v_cndmask_b32_e32 v7, s21, v3, vcc_lo
	v_mov_b32_e32 v3, s13
	v_and_b32_e32 v9, 2, v4
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e32 v8, s16, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v13, v8, v7
	v_cndmask_b32_e32 v14, s3, v3, vcc_lo
	v_mad_u64_u32 v[2:3], null, v13, v14, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, v10, v2
	s_or_b32 s27, vcc_lo, s27
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow563
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s27
.LBB0_6:                                ; %Flow564
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_and_not1_saveexec_b32 s2, s2
; %bb.7:                                ; %.preheader288.._crit_edge_crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=2
	v_mul_lo_u32 v13, v7, v8
	v_and_b32_e32 v9, 2, v4
	v_and_b32_e32 v12, 4, v4
; %bb.8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v3, s24, v10
	v_sub_nc_u32_e32 v10, v10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v3
	v_add_co_u32 v14, vcc_lo, s6, v3
	v_ashrrev_i32_e32 v18, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	v_add_nc_u32_e32 v19, v10, v18
	global_load_u8 v3, v[14:15], off
	v_ashrrev_i32_e32 v14, 31, v7
	v_xor_b32_e32 v19, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v7, v14
	v_xor_b32_e32 v15, v15, v14
	v_xor_b32_e32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v16, v15
	v_sub_nc_u32_e32 v17, 0, v15
	v_rcp_iflag_f32_e32 v16, v16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v16, 0x4f7ffffe, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v16, v16
	v_mul_lo_u32 v17, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v16, v17
	v_add_nc_u32_e32 v16, v16, v17
	v_ashrrev_i32_e32 v17, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v16, v19, v16
	v_add_nc_u32_e32 v21, v8, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, v21, v17
	v_ashrrev_i32_e32 v21, 31, v13
	v_mul_lo_u32 v20, v16, v15
	v_add_nc_u32_e32 v22, 1, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v23, v17
	v_xor_b32_e32 v18, v18, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, v19, v20
	v_sub_nc_u32_e32 v24, v20, v15
	v_cmp_ge_u32_e32 vcc_lo, v20, v15
	v_dual_cndmask_b32 v16, v16, v22 :: v_dual_add_nc_u32 v13, v13, v21
	v_rcp_iflag_f32_e32 v22, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v20, v24, vcc_lo
	v_xor_b32_e32 v13, v13, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v23, 1, v16
	v_cmp_ge_u32_e32 vcc_lo, v20, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_u32_e32 v24, v13
	s_waitcnt_depctr 0xfff
	v_dual_cndmask_b32 v15, v16, v23 :: v_dual_mul_f32 v16, 0x4f7ffffe, v22
	v_sub_nc_u32_e32 v22, 0, v17
	v_rcp_iflag_f32_e32 v20, v24
	v_sub_nc_u32_e32 v23, 0, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v14
	v_cvt_u32_f32_e32 v16, v16
	v_sub_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v15, v22, v16
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, 0x4f7ffffe, v20
	v_ashrrev_i32_e32 v22, 31, v14
	v_cvt_u32_f32_e32 v20, v20
	v_mul_hi_u32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v24, v14, v22
	v_mul_lo_u32 v14, v14, v7
	v_mul_lo_u32 v23, v23, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v24, v24, v22
	v_add_nc_u32_e32 v15, v16, v15
	v_sub_nc_u32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v20, v23
	v_mul_hi_u32 v15, v24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v16, v20, v16
	v_mul_lo_u32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v16, v19, v16
	v_sub_nc_u32_e32 v15, v24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v20, v16, v13
	v_sub_nc_u32_e32 v23, v15, v17
	v_cmp_ge_u32_e32 vcc_lo, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v15, v15, v23, vcc_lo
	v_sub_nc_u32_e32 v19, v19, v20
	v_add_nc_u32_e32 v20, 1, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v23, v15, v17
	v_cmp_ge_u32_e64 s2, v15, v17
	v_sub_nc_u32_e32 v24, v19, v13
	v_cmp_ge_u32_e32 vcc_lo, v19, v13
	v_bfe_i32 v17, v4, 0, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v15, v23, s2
	s_add_i32 s2, s26, 1
	v_cndmask_b32_e32 v19, v19, v24, vcc_lo
	s_cmp_gt_u32 s26, 2
	v_xor_b32_e32 v15, v15, v22
	s_cselect_b32 s26, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v22
	v_cndmask_b32_e32 v16, v16, v20, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v19, v13
	v_add_nc_u32_e32 v20, 1, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v16, v20, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_and_b32_e32 v16, s21, v17
	v_xor_b32_e32 v13, v13, v18
	v_cndmask_b32_e32 v9, 0, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v10, v16
	v_sub_nc_u32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v15, v9
	v_cndmask_b32_e64 v12, 0, s13, vcc_lo
	v_mul_hi_i32 v14, 0x55555556, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v13, v12
	v_mul_hi_i32 v13, 0x55555556, v10
	v_mul_hi_i32 v15, 0x55555556, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v16, 31, v14
	v_lshrrev_b32_e32 v17, 31, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v14, v14, v16
	v_lshrrev_b32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v13, v13, v17
	v_lshl_add_u32 v17, v14, 1, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v15, v15, v16
	v_lshl_add_u32 v16, v13, 1, v13
	v_lshlrev_b32_e32 v14, 3, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v9, v9, v17
	v_lshl_add_u32 v17, v15, 1, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, v10, v16
	v_lshlrev_b32_e32 v15, 6, v15
	v_mul_lo_u32 v9, 0x600, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v12, v12, v17
	v_lshl_add_u32 v13, v10, 9, v13
	v_add_nc_u32_e32 v10, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v12, 0x1200, v12
	v_cmp_lt_u32_e32 vcc_lo, 0x35ff, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v9, v13, v9, v14
	s_or_b32 s26, s26, vcc_lo
	v_add3_u32 v9, v9, v12, v15
	s_and_b32 s26, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s25, s26, s25
	s_mov_b32 s26, s2
	s_waitcnt vmcnt(0)
	ds_store_b8 v9, v3
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_2
; %bb.9:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	v_add_nc_u32_e32 v3, 0x800, v6
	v_cmp_lt_u32_e32 vcc_lo, 0x2dff, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v6, v3
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_1
; %bb.10:                               ; %.preheader287.preheader
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr14
.LBB0_11:                               ; %.preheader287
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s16, s[10:11], 0x0
	s_cmp_eq_u32 s2, 3
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s14, s16, s14
	s_cmp_eq_u32 s2, 2
	s_cselect_b32 s13, s16, s13
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 s7, s16, s7
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s6, s16, s6
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s2, 4
	s_cbranch_scc0 .LBB0_11
; %bb.12:
	s_and_b32 s2, 0xffff, s20
	s_load_b32 s1, s[0:1], 0x0
	s_mul_i32 s2, s15, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v1, s2, v0, 1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 4, v[1:2]
	v_add_co_u32 v9, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s1, 1
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b128 v[1:4], v[9:10], off offset:16
	s_waitcnt vmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_67
; %bb.13:                               ; %.preheader.lr.ph
	v_bfe_u32 v12, v0, 5, 2
	v_bfe_u32 v13, v0, 1, 3
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v12, 0x7c, v11, v12
	v_and_or_b32 v11, 0x180, v0, v12
	v_and_b32_e32 v14, 7, v12
	v_mul_u32_u24_e32 v12, 3, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v15, 6, v11
	v_mul_u32_u24_e32 v13, 3, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_u32_u24_e32 v14, 3, v15
	v_mov_b32_e32 v15, 0
.LBB0_14:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v16, v3
	s_mov_b32 s0, 0
.LBB0_15:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v3, v2 :: v_dual_lshlrev_b32 v4, 11, v17
	v_mov_b32_e32 v2, v1
	v_xor_b32_e32 v1, v4, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v4, 19, v2
	v_lshrrev_b32_e32 v17, 8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v17, v4
	v_mov_b32_e32 v17, v16
	v_xor3_b32 v1, v4, v1, v2
	v_mov_b32_e32 v4, v16
	v_mov_b32_e32 v16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, 0xfffa0281, v1
	s_or_b32 s0, vcc_lo, s0
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_15
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_hi_u32 v16, 0x2f684bdb, v1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v1, v16
	v_lshrrev_b32_e32 v17, 1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, v17, v16
	v_lshrrev_b32_e32 v16, 4, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, 27
	v_sub_nc_u32_e32 v18, v1, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v17, v18, 9, v11
	ds_load_u8 v19, v17
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u16_e32 0, v19
	s_cbranch_execz .LBB0_26
; %bb.17:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v20, 0xff, v18
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u16 v21, 0xab, v20
	v_lshrrev_b16 v21, 9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v22, 0x56, v21
	v_mul_lo_u16 v23, v21, 3
	v_lshrrev_b16 v22, 8, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u16 v23, v18, v23
	v_bfe_i32 v18, v19, 0, 8
	v_mul_lo_u16 v19, v20, 57
	v_mul_lo_u16 v22, v22, 3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v20, 0xff, v23
	v_bfe_u32 v25, v18, 3, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_lshrrev_b16 v19, 9, v19
	v_and_b32_e32 v27, 15, v18
	v_sub_nc_u16 v21, v21, v22
	v_and_b32_e32 v22, 1, v18
	v_add_nc_u32_e32 v23, v13, v20
	v_and_b32_e32 v19, 0xffff, v19
	v_bfe_u32 v20, v18, 1, 1
	v_and_b32_e32 v21, 0xff, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, v14, v19
	v_add_nc_u32_e32 v24, v12, v21
	v_add_nc_u32_e32 v21, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v24, v25
	v_sub_nc_u32_e32 v19, v21, v25
	v_bfe_u32 v21, v27, 2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v20, v22, v20
	v_sub_nc_u32_e32 v22, v26, v25
	v_add_nc_u16 v25, v19, 24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v28, v20, 24
	v_add_nc_u32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v22, 0xff, v25
	v_and_b32_e32 v25, 0xff, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, 24, v21
	v_mul_lo_u16 v22, 0xab, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v25, 0xab, v25
	v_mul_hi_u32 v28, 0xaaaaaaab, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v22, 12, v22
	v_lshrrev_b16 v25, 12, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v22, 0xffff, v22
	v_lshrrev_b32_e32 v28, 4, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v25, 0xffff, v25
	v_add_nc_u32_e32 v22, -1, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, -1, v28
	v_add_nc_u32_e32 v25, -1, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v22, v22, v28, v25
	v_cmpx_eq_u32_e32 0, v22
	s_cbranch_execz .LBB0_25
; %bb.18:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v22, 0x55555556, v21
	v_bfe_i32 v25, v19, 0, 8
	v_bfe_i32 v28, v20, 0, 8
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v25, 0x56, v25
	v_mul_lo_u16 v28, 0x56, v28
	v_lshrrev_b32_e32 v29, 31, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v30, 15, v25
	v_lshrrev_b16 v25, 8, v25
	v_add_nc_u32_e32 v22, v22, v29
	v_lshrrev_b16 v29, 15, v28
	v_lshrrev_b16 v28, 8, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v25, v25, v30
	v_lshl_add_u32 v31, v22, 1, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v28, v28, v29
	v_mul_lo_u16 v29, v25, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v21, v21, v31
	v_mul_lo_u16 v30, v28, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v19, v19, v29
	v_mul_lo_u32 v21, 0x1200, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v20, v20, v30
	v_bfe_i32 v19, v19, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v20, v20, 0, 8
	v_and_or_b32 v21, 0xff, v25, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v19, 9, v19
	v_and_b32_e32 v25, 0xff, v28
	v_mul_i32_i24_e32 v20, 0x600, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v21, v22, 6, v21
	v_lshlrev_b32_e32 v22, 3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v19, v21, v19, v20
	v_add_nc_u32_e32 v19, v19, v22
	v_and_b32_e32 v22, 64, v18
	ds_load_u8 v20, v19
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v21, 64, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, v21, v22
	v_cmpx_ne_u32_e32 0, v25
	s_cbranch_execz .LBB0_24
; %bb.19:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b32_e32 v21, 11, v8
	v_mov_b32_e32 v29, s7
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v21, v8
	v_lshrrev_b32_e32 v21, 19, v5
	v_lshrrev_b32_e32 v28, 8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v21, v28, v21
	v_bfe_u32 v28, v18, 2, 2
	v_xor3_b32 v21, v21, v8, v5
	v_lshlrev_b32_e32 v8, 1, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 1, v28
	v_and_b32_e32 v30, 1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_and_or_b32 v8, v8, 6, v30
	v_cndmask_b32_e32 v29, s6, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v28
	v_lshlrev_b32_e32 v8, 2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v29, v29, s13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v28
	v_cndmask_b32_e64 v28, v29, s14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfe_u32 v8, v28, v8, 4
	v_xor_b32_e32 v28, 15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v27, v28, v27
	v_and_b32_e32 v28, v28, v18
	v_cmp_eq_u32_e32 vcc_lo, 15, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v28, v27, v28 :: v_dual_and_b32 v29, 2, v21
	v_cmp_eq_u32_e32 vcc_lo, 0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v27, v8, v28, vcc_lo
	v_lshrrev_b32_e32 v29, 3, v27
	v_and_b32_e32 v30, 1, v27
	v_bfe_u32 v31, v27, 1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v23, v29
	v_sub_nc_u32_e32 v24, v24, v29
	v_sub_nc_u32_e32 v26, v26, v29
	v_add_nc_u32_e32 v23, v23, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, v24, v31
	v_bfe_u32 v30, v27, 2, 1
	v_add_nc_u16 v29, v23, 24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v31, v24, 24
	v_add_nc_u32_e32 v26, v26, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v29, 0xff, v29
	v_and_b32_e32 v30, 0xff, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v31, 24, v26
	v_mul_lo_u16 v29, 0xab, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v30, 0xab, v30
	v_mul_hi_u32 v31, 0xaaaaaaab, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v29, 12, v29
	v_lshrrev_b16 v30, 12, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v29, 0xffff, v29
	v_and_b32_e32 v30, 0xffff, v30
	v_lshrrev_b32_e32 v31, 4, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v29, -1, v29
	v_add_nc_u32_e32 v30, -1, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v31, -1, v31
	v_or3_b32 v29, v29, v31, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v29
	s_cbranch_execz .LBB0_23
; %bb.20:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v29, 0x55555556, v26
	v_bfe_i32 v30, v23, 0, 8
	v_bfe_i32 v31, v24, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v30, 0x56, v30
	v_mul_lo_u16 v31, 0x56, v31
	v_lshrrev_b32_e32 v32, 31, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v33, 15, v30
	v_lshrrev_b16 v30, 8, v30
	v_add_nc_u32_e32 v29, v29, v32
	v_lshrrev_b16 v32, 15, v31
	v_lshrrev_b16 v31, 8, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v30, v30, v33
	v_lshl_add_u32 v34, v29, 1, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v31, v31, v32
	v_mul_lo_u16 v32, v30, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v26, v26, v34
	v_mul_lo_u16 v33, v31, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v23, v23, v32
	v_mul_lo_u32 v26, 0x1200, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v24, v24, v33
	v_bfe_i32 v23, v23, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v24, v24, 0, 8
	v_and_or_b32 v26, 0xff, v30, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v23, 9, v23
	v_and_b32_e32 v30, 0xff, v31
	v_mul_i32_i24_e32 v24, 0x600, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v26, v29, 6, v26
	v_lshlrev_b32_e32 v29, 3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v23, v26, v23, v24
	v_add_nc_u32_e32 v23, v23, v29
	ds_load_u8 v24, v23
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e64 s0, 0, v24
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_23
; %bb.21:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v24, 4, v21
	v_cmp_eq_u32_e64 s0, 0x80, v25
	v_lshrrev_b32_e32 v26, 1, v18
	v_and_b32_e32 v29, 0xff, v20
	v_dual_cndmask_b32 v8, v28, v8 :: v_dual_and_b32 v25, 0x70, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v24, s0
	v_and_b32_e32 v24, 16, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 1, v29
	v_cmp_eq_u32_e64 s0, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v22, v24, v25, s0
	v_cndmask_b32_e64 v18, v18, v26, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v22, v27, v22
	v_and_or_b32 v8, v18, 16, v8
	ds_store_b8 v17, v22
	ds_store_b8 v23, v8
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v8, 31, v20
	ds_store_b8 v19, v8
.LBB0_23:                               ; %Flow558
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v17, v5 :: v_dual_mov_b32 v18, v6
	v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v5, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v6, v17 :: v_dual_mov_b32 v7, v18
.LBB0_24:                               ; %Flow559
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_25:                               ; %Flow560
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_26:                               ; %_Z9TransForwPciPjR15HIP_vector_typeIjLj4EE.exit
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_hi_u32 v17, 0x97b425f, v16
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_mul_u32_u24_e32 v17, 27, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, v16, v17
	v_lshl_or_b32 v16, v19, 9, v11
	ds_load_u8 v17, v16
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u16_e32 0, v17
	s_cbranch_execz .LBB0_34
; %bb.27:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v20, 0xff, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v18, 0xab, v20
	v_mul_lo_u16 v20, v20, 57
	v_lshrrev_b16 v21, 9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b16 v20, 9, v20
	v_mul_lo_u16 v18, 0x56, v21
	v_mul_lo_u16 v23, v21, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v20, 0xffff, v20
	v_lshrrev_b16 v18, 8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v19, v19, v23
	v_add_nc_u32_e32 v25, v14, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v22, v18, 3
	v_bfe_i32 v18, v17, 0, 8
	v_sub_nc_u16 v21, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_and_b32_e32 v22, 1, v18
	v_bfe_u32 v24, v18, 3, 1
	v_bfe_u32 v23, v18, 1, 1
	v_add_nc_u32_e32 v21, v12, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v19, v13, v19, v22
	v_lshrrev_b16 v22, 2, v17
	v_sub_nc_u32_e32 v21, v21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v24
	v_add_nc_u32_e32 v20, v21, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v21, 1, v22
	v_sub_nc_u32_e32 v22, v25, v24
	v_add_nc_u16 v23, v19, 24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v24, v20, 24
	v_add_nc_u32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v22, 0xff, v23
	v_and_b32_e32 v23, 0xff, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, 24, v21
	v_mul_lo_u16 v22, 0xab, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v23, 0xab, v23
	v_mul_hi_u32 v24, 0xaaaaaaab, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v22, 12, v22
	v_lshrrev_b16 v23, 12, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v22, 0xffff, v22
	v_lshrrev_b32_e32 v24, 4, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v23, 0xffff, v23
	v_add_nc_u32_e32 v22, -1, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, -1, v24
	v_add_nc_u32_e32 v23, -1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v22, v22, v24, v23
	v_cmp_eq_u32_e32 vcc_lo, 0, v22
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_34
; %bb.28:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v22, 0x55555556, v21
	v_bfe_i32 v23, v19, 0, 8
	v_bfe_i32 v24, v20, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v23, 0x56, v23
	v_mul_lo_u16 v24, 0x56, v24
	v_lshrrev_b32_e32 v25, 31, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v26, 15, v23
	v_lshrrev_b16 v23, 8, v23
	v_add_nc_u32_e32 v22, v22, v25
	v_lshrrev_b16 v25, 15, v24
	v_lshrrev_b16 v24, 8, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v23, v23, v26
	v_lshl_add_u32 v27, v22, 1, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v24, v24, v25
	v_mul_lo_u16 v25, v23, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v21, v21, v27
	v_mul_lo_u16 v26, v24, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v19, v19, v25
	v_mul_lo_u32 v21, 0x1200, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v20, v20, v26
	v_bfe_i32 v19, v19, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v20, v20, 0, 8
	v_and_or_b32 v21, 0xff, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v19, 9, v19
	v_and_b32_e32 v23, 0xff, v24
	v_mul_i32_i24_e32 v20, 0x600, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v21, v22, 6, v21
	v_lshlrev_b32_e32 v22, 3, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v19, v21, v19, v20
	v_add_nc_u32_e32 v19, v19, v22
	v_and_b32_e32 v22, 64, v18
	ds_load_u8 v20, v19
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v21, 64, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v21, v21, v22
	v_cmp_eq_u32_e32 vcc_lo, 64, v21
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_34
; %bb.29:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v21, 15, v18
	v_cmp_ne_u32_e32 vcc_lo, 0, v22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
; %bb.30:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b16 v17, 1, v17
	v_lshrrev_b32_e32 v18, 1, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v17, 32, v17
	v_and_or_b32 v23, v18, 16, v21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v17, v17, v20
                                        ; implicit-def: $vgpr20
	v_or_b32_e32 v22, 64, v17
; %bb.31:                               ; %Flow553
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s3, s3
; %bb.32:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v17, 0xff, v20
	v_lshlrev_b32_e32 v18, 1, v18
	v_and_b32_e32 v22, 31, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v17, 1, v17
	v_and_b32_e32 v17, 16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v17, v18, 32, v17
	v_or3_b32 v23, v17, v21, 64
; %bb.33:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b8 v16, v23
	ds_store_b8 v19, v22
.LBB0_34:                               ; %_Z9DiffuseSLPci.exit
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_hi_u32 v16, 0x59e60383, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, exec_lo
	v_lshrrev_b32_e32 v16, 8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, 0x97b425f, v16
	v_mul_u32_u24_e32 v17, 27, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v16, v17
	v_lshl_or_b32 v16, v17, 9, v11
	ds_load_u8 v18, v16
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u16_e32 0, v18
	s_cbranch_execz .LBB0_44
; %bb.35:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v19, 0xff, v17
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u16 v20, 0xab, v19
	v_lshrrev_b16 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v21, 0x56, v20
	v_mul_lo_u16 v22, v20, 3
	v_lshrrev_b16 v21, 8, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u16 v22, v17, v22
	v_bfe_i32 v17, v18, 0, 8
	v_mul_lo_u16 v18, v19, 57
	v_mul_lo_u16 v21, v21, 3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v19, 0xff, v22
	v_bfe_u32 v24, v17, 3, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_lshrrev_b16 v18, 9, v18
	v_and_b32_e32 v26, 15, v17
	v_sub_nc_u16 v20, v20, v21
	v_and_b32_e32 v21, 1, v17
	v_add_nc_u32_e32 v22, v13, v19
	v_and_b32_e32 v18, 0xffff, v18
	v_bfe_u32 v19, v17, 1, 1
	v_and_b32_e32 v20, 0xff, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v25, v14, v18
	v_add_nc_u32_e32 v23, v12, v20
	v_add_nc_u32_e32 v20, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v23, v24
	v_sub_nc_u32_e32 v18, v20, v24
	v_bfe_u32 v20, v26, 2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v19, v21, v19
	v_sub_nc_u32_e32 v21, v25, v24
	v_add_nc_u16 v24, v18, 24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v27, v19, 24
	v_add_nc_u32_e32 v20, v21, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v21, 0xff, v24
	v_and_b32_e32 v24, 0xff, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v27, 24, v20
	v_mul_lo_u16 v21, 0xab, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v24, 0xab, v24
	v_mul_hi_u32 v27, 0xaaaaaaab, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v21, 12, v21
	v_lshrrev_b16 v24, 12, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v21, 0xffff, v21
	v_lshrrev_b32_e32 v27, 4, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v24, 0xffff, v24
	v_add_nc_u32_e32 v21, -1, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v27, -1, v27
	v_add_nc_u32_e32 v24, -1, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v21, v21, v27, v24
	v_cmpx_eq_u32_e32 0, v21
	s_cbranch_execz .LBB0_43
; %bb.36:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v21, 0x55555556, v20
	v_bfe_i32 v24, v18, 0, 8
	v_bfe_i32 v27, v19, 0, 8
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v24, 0x56, v24
	v_mul_lo_u16 v27, 0x56, v27
	v_lshrrev_b32_e32 v28, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v29, 15, v24
	v_lshrrev_b16 v24, 8, v24
	v_add_nc_u32_e32 v21, v21, v28
	v_lshrrev_b16 v28, 15, v27
	v_lshrrev_b16 v27, 8, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v24, v24, v29
	v_lshl_add_u32 v30, v21, 1, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v27, v27, v28
	v_mul_lo_u16 v28, v24, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v20, v20, v30
	v_mul_lo_u16 v29, v27, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v18, v18, v28
	v_mul_lo_u32 v20, 0x1200, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v19, v19, v29
	v_bfe_i32 v18, v18, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v19, v19, 0, 8
	v_and_or_b32 v20, 0xff, v24, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v18, 9, v18
	v_and_b32_e32 v24, 0xff, v27
	v_mul_i32_i24_e32 v19, 0x600, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v20, v21, 6, v20
	v_lshlrev_b32_e32 v21, 3, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v18, v20, v18, v19
	v_add_nc_u32_e32 v18, v18, v21
	v_and_b32_e32 v21, 64, v17
	ds_load_u8 v19, v18
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v20, 64, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v24, v20, v21
	v_cmpx_ne_u32_e32 0, v24
	s_cbranch_execz .LBB0_42
; %bb.37:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b32_e32 v20, 11, v8
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v20, v8
	v_lshrrev_b32_e32 v20, 19, v5
	v_lshrrev_b32_e32 v27, 8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v20, v27, v20
	v_bfe_u32 v27, v17, 2, 2
	v_xor3_b32 v20, v20, v8, v5
	v_mov_b32_e32 v28, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 1, v27
	v_lshlrev_b32_e32 v8, 1, v17
	v_and_b32_e32 v29, 1, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v28, s6, v28, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v27
	v_and_or_b32 v8, v8, 6, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, s13, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 3, v27
	v_lshlrev_b32_e32 v8, 2, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v27, v28, s14, vcc_lo
	v_and_b32_e32 v28, 2, v20
	v_bfe_u32 v8, v27, v8, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v27, 15, v8
	v_or_b32_e32 v26, v27, v26
	v_and_b32_e32 v27, v27, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 15, v26
	v_cndmask_b32_e32 v27, v26, v27, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v8, v27, vcc_lo
	v_lshrrev_b32_e32 v28, 3, v26
	v_bfe_u32 v30, v26, 1, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v23, v28
	v_sub_nc_u32_e32 v22, v22, v28
	v_sub_nc_u32_e32 v25, v25, v28
	v_add_nc_u32_e32 v23, v23, v30
	v_and_b32_e32 v29, 1, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v30, v23, 24
	v_add_nc_u32_e32 v22, v22, v29
	v_bfe_u32 v29, v26, 2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v28, v22, 24
	v_add_nc_u32_e32 v25, v25, v29
	v_and_b32_e32 v29, 0xff, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v28, 0xff, v28
	v_add_nc_u32_e32 v30, 24, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v29, 0xab, v29
	v_mul_lo_u16 v28, 0xab, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v30, 0xaaaaaaab, v30
	v_lshrrev_b16 v29, 12, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b16 v28, 12, v28
	v_and_b32_e32 v29, 0xffff, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v30, 4, v30
	v_and_b32_e32 v28, 0xffff, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v29, -1, v29
	v_add_nc_u32_e32 v30, -1, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v28, -1, v28
	v_or3_b32 v28, v28, v30, v29
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v28
	s_cbranch_execz .LBB0_41
; %bb.38:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v28, 0x55555556, v25
	v_bfe_i32 v29, v22, 0, 8
	v_bfe_i32 v30, v23, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v29, 0x56, v29
	v_mul_lo_u16 v30, 0x56, v30
	v_lshrrev_b32_e32 v31, 31, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v32, 15, v29
	v_lshrrev_b16 v29, 8, v29
	v_add_nc_u32_e32 v28, v28, v31
	v_lshrrev_b16 v31, 15, v30
	v_lshrrev_b16 v30, 8, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v29, v29, v32
	v_lshl_add_u32 v33, v28, 1, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v30, v30, v31
	v_mul_lo_u16 v31, v29, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v25, v25, v33
	v_mul_lo_u16 v32, v30, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v22, v22, v31
	v_mul_lo_u32 v25, 0x1200, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v23, v23, v32
	v_bfe_i32 v22, v22, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v23, v23, 0, 8
	v_and_or_b32 v25, 0xff, v29, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v22, 9, v22
	v_and_b32_e32 v29, 0xff, v30
	v_mul_i32_i24_e32 v23, 0x600, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v25, v28, 6, v25
	v_lshlrev_b32_e32 v28, 3, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v22, v25, v22, v23
	v_add_nc_u32_e32 v22, v22, v28
	ds_load_u8 v23, v22
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e64 s0, 0, v23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_41
; %bb.39:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v23, 4, v20
	v_cmp_eq_u32_e64 s0, 0x80, v24
	v_lshrrev_b32_e32 v25, 1, v17
	v_and_b32_e32 v28, 0xff, v19
	v_and_b32_e32 v24, 0x70, v17
	v_cndmask_b32_e32 v8, v27, v8, vcc_lo
	v_cndmask_b32_e64 v21, v21, v23, s0
	v_and_b32_e32 v23, 16, v25
	v_lshrrev_b32_e32 v25, 1, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v21
	v_cndmask_b32_e64 v21, v23, v24, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v17, v25, s0
	v_or_b32_e32 v21, v26, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_and_or_b32 v8, v17, 16, v8
	ds_store_b8 v16, v21
	ds_store_b8 v22, v8
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v8, 31, v19
	ds_store_b8 v18, v8
.LBB0_41:                               ; %Flow550
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v17, v6
	v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v5, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v6, v16 :: v_dual_mov_b32 v7, v17
.LBB0_42:                               ; %Flow551
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_43:                               ; %Flow552
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_44:                               ; %_Z9TransForwPciPjR15HIP_vector_typeIjLj4EE.exit238
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_hi_u32 v16, 0xd517bc79, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, exec_lo
	v_lshrrev_b32_e32 v16, 14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, 0x97b425f, v16
	v_mul_u32_u24_e32 v17, 27, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, v16, v17
	v_lshl_or_b32 v16, v17, 9, v11
	ds_load_u8 v18, v16
	s_waitcnt lgkmcnt(0)
	v_cmpx_ne_u16_e32 0, v18
	s_cbranch_execz .LBB0_66
; %bb.45:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v19, 0xff, v17
	v_lshrrev_b16 v23, 1, v18
	v_lshrrev_b16 v27, 2, v18
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v20, 0xab, v19
	v_mul_lo_u16 v19, v19, 57
	v_lshrrev_b16 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b16 v19, 9, v19
	v_mul_lo_u16 v21, 0x56, v20
	v_mul_lo_u16 v22, v20, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v19, 0xffff, v19
	v_lshrrev_b16 v21, 8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v22, v17, v22
	v_bfe_i32 v17, v18, 0, 8
	v_mul_lo_u16 v21, v21, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v24, 1, v17
	v_bfe_u32 v25, v17, 3, 1
	v_sub_nc_u16 v20, v20, v21
	v_and_b32_e32 v21, 0xff, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v20, 0xff, v20
	v_add_nc_u32_e32 v21, v13, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v22, v12, v20
	v_and_b32_e32 v20, 1, v23
	v_add_nc_u32_e32 v24, v24, v21
	v_add_nc_u32_e32 v23, v14, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v26, v22, v25
	v_sub_nc_u32_e32 v18, v24, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v24, v23, v25
	v_add_nc_u32_e32 v19, v26, v20
	v_and_b32_e32 v20, 1, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v25, v18, 24
	v_add_nc_u16 v26, v19, 24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v20, v24, v20
	v_and_b32_e32 v24, 0xff, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v25, 0xff, v26
	v_add_nc_u32_e32 v26, 24, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v24, 0xab, v24
	v_mul_lo_u16 v25, 0xab, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v26, 0xaaaaaaab, v26
	v_lshrrev_b16 v24, 12, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b16 v25, 12, v25
	v_and_b32_e32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 4, v26
	v_and_b32_e32 v25, 0xffff, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, -1, v24
	v_add_nc_u32_e32 v26, -1, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, -1, v25
	v_or3_b32 v24, v24, v26, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v24
	s_cbranch_execz .LBB0_65
; %bb.46:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v24, 0x55555556, v20
	v_bfe_i32 v25, v18, 0, 8
	v_bfe_i32 v26, v19, 0, 8
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v25, 0x56, v25
	v_mul_lo_u16 v26, 0x56, v26
	v_lshrrev_b32_e32 v27, 31, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v28, 15, v25
	v_lshrrev_b16 v25, 8, v25
	v_add_nc_u32_e32 v24, v24, v27
	v_lshrrev_b16 v27, 15, v26
	v_lshrrev_b16 v26, 8, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v25, v25, v28
	v_lshl_add_u32 v29, v24, 1, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v26, v26, v27
	v_mul_lo_u16 v27, v25, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v20, v20, v29
	v_mul_lo_u16 v28, v26, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v18, v18, v27
	v_mul_lo_u32 v20, 0x1200, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v19, v19, v28
	v_bfe_i32 v18, v18, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v19, v19, 0, 8
	v_and_or_b32 v20, 0xff, v25, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v18, 9, v18
	v_and_b32_e32 v25, 0xff, v26
	v_mul_i32_i24_e32 v19, 0x600, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v20, v24, 6, v20
	v_lshlrev_b32_e32 v24, 3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v18, v20, v18, v19
	v_add_nc_u32_e32 v18, v18, v24
	ds_load_u8 v20, v18
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v19, 64, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v19
	s_cbranch_execz .LBB0_64
; %bb.47:                               ; %_Z25GPUValidateAddUnitVectorsiiRi.exit.i
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_or_b32_e32 v19, v20, v17
	v_and_b32_e32 v24, 15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v19, 15, v19
	v_and_b32_e32 v24, v24, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 15, v19
	v_cmp_eq_u32_e64 s0, 0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s10, s0, vcc_lo
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_63
; %bb.48:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_cndmask_b32_e32 v19, v19, v24, vcc_lo
	s_mov_b32 s11, 0
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 11, v19
	s_xor_b32 s10, exec_lo, s10
; %bb.49:                               ; %LeafBlock536
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 12, v19
	s_and_b32 s11, vcc_lo, exec_lo
; %bb.50:                               ; %Flow542
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s10, s10
; %bb.51:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 3, v19
	s_and_not1_b32 s11, s11, exec_lo
	s_and_b32 s16, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s11, s16
; %bb.52:                               ; %Flow543
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s11
	s_cbranch_execz .LBB0_62
; %bb.53:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshrrev_b32_e32 v24, 3, v19
	v_and_b32_e32 v25, 1, v19
	v_bfe_u32 v26, v19, 1, 1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v21, v21, v24
	v_sub_nc_u32_e32 v22, v22, v24
	v_sub_nc_u32_e32 v23, v23, v24
	v_add_nc_u32_e32 v21, v21, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v22, v22, v26
	v_bfe_u32 v25, v19, 2, 1
	v_add_nc_u16 v24, v21, 24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v26, v22, 24
	v_add_nc_u32_e32 v23, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v24, 0xff, v24
	v_and_b32_e32 v25, 0xff, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v26, 24, v23
	v_mul_lo_u16 v24, 0xab, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u16 v25, 0xab, v25
	v_mul_hi_u32 v26, 0xaaaaaaab, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v24, 12, v24
	v_lshrrev_b16 v25, 12, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 4, v26
	v_and_b32_e32 v24, 0xffff, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v25, 0xffff, v25
	v_add_nc_u32_e32 v26, -1, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v24, -1, v24
	v_add_nc_u32_e32 v25, -1, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or3_b32 v24, v24, v26, v25
	v_cmpx_eq_u32_e32 0, v24
	s_cbranch_execz .LBB0_61
; %bb.54:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mul_hi_i32 v24, 0x55555556, v23
	v_bfe_i32 v25, v21, 0, 8
	v_bfe_i32 v26, v22, 0, 8
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u16 v25, 0x56, v25
	v_mul_lo_u16 v26, 0x56, v26
	v_lshrrev_b32_e32 v27, 31, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v28, 15, v25
	v_lshrrev_b16 v25, 8, v25
	v_add_nc_u32_e32 v24, v24, v27
	v_lshrrev_b16 v27, 15, v26
	v_lshrrev_b16 v26, 8, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u16 v25, v25, v28
	v_lshl_add_u32 v29, v24, 1, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u16 v26, v26, v27
	v_mul_lo_u16 v27, v25, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v23, v23, v29
	v_mul_lo_u16 v28, v26, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v21, v21, v27
	v_mul_lo_u32 v23, 0x1200, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v22, v22, v28
	v_bfe_i32 v21, v21, 0, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v22, v22, 0, 8
	v_and_or_b32 v23, 0xff, v25, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v21, 9, v21
	v_and_b32_e32 v25, 0xff, v26
	v_mul_i32_i24_e32 v22, 0x600, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v23, v24, 6, v23
	v_lshlrev_b32_e32 v24, 3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v21, v23, v21, v22
	v_add_nc_u32_e32 v21, v21, v24
	v_and_b32_e32 v24, 64, v17
	ds_load_u8 v22, v21
	s_waitcnt lgkmcnt(0)
	v_and_b32_e32 v23, 64, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, v23, v24
	v_cmpx_ne_u32_e32 0x80, v25
	s_cbranch_execz .LBB0_60
; %bb.55:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b32_e32 v23, 11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v23, v8
	v_lshrrev_b32_e32 v23, 19, v5
	v_lshrrev_b32_e32 v26, 8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v23, v26, v23
	v_xor3_b32 v23, v23, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 1, v23
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v24
	v_cndmask_b32_e64 v24, 0, 1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v24, v8, vcc_lo
	v_and_b32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v8
	v_and_b32_e32 v8, 48, v20
                                        ; implicit-def: $vgpr20
	s_xor_b32 s20, vcc_lo, -1
	s_and_saveexec_b32 s21, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s21
; %bb.56:                               ;   in Loop: Header=BB0_14 Depth=1
	v_lshlrev_b32_e32 v17, 1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v8, v17, 32, v8
                                        ; implicit-def: $vgpr17
	v_or3_b32 v20, v8, v19, 64
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr8
; %bb.57:                               ; %Flow539
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s20, s20
; %bb.58:                               ;   in Loop: Header=BB0_14 Depth=1
	v_and_b32_e32 v20, 0xff, v22
	v_lshlrev_b32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v8, v20, 63, v8
	v_and_or_b32 v20, 0x70, v17, v19
	v_or_b32_e32 v22, 64, v8
; %bb.59:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_dual_mov_b32 v17, v5 :: v_dual_mov_b32 v8, v7
	v_mov_b32_e32 v19, v6
	v_mov_b32_e32 v5, v23
	ds_store_b8 v18, v15
	ds_store_b8 v16, v20
	ds_store_b8 v21, v22
	v_dual_mov_b32 v6, v17 :: v_dual_mov_b32 v7, v19
.LBB0_60:                               ; %Flow540
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_61:                               ; %Flow541
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_62:                               ; %Flow544
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_63:                               ; %Flow545
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_64:                               ; %Flow546
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_65:                               ; %Flow547
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_66:                               ; %_Z9TransBackPciPjR15HIP_vector_typeIjLj4EE.exit
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s2, s2, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s2, s1
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_14
.LBB0_67:                               ; %._crit_edge321
	v_cvt_f32_u32_e32 v11, s18
	v_cvt_f32_u32_e32 v12, s19
	s_sub_i32 s1, 0, s18
	s_mul_i32 s4, s19, s18
	s_mul_hi_i32 s10, s17, 0x38e38e39
	v_rcp_iflag_f32_e32 v11, v11
	v_rcp_iflag_f32_e32 v12, v12
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v11, 0x4f7ffffe, v11 :: v_dual_mul_f32 v12, 0x4f7ffffe, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v11, v11
	v_cvt_u32_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v11
	v_cvt_f32_u32_e32 v11, s4
	v_readfirstlane_b32 s6, v12
	v_cvt_f32_u32_e32 v12, s12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_mul_i32 s1, s1, s0
	v_rcp_iflag_f32_e32 v11, v11
	s_mul_hi_u32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s0, s1
	s_mul_hi_u32 s0, s15, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s2, s0, s18
	s_add_i32 s3, s0, 1
	s_sub_i32 s2, s15, s2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	s_sub_i32 s5, s2, s18
	s_cmp_ge_u32 s2, s18
	s_cselect_b32 s0, s3, s0
	s_cselect_b32 s2, s5, s2
	s_add_i32 s3, s0, 1
	s_cmp_ge_u32 s2, s18
	v_cvt_u32_f32_e32 v11, v11
	s_cselect_b32 s0, s3, s0
	s_sub_i32 s2, 0, s19
	s_mul_i32 s5, s0, s18
	s_mul_i32 s2, s2, s6
	s_sub_i32 s5, s15, s5
	s_mul_hi_u32 s2, s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s6, s2
	v_readfirstlane_b32 s6, v11
	s_mul_hi_u32 s3, s0, s2
	v_rcp_iflag_f32_e32 v11, v12
	s_mul_i32 s3, s3, s19
	s_sub_i32 s0, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s3, s0, s19
	s_cmp_ge_u32 s0, s19
	s_cselect_b32 s0, s3, s0
	s_sub_i32 s3, s0, s19
	s_cmp_ge_u32 s0, s19
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, 0x4f7ffffe, v11
	s_cselect_b32 s0, s3, s0
	s_sub_i32 s3, 0, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s3, s6
	v_cvt_u32_f32_e32 v11, v11
	s_mul_hi_u32 s7, s6, s3
	s_mov_b32 s3, 0
	s_add_i32 s6, s6, s7
	s_mul_hi_i32 s7, s17, 0x2aaaaaab
	s_mul_hi_u32 s6, s15, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s6, s4
	s_add_i32 s13, s6, 1
	s_sub_i32 s11, s15, s11
	s_sub_i32 s14, s11, s4
	s_cmp_ge_u32 s11, s4
	s_cselect_b32 s6, s13, s6
	s_cselect_b32 s11, s14, s11
	s_add_i32 s13, s6, 1
	s_cmp_ge_u32 s11, s4
	v_readfirstlane_b32 s14, v11
	s_cselect_b32 s11, s13, s6
	s_lshr_b32 s6, s7, 31
	s_ashr_i32 s7, s7, 2
	s_lshr_b32 s13, s10, 31
	s_ashr_i32 s10, s10, 7
	s_add_i32 s15, s7, s6
	s_add_i32 s6, s10, s13
	s_mul_hi_i32 s13, s15, 0x2aaaaaab
	s_add_i32 s4, s5, s18
	s_add_i32 s5, s0, s19
	s_sub_i32 s0, 0, s12
	s_lshr_b32 s16, s13, 31
	s_ashr_i32 s13, s13, 2
	s_mul_i32 s0, s0, s14
	s_add_i32 s13, s13, s16
	s_add_i32 s7, s11, s12
	s_mul_i32 s11, s15, 24
	s_mul_hi_u32 s0, s14, s0
	s_mul_i32 s16, s13, 24
	s_sub_i32 s11, s17, s11
	s_add_i32 s13, s14, s0
	s_sub_i32 s14, s15, s16
	s_sub_i32 s10, 24, s6
	s_sub_i32 s15, 24, s11
	s_sub_i32 s16, 24, s14
	s_mov_b32 s17, 0
.LBB0_68:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_70 Depth 2
	s_and_b32 s25, s3, 1
	s_mov_b32 s21, exec_lo
	s_cmp_eq_u32 s25, 0
	s_cselect_b32 s22, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s22, exec_lo
	s_cselect_b32 s0, s15, s11
	s_bitcmp0_b32 s3, 1
	s_cselect_b32 s23, -1, 0
	s_and_b32 s20, s23, exec_lo
	s_cselect_b32 s27, s16, s14
	s_cmp_lt_u32 s3, 4
	s_mul_i32 s28, s0, s27
	s_cselect_b32 s24, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s20, s24, exec_lo
	s_cselect_b32 s20, s10, s6
	s_mul_i32 s20, s28, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s20, v0
	s_cbranch_execz .LBB0_71
; %bb.69:                               ; %.lr.ph332
                                        ;   in Loop: Header=BB0_68 Depth=1
	s_lshr_b32 s26, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s26, s7, s26
	s_mul_hi_u32 s29, s26, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s29, s29, s12
	s_sub_i32 s26, s26, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s29, s26, s12
	s_cmp_ge_u32 s26, s12
	s_cselect_b32 s26, s29, s26
	s_sub_i32 s29, s26, s12
	s_cmp_ge_u32 s26, s12
	s_cselect_b32 s26, s29, s26
	s_bfe_i32 s29, s3, 0x10001
	s_mul_i32 s26, s26, s19
	s_add_i32 s29, s5, s29
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s30, s29, s2
	s_mul_i32 s30, s30, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s29, s29, s30
	s_sub_i32 s30, s29, s19
	s_cmp_ge_u32 s29, s19
	s_cselect_b32 s29, s30, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s30, s29, s19
	s_cmp_ge_u32 s29, s19
	s_cselect_b32 s29, s30, s29
	s_sub_i32 s25, s4, s25
	s_add_i32 s26, s26, s29
	s_mul_hi_u32 s30, s25, s1
	s_mul_i32 s26, s26, s18
	s_mul_i32 s30, s30, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s25, s25, s30
	s_sub_i32 s29, s25, s18
	s_cmp_ge_u32 s25, s18
	s_cselect_b32 s25, s29, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s29, s25, s18
	s_cmp_ge_u32 s25, s18
	s_cselect_b32 s25, s29, s25
	s_add_i32 s30, s26, s25
	s_and_b32 s22, s22, exec_lo
	s_cselect_b32 s22, s11, 0
	s_and_b32 s23, s23, exec_lo
	s_cselect_b32 s23, s14, 0
	s_and_b32 s24, s24, exec_lo
	s_cselect_b32 s24, s6, 0
	s_ashr_i32 s25, s0, 31
	s_ashr_i32 s29, s27, 31
	s_ashr_i32 s26, s28, 31
	s_add_i32 s31, s0, s25
	s_add_i32 s33, s27, s29
	s_add_i32 s34, s28, s26
	s_xor_b32 s27, s31, s25
	s_xor_b32 s28, s33, s29
	v_cvt_f32_u32_e32 v11, s27
	v_cvt_f32_u32_e32 v12, s28
	s_xor_b32 s29, s34, s26
	s_sub_i32 s33, 0, s28
	v_cvt_f32_u32_e32 v13, s29
	v_rcp_iflag_f32_e32 v11, v11
	v_rcp_iflag_f32_e32 v12, v12
	s_sub_i32 s31, 0, s27
	s_sub_i32 s34, 0, s29
	v_rcp_iflag_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v11, 0x4f7ffffe, v11 :: v_dual_mul_f32 v12, 0x4f7ffffe, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v11, v11
	v_cvt_u32_f32_e32 v12, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v14, s31, v11
	v_mul_lo_u32 v15, s33, v12
	s_mul_i32 s31, s30, 0x3600
	s_mov_b32 s30, 0
	s_add_i32 s31, s31, s17
	s_sub_i32 s33, 0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v14, v11, v14
	v_mul_hi_u32 v15, v12, v15
	v_mul_f32_e32 v13, 0x4f7ffffe, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v14, v0 :: v_dual_add_nc_u32 v11, v11, v14
	v_add_nc_u32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v13, v13
	v_mul_lo_u32 v16, s34, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v13, v16
	v_add_nc_u32_e32 v13, v13, v16
.LBB0_70:                               ;   Parent Loop BB0_68 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mul_hi_u32 v15, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v19, v14, v13
	v_mul_lo_u32 v16, v15, s27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, 1, v19
	v_sub_nc_u32_e32 v16, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s27, v16
	v_cmp_le_u32_e32 vcc_lo, s27, v16
	v_dual_cndmask_b32 v16, v16, v18 :: v_dual_add_nc_u32 v17, 1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s27, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, 1, v15
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, s25, v15
	v_subrev_nc_u32_e32 v15, s25, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_nc_u32_e32 v17, v15, v16
	v_mul_lo_u32 v15, s33, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v17, v17, v16
	v_add3_u32 v15, s22, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, v17, v12
	v_mul_lo_u32 v18, v18, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v18
	v_mul_lo_u32 v18, v19, s29
	v_subrev_nc_u32_e32 v21, s28, v17
	v_cmp_le_u32_e32 vcc_lo, s28, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v18, v14, v18
	v_cndmask_b32_e32 v17, v17, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v21, s29, v18
	v_cmp_le_u32_e32 vcc_lo, s29, v18
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_subrev_nc_u32_e32 v20, s28, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v18, v18, v21, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s28, v17
	v_add_nc_u32_e32 v21, 1, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v17, v17, v20, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s29, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v19, v21, vcc_lo
	v_xor_b32_e32 v17, v17, v16
	v_mul_hi_i32 v19, 0x55555556, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, s26, v18
	v_sub_nc_u32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v17, s26, v18
	v_add_nc_u32_e32 v16, s23, v16
	v_lshrrev_b32_e32 v22, 31, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, s24, v17
	v_mul_hi_i32 v18, 0x55555556, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v19, v19, v22
	v_mul_hi_i32 v20, 0x55555556, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v22, v19, 1, v19
	v_lshrrev_b32_e32 v21, 31, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v15, v15, v22
	v_lshrrev_b32_e32 v23, 31, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, v18, v21
	v_lshl_add_u32 v15, v15, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v20, v20, v23
	v_lshl_add_u32 v21, v18, 1, v18
	v_lshlrev_b32_e32 v18, 3, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v23, v20, 1, v20
	v_sub_nc_u32_e32 v16, v16, v21
	v_lshlrev_b32_e32 v19, 6, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v17, v17, v23
	v_mul_lo_u32 v16, 0x600, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v17, 0x1200, v17
	v_add3_u32 v15, v15, v16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add3_u32 v15, v15, v17, v19
	ds_load_u8 v17, v15
	v_add_nc_u32_e32 v15, s31, v14
	v_add_nc_u32_e32 v14, 0x200, v14
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_u32 v15, vcc_lo, s8, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e64 s0, s20, v14
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s30, s0, s30
	s_waitcnt lgkmcnt(0)
	global_store_b8 v[15:16], v17, off
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB0_70
.LBB0_71:                               ; %Flow538
                                        ;   in Loop: Header=BB0_68 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_add_i32 s3, s3, 1
	s_add_i32 s17, s20, s17
	s_cmp_eq_u32 s3, 8
	s_cbranch_scc0 .LBB0_68
; %bb.72:
	s_clause 0x1
	global_store_b128 v[9:10], v[5:8], off
	global_store_b128 v[9:10], v[1:4], off offset:16
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
		.amdhsa_group_segment_fixed_size 13824
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, .Lfunc_end0-_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9348
; NumSgprs: 37
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 13824 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 13824
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
    .private_segment_fixed_size: 0
    .sgpr_count:     37
    .sgpr_spill_count: 0
    .symbol:         _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
