#include <cuda.h>
#include <stdio.h>
#include <iostream>
#include <chrono>
using namespace std;

__global__ void add(int *a, int *b)
{
    for(int i = 0; i < 1000000; i++)
        a[i] += b[i];
}
void addCPU(int *a, int *b)
{
    for(int i = 0; i < 1000000; i++)
        a[i] += b[i];
}
int main()
{
    std::chrono::_V2::system_clock::time_point checkpoint[10];
    int n = 1000000;
    int *a = (int *)malloc(n * sizeof(int));
    int *b = (int *)malloc(n * sizeof(int));
    int *da, *db;

    srand(time(NULL));
    for(int i = 0; i < n; i++)
    {
        a[i] = rand() % 152;
        b[i] = rand() % 314;
    }

    cudaMalloc(&da, sizeof(int) * n);
    cudaMalloc(&db, sizeof(int) * n);
    cudaMemcpy(da, a, sizeof(int) * n, cudaMemcpyHostToDevice);
    cudaMemcpy(db, b, sizeof(int) * n, cudaMemcpyHostToDevice);

    checkpoint[0] = std::chrono::high_resolution_clock::now();
    add<<<1,1>>>(da, db);
    cudaDeviceSynchronize();
    checkpoint[1] = std::chrono::high_resolution_clock::now();
    addCPU(a, b);
    checkpoint[2] = std::chrono::high_resolution_clock::now();

    auto x = std::chrono::duration_cast<std::chrono::microseconds>(checkpoint[1] - checkpoint[0]).count();
    auto y = std::chrono::duration_cast<std::chrono::microseconds>(checkpoint[2] - checkpoint[1]).count();

    cout << "Your single CPU thread is "<<((float)x)/y<<" times faster than your single GPU thread."<< endl;
    return 0;
}


	.file	"tmpxft_00370848_00000000-6_comapre_cpu_gpu.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3744:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3744:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6addCPUPiS_
	.type	_Z6addCPUPiS_, @function
_Z6addCPUPiS_:
.LFB3734:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	movl	(%rsi,%rax), %edx
	addl	%edx, (%rdi,%rax)
	addq	$4, %rax
	cmpq	$4000000, %rax
	jne	.L3
	ret
	.cfi_endproc
.LFE3734:
	.size	_Z6addCPUPiS_, .-_Z6addCPUPiS_
	.globl	_Z24__device_stub__Z3addPiS_PiS_
	.type	_Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB3766:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z3addPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L6:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3766:
	.size	_Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
	.globl	_Z3addPiS_
	.type	_Z3addPiS_, @function
_Z3addPiS_:
.LFB3767:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z3addPiS_PiS_
	.cfi_endproc
.LFE3767:
	.size	_Z3addPiS_, .-_Z3addPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Your single CPU thread is "
.LC1:
	.string	" times faster than your single GPU thread."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3735:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$4000000, %edi
	movl	$152, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 176
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4000000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, %r12
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L12:
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, 0(%rbp,%rbx)
	call	rand@PLT
	movl	$314, %ecx
	cltd
	idivl	%ecx
	movl	%edx, (%r12,%rbx)
	addq	$4, %rbx
	cmpq	$4000000, %rbx
	jne	.L12
	movq	%rsp, %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4000000, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4000000, %edx
	call	cudaMemcpy@PLT
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rax, %r13
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z24__device_stub__Z3addPiS_PiS_
.L13:
	call	cudaDeviceSynchronize@PLT
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movl	$1000, %r12d
	movq	%rax, %rbx
	call	_Z6addCPUPiS_
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%rbx, %rax
	cqto
	idivq	%r12
	movq	%rax, %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtsi2ssq	%rbp, %xmm1
	movq	%rax, %rdi
	movq	%rbx, %rax
	subq	%r13, %rax
	cqto
	idivq	%r12
	cvtsi2ssq	%rax, %xmm0
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$136, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3735:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z3addPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3769:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3addPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3769:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <chrono>
using namespace std;

__global__ void add(int *a, int *b)
{
    for(int i = 0; i < 1000000; i++)
        a[i] += b[i];
}
void addCPU(int *a, int *b)
{
    for(int i = 0; i < 1000000; i++)
        a[i] += b[i];
}
int main()
{
    std::chrono::_V2::system_clock::time_point checkpoint[10];
    int n = 1000000;
    int *a = (int *)malloc(n * sizeof(int));
    int *b = (int *)malloc(n * sizeof(int));
    int *da, *db;

    srand(time(NULL));
    for(int i = 0; i < n; i++)
    {
        a[i] = rand() % 152;
        b[i] = rand() % 314;
    }

    hipMalloc(&da, sizeof(int) * n);
    hipMalloc(&db, sizeof(int) * n);
    hipMemcpy(da, a, sizeof(int) * n, hipMemcpyHostToDevice);
    hipMemcpy(db, b, sizeof(int) * n, hipMemcpyHostToDevice);

    checkpoint[0] = std::chrono::high_resolution_clock::now();
    add<<<1,1>>>(da, db);
    hipDeviceSynchronize();
    checkpoint[1] = std::chrono::high_resolution_clock::now();
    addCPU(a, b);
    checkpoint[2] = std::chrono::high_resolution_clock::now();

    auto x = std::chrono::duration_cast<std::chrono::microseconds>(checkpoint[1] - checkpoint[0]).count();
    auto y = std::chrono::duration_cast<std::chrono::microseconds>(checkpoint[2] - checkpoint[1]).count();

    cout << "Your single CPU thread is "<<((float)x)/y<<" times faster than your single GPU thread."<< endl;
    return 0;
}


	.text
	.file	"comapre_cpu_gpu.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__addPiS_      # -- Begin function _Z18__device_stub__addPiS_
	.type	_Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_:             # @_Z18__device_stub__addPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__addPiS_, .Lfunc_end0-_Z18__device_stub__addPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z6addCPUPiS_                   # -- Begin function _Z6addCPUPiS_
	.type	_Z6addCPUPiS_,@function
_Z6addCPUPiS_:                          # @_Z6addCPUPiS_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	(%rsi,%rax,4), %ecx
	addl	%ecx, (%rdi,%rax,4)
	incq	%rax
	cmpq	$1000000, %rax                  # imm = 0xF4240
	jne	.LBB1_1
# %bb.2:
	retq
.Lfunc_end1:
	.size	_Z6addCPUPiS_, .Lfunc_end1-_Z6addCPUPiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %rbx
	movl	$4000000, %edi                  # imm = 0x3D0900
	callq	malloc
	movq	%rax, %r14
	xorl	%r15d, %r15d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1808407283, %rax, %rcx         # imm = 0x6BCA1AF3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$152, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%rbx,%r15,4)
	callq	rand
	cltq
	imulq	$875407347, %rax, %rcx          # imm = 0x342DA7F3
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$38, %rcx
	addl	%edx, %ecx
	imull	$314, %ecx, %ecx                # imm = 0x13A
	subl	%ecx, %eax
	movl	%eax, (%r14,%r15,4)
	incq	%r15
	cmpq	$1000000, %r15                  # imm = 0xF4240
	jne	.LBB2_1
# %bb.2:
	leaq	8(%rsp), %r15
	movl	$4000000, %esi                  # imm = 0x3D0900
	movq	%r15, %rdi
	callq	hipMalloc
	movq	%rsp, %r12
	movl	$4000000, %esi                  # imm = 0x3D0900
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$4000000, %edx                  # imm = 0x3D0900
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %r15
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z18__device_stub__addPiS_
.LBB2_4:
	callq	hipDeviceSynchronize
	xorl	%r13d, %r13d
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %r12
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movl	(%r14,%r13,4), %eax
	addl	%eax, (%rbx,%r13,4)
	incq	%r13
	cmpq	$1000000, %r13                  # imm = 0xF4240
	jne	.LBB2_5
# %bb.6:                                # %_Z6addCPUPiS_.exit
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rcx
	subq	%r12, %rcx
	subq	%r15, %r12
	movabsq	$2361183241434822607, %rsi      # imm = 0x20C49BA5E353F7CF
	movq	%r12, %rax
	imulq	%rsi
	movq	%rdx, %rbx
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$7, %rbx
	addq	%rax, %rbx
	movq	%rcx, %rax
	imulq	%rsi
	movq	%rdx, %r14
	movq	%rdx, %rax
	shrq	$63, %rax
	sarq	$7, %r14
	addq	%rax, %r14
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtsi2ss	%rbx, %xmm0
	cvtsi2ss	%r14, %xmm1
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movl	$42, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addPiS_,@object              # @_Z3addPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z3addPiS_
	.p2align	3, 0x0
_Z3addPiS_:
	.quad	_Z18__device_stub__addPiS_
	.size	_Z3addPiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Your single CPU thread is "
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" times faster than your single GPU thread."
	.size	.L.str.1, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3addPiS_"
	.size	.L__unnamed_1, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addPiS_
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addPiS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addPiS_              ; -- Begin function _Z3addPiS_
	.globl	_Z3addPiS_
	.p2align	8
	.type	_Z3addPiS_,@function
_Z3addPiS_:                             ; @_Z3addPiS_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b64 s[4:5], 0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s2, s4
	s_addc_u32 s7, s3, s5
	s_add_u32 s8, s0, s4
	s_addc_u32 s9, s1, s5
	s_clause 0x1
	global_load_b32 v1, v0, s[6:7]
	global_load_b32 v2, v0, s[8:9]
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s4, 0x3d0900
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v2, v1
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 10
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addPiS_, .Lfunc_end0-_Z3addPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 104
; NumSgprs: 10
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z3addPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
