#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;

//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;

//Contents of the A matrix should already be in U

//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!

// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}

//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();

//Elimination step

int istart = ( k + 1 )  +  tx * ops_per_thread;
int iend = istart + ops_per_thread;

for (i = istart; i < iend; i++) {
//Do work  for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}


//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}

//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();




//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;

//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work  for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}


//Don't sync, will sync outside here
}
	.file	"tmpxft_002525be_00000000-6_chol_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z11chol_kernelPfiPfi
	.type	_Z32__device_stub__Z11chol_kernelPfiPfi, @function
_Z32__device_stub__Z11chol_kernelPfiPfi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11chol_kernelPfi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z32__device_stub__Z11chol_kernelPfiPfi, .-_Z32__device_stub__Z11chol_kernelPfiPfi
	.globl	_Z11chol_kernelPfi
	.type	_Z11chol_kernelPfi, @function
_Z11chol_kernelPfi:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z11chol_kernelPfiPfi
	.cfi_endproc
.LFE2033:
	.size	_Z11chol_kernelPfi, .-_Z11chol_kernelPfi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11chol_kernelPfi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11chol_kernelPfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void chol_kernel(float * U, int ops_per_thread) {
//Determine the boundaries for this thread
//Get a thread identifier
int tx = blockIdx.x * blockDim.x + threadIdx.x;

//Iterators
unsigned int i, j, k;
//unsigned int size = MATRIX_SIZE*MATRIX_SIZE;
unsigned int num_rows = MATRIX_SIZE;

//Contents of the A matrix should already be in U

//Perform the Cholesky decomposition in place on the U matrix
for (k = 0; k < num_rows; k++) {
//Only one thread does squre root and division
if (tx == 0) {
// Take the square root of the diagonal element
U[k * num_rows + k] = sqrt(U[k * num_rows + k]);
//Don't bother doing check...live life on the edge!

// Division step
for (j = (k + 1); j < num_rows; j++) {
U[k * num_rows + j] /= U[k * num_rows + k]; // Division step
}
}

//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();

//Elimination step

int istart = ( k + 1 )  +  tx * ops_per_thread;
int iend = istart + ops_per_thread;

for (i = istart; i < iend; i++) {
//Do work  for this i iteration
for (j = i; j < num_rows; j++) {
U[i * num_rows + j] -= U[k * num_rows + i] * U[k * num_rows + j];
}
}


//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();
}

//Sync threads!!!!! (only one thread block so, ok)
__syncthreads();




//As the final step, zero out the lower triangular portion of U
//for(i = 0; i < U.num_rows; i++)
//Each thread does so many iterations of zero out loop
//Starting index for this thread
int istart = tx * ops_per_thread;
//Ending index for this thread
int iend = istart + ops_per_thread;

//Check boundaries, else do nothing
for (i = istart; i < iend; i++) {
//Do work  for this i iteration
for (j = 0; j < i; j++) {
U[i * num_rows + j] = 0.0;
}
}


//Don't sync, will sync outside here
}
	.text
	.file	"chol_kernel.hip"
	.globl	_Z26__device_stub__chol_kernelPfi # -- Begin function _Z26__device_stub__chol_kernelPfi
	.type	_Z26__device_stub__chol_kernelPfi,@function
_Z26__device_stub__chol_kernelPfi:      # @_Z26__device_stub__chol_kernelPfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11chol_kernelPfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__chol_kernelPfi, .Lfunc_end0-_Z26__device_stub__chol_kernelPfi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11chol_kernelPfi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11chol_kernelPfi,@object      # @_Z11chol_kernelPfi
	.section	.rodata,"a",@progbits
	.globl	_Z11chol_kernelPfi
	.p2align	3, 0x0
_Z11chol_kernelPfi:
	.quad	_Z26__device_stub__chol_kernelPfi
	.size	_Z11chol_kernelPfi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11chol_kernelPfi"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__chol_kernelPfi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11chol_kernelPfi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11chol_kernelPfi      ; -- Begin function _Z11chol_kernelPfi
	.globl	_Z11chol_kernelPfi
	.p2align	8
	.type	_Z11chol_kernelPfi,@function
_Z11chol_kernelPfi:                     ; @_Z11chol_kernelPfi
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s12, s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x0
	s_movk_i32 s1, 0x801
	s_mov_b32 s5, 0
	s_mov_b32 s13, -1
	s_mov_b32 s14, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_add_u32 s6, s2, 4
	s_addc_u32 s7, s3, 0
	v_mov_b32_e32 v2, 0
	v_mul_lo_u32 v8, v1, s12
	v_cmp_eq_u32_e64 s0, 0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, s12, v8
	v_mad_u64_u32 v[0:1], null, v8, s1, 0x801
	v_dual_mov_b32 v11, v8 :: v_dual_add_nc_u32 v10, 1, v8
	v_mov_b32_e32 v12, v9
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_4
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	s_mul_i32 s4, s14, 0x801
	s_mov_b64 s[10:11], s[6:7]
	s_lshl_b64 s[8:9], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s2, s8
	s_addc_u32 s9, s3, s9
	s_cmpk_gt_u32 s14, 0x7fe
	global_load_b32 v1, v2, s[8:9]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v3, 0x4f800000, v1
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_sqrt_f32_e32 v3, v1
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v4, v3, v1
	v_fma_f32 v7, -v5, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s1, 0, v6
	v_cndmask_b32_e64 v3, v3, v4, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, 0, v7
	v_cndmask_b32_e64 v3, v3, v5, s1
	s_mov_b32 s1, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x37800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v1, 0x260
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	global_store_b32 v2, v1, s[8:9]
	s_cbranch_scc1 .LBB0_4
.LBB0_3:                                ; %.lr.ph
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b32 v1, v2, s[8:9]
	global_load_b32 v3, v2, s[10:11]
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v1, v1, v3
	v_div_scale_f32 v7, vcc_lo, v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v13, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v13, v5
	v_fma_f32 v4, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v6
	v_div_fixup_f32 v1, v4, v1, v3
	global_store_b32 v2, v1, s[10:11]
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_lt_u32 s1, 0x7fe
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %.loopexit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_add_i32 s4, s14, 1
	s_mov_b32 s8, exec_lo
	v_add_nc_u32_e32 v13, s4, v8
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_add_nc_u32_e32 v1, s12, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v13, v1
	s_cbranch_execz .LBB0_10
; %bb.5:                                ; %.preheader67.lr.ph
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v14, v10
	v_mov_b32_e32 v15, v11
	s_lshl_b32 s9, s14, 11
	s_mov_b32 s10, 0
.LBB0_6:                                ; %.preheader67
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
	s_mov_b32 s11, exec_lo
	v_cmpx_gt_u32_e32 0x800, v13
	s_cbranch_execz .LBB0_9
; %bb.7:                                ; %.lr.ph70
                                        ;   in Loop: Header=BB0_6 Depth=2
	v_mov_b32_e32 v4, v2
	v_or_b32_e32 v1, s9, v13
	s_mov_b32 s14, 0
	v_mov_b32_e32 v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v1, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
.LBB0_8:                                ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_lshlrev_b64 v[17:18], 2, v[1:2]
	global_load_b32 v19, v[6:7], off
	global_load_b32 v20, v[4:5], off
	v_add_nc_u32_e32 v16, 1, v16
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v17, vcc_lo, s2, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_lt_u32_e32 vcc_lo, 0x7fe, v16
	global_load_b32 v17, v[17:18], off
	s_or_b32 s14, vcc_lo, s14
	s_waitcnt vmcnt(0)
	v_fma_f32 v17, -v19, v17, v20
	global_store_b32 v[4:5], v17, off
	v_add_co_u32 v4, s1, v4, 4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s1, 0, v5, s1
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_8
.LBB0_9:                                ; %Flow116
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v1, 1, v13
	v_cmp_eq_u32_e32 vcc_lo, v13, v12
	v_add_nc_u32_e32 v15, 1, v15
	v_add_nc_u32_e32 v14, 1, v14
	v_add_nc_u32_e32 v3, 0x801, v3
	v_mov_b32_e32 v13, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_6
.LBB0_10:                               ; %Flow118
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_add_nc_u32_e32 v12, 1, v12
	v_add_nc_u32_e32 v11, 1, v11
	v_add_nc_u32_e32 v10, 0x801, v10
	v_add_nc_u32_e32 v0, 0x801, v0
	s_add_u32 s6, s6, 0x2004
	s_addc_u32 s7, s7, 0
	s_add_i32 s13, s13, 1
	s_cmpk_lg_i32 s4, 0x800
	s_mov_b32 s14, s4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_1
; %bb.11:
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u32_e64 v8, v9
	s_cbranch_execz .LBB0_17
; %bb.12:                               ; %.preheader.preheader
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 11, v8
	s_mov_b32 s1, 0
.LBB0_13:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u32_e32 0, v8
	s_cbranch_execz .LBB0_16
; %bb.14:                               ; %.lr.ph76
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_mov_b32 s5, 0
	s_mov_b32 s6, 0
.LBB0_15:                               ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v0, s6, v2
	s_add_i32 s6, s6, 1
	v_cmp_ge_u32_e32 vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	s_or_b32 s5, vcc_lo, s5
	v_add_co_u32 v3, s0, s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
	global_store_b32 v[3:4], v1, off
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow112
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_add_nc_u32_e32 v8, 1, v8
	v_add_nc_u32_e32 v2, 0x800, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, v8, v9
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_13
.LBB0_17:                               ; %._crit_edge79
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11chol_kernelPfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11chol_kernelPfi, .Lfunc_end0-_Z11chol_kernelPfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1052
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11chol_kernelPfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11chol_kernelPfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
