#include<stdio.h>
#include<cstdlib>

__global__ void race(volatile int *arr, size_t size, int n, int *out) {
  int gid = threadIdx.x + blockDim.x * blockIdx.x;
  int ptr = gid;
  if (ptr > size) ptr = 0;
  for (int i = 0; i < n; i++) {
    ptr = arr[size * gid + ptr];
  }
  out[gid] = ptr;
}

int main(int argc, char *argv[]) {
  int grid_size=10, block_size=128, n=100, step=100;
  if (argc > 4) {
    sscanf(argv[1], "%d", &grid_size);
    sscanf(argv[2], "%d", &block_size);
    sscanf(argv[3], "%d", &n);
    sscanf(argv[4], "%d", &step);
  }
  size_t size = n;
  size_t total_size = size * grid_size * block_size * sizeof(int);
  printf("size = %zd KB\n", total_size / 1024);
  int *arr = new int[size * grid_size * block_size];
  int *ra = new int[size];
  int *out = new int[grid_size * block_size];
  for (size_t tid = 0; tid < grid_size * block_size; tid++) {
    int *arr2 = arr + tid * size;
    for (int i = 0; i < n; i++) {
      ra[i] = i;
    }
    for (int i = 1; i < n; i++) {
      int r = rand()%(i+1);
      int tmp = ra[i];
      ra[i] = ra[r];
      ra[r] = tmp;
    }
    /*for (int i = 1; i < n; i++) {
      arr2[ra[i-1]] = ra[i];
    }
    arr2[ra[n-1]] = ra[0];*/
    for (int i = 1; i < n; i++) {
      arr2[i-1] = i;
    }
    arr2[n-1] = 0;
  }
  int *garr, *gout;
  cudaMalloc(&garr, total_size);
  cudaMalloc(&gout, sizeof(int) * grid_size * block_size);
  cudaMemcpy(garr, arr, total_size, cudaMemcpyHostToDevice);
  race<<<grid_size, block_size>>>(garr, size, step, gout);
  cudaMemcpy(out, gout, sizeof(int) * grid_size * block_size, cudaMemcpyDeviceToHost);
  return 0;
}
	.file	"tmpxft_002bb986_00000000-6_rnd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z4racePVimiPiPVimiPi
	.type	_Z28__device_stub__Z4racePVimiPiPVimiPi, @function
_Z28__device_stub__Z4racePVimiPiPVimiPi:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z4racePVimiPi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z4racePVimiPiPVimiPi, .-_Z28__device_stub__Z4racePVimiPiPVimiPi
	.globl	_Z4racePVimiPi
	.type	_Z4racePVimiPi, @function
_Z4racePVimiPi:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z4racePVimiPiPVimiPi
	.cfi_endproc
.LFE2053:
	.size	_Z4racePVimiPi, .-_Z4racePVimiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC1:
	.string	"size = %zd KB\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	movl	$10, 32(%rsp)
	movl	$128, 36(%rsp)
	movl	$100, 40(%rsp)
	movl	$100, 44(%rsp)
	cmpl	$4, %edi
	jle	.L9
	leaq	.LC0(%rip), %rbp
	movq	8(%rsi), %rdi
	movq	%rsi, %rbx
	leaq	32(%rsp), %rdx
	movq	%rbp, %rsi
	call	__isoc23_sscanf@PLT
	movq	16(%rbx), %rdi
	leaq	36(%rsp), %rdx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	call	__isoc23_sscanf@PLT
	movq	24(%rbx), %rdi
	leaq	40(%rsp), %rdx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	call	__isoc23_sscanf@PLT
	movq	32(%rbx), %rdi
	leaq	44(%rsp), %rdx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	call	__isoc23_sscanf@PLT
.L9:
	movslq	40(%rsp), %rbp
	movslq	32(%rsp), %rbx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	movabsq	$2305843009213693950, %r14
	movslq	36(%rsp), %rax
	imulq	%rbp, %rbx
	imulq	%rax, %rbx
	leaq	0(,%rbx,4), %rax
	movq	%rax, %rdx
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	shrq	$10, %rdx
	call	__printf_chk@PLT
	movslq	32(%rsp), %rdi
	movslq	36(%rsp), %rax
	imulq	%rbp, %rdi
	imulq	%rax, %rdi
	cmpq	%rdi, %r14
	jb	.L10
	salq	$2, %rdi
	call	_Znam@PLT
	movq	%rax, 16(%rsp)
	cmpq	%rbp, %r14
	jnb	.L11
.L10:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L24
	call	__cxa_throw_bad_array_new_length@PLT
.L11:
	leaq	0(,%rbp,4), %r13
	movq	%r13, %rdi
	call	_Znam@PLT
	movl	32(%rsp), %edi
	imull	36(%rsp), %edi
	movq	%rax, %r15
	movslq	%edi, %rdi
	cmpq	%rdi, %r14
	jb	.L10
	salq	$2, %rdi
	xorl	%r14d, %r14d
	call	_Znam@PLT
	movq	16(%rsp), %rbx
	movq	%rax, 24(%rsp)
.L13:
	movl	32(%rsp), %eax
	imull	36(%rsp), %eax
	cltq
	cmpq	%rax, %r14
	jnb	.L25
	movl	40(%rsp), %edx
	xorl	%eax, %eax
.L14:
	cmpl	%eax, %edx
	jle	.L26
	movl	%eax, (%r15,%rax,4)
	incq	%rax
	jmp	.L14
.L26:
	xorl	%r12d, %r12d
.L16:
	movslq	40(%rsp), %rax
	incq	%r12
	cmpl	%r12d, %eax
	jle	.L27
	call	rand@PLT
	leal	1(%r12), %r9d
	movl	(%r15,%r12,4), %r8d
	cltd
	idivl	%r9d
	movslq	%edx, %rdx
	leaq	(%r15,%rdx,4), %rax
	movl	(%rax), %edx
	movl	%edx, (%r15,%r12,4)
	movl	%r8d, (%rax)
	jmp	.L16
.L27:
	movl	$1, %edx
.L18:
	cmpl	%edx, %eax
	jle	.L28
	movl	%edx, -4(%rbx,%rdx,4)
	incq	%rdx
	jmp	.L18
.L28:
	xorl	%edx, %edx
	incq	%r14
	movl	%edx, -4(%rbx,%rax,4)
	addq	%r13, %rbx
	jmp	.L13
.L25:
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movslq	32(%rsp), %rsi
	movslq	36(%rsp), %rax
	leaq	56(%rsp), %rdi
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	48(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	36(%rsp), %eax
	movl	32(%rsp), %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 76(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movl	84(%rsp), %ecx
	movl	%edx, 64(%rsp)
	movq	76(%rsp), %rdx
	movq	%rax, 68(%rsp)
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	56(%rsp), %rcx
	movl	44(%rsp), %edx
	movq	%rbp, %rsi
	movq	48(%rsp), %rdi
	call	_Z28__device_stub__Z4racePVimiPiPVimiPi
.L21:
	movslq	32(%rsp), %rdx
	movslq	36(%rsp), %rax
	movl	$2, %ecx
	movq	56(%rsp), %rsi
	movq	24(%rsp), %rdi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
.L24:
	call	__stack_chk_fail@PLT
.L22:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z4racePVimiPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4racePVimiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<cstdlib>

__global__ void race(volatile int *arr, size_t size, int n, int *out) {
  int gid = threadIdx.x + blockDim.x * blockIdx.x;
  int ptr = gid;
  if (ptr > size) ptr = 0;
  for (int i = 0; i < n; i++) {
    ptr = arr[size * gid + ptr];
  }
  out[gid] = ptr;
}

int main(int argc, char *argv[]) {
  int grid_size=10, block_size=128, n=100, step=100;
  if (argc > 4) {
    sscanf(argv[1], "%d", &grid_size);
    sscanf(argv[2], "%d", &block_size);
    sscanf(argv[3], "%d", &n);
    sscanf(argv[4], "%d", &step);
  }
  size_t size = n;
  size_t total_size = size * grid_size * block_size * sizeof(int);
  printf("size = %zd KB\n", total_size / 1024);
  int *arr = new int[size * grid_size * block_size];
  int *ra = new int[size];
  int *out = new int[grid_size * block_size];
  for (size_t tid = 0; tid < grid_size * block_size; tid++) {
    int *arr2 = arr + tid * size;
    for (int i = 0; i < n; i++) {
      ra[i] = i;
    }
    for (int i = 1; i < n; i++) {
      int r = rand()%(i+1);
      int tmp = ra[i];
      ra[i] = ra[r];
      ra[r] = tmp;
    }
    /*for (int i = 1; i < n; i++) {
      arr2[ra[i-1]] = ra[i];
    }
    arr2[ra[n-1]] = ra[0];*/
    for (int i = 1; i < n; i++) {
      arr2[i-1] = i;
    }
    arr2[n-1] = 0;
  }
  int *garr, *gout;
  hipMalloc(&garr, total_size);
  hipMalloc(&gout, sizeof(int) * grid_size * block_size);
  hipMemcpy(garr, arr, total_size, hipMemcpyHostToDevice);
  race<<<grid_size, block_size>>>(garr, size, step, gout);
  hipMemcpy(out, gout, sizeof(int) * grid_size * block_size, hipMemcpyDeviceToHost);
  return 0;
}
	.text
	.file	"rnd.hip"
	.globl	_Z19__device_stub__racePVimiPi  # -- Begin function _Z19__device_stub__racePVimiPi
	.type	_Z19__device_stub__racePVimiPi,@function
_Z19__device_stub__racePVimiPi:         # @_Z19__device_stub__racePVimiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4racePVimiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__racePVimiPi, .Lfunc_end0-_Z19__device_stub__racePVimiPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$10, 4(%rsp)
	movl	$128, (%rsp)
	movl	$100, %eax
	movl	%eax, 8(%rsp)
	movl	%eax, 12(%rsp)
	cmpl	$5, %edi
	jl	.LBB1_1
# %bb.2:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	leaq	4(%rsp), %r14
	movl	$.L.str, %esi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	16(%rbx), %rdi
	movq	%rsp, %r15
	movl	$.L.str, %esi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	24(%rbx), %rdi
	leaq	8(%rsp), %r12
	movl	$.L.str, %esi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	32(%rbx), %rdi
	leaq	12(%rsp), %rdx
	movl	$.L.str, %esi
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movl	(%r12), %eax
	movslq	(%r14), %rcx
	movslq	(%r15), %rsi
	jmp	.LBB1_3
.LBB1_1:
	movl	$10, %ecx
	movl	$128, %esi
.LBB1_3:
	imulq	%rcx, %rsi
	movslq	%eax, %rbx
	leaq	(,%rbx,4), %rbp
	imulq	%rbp, %rsi
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	shrq	$10, %rsi
	xorl	%r15d, %r15d
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movslq	4(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	imulq	%rbx, %rax
	movslq	(%rsp), %r12
	imulq	%r12, %rax
	movq	%rax, %rcx
	shrq	$62, %rcx
	shlq	$2, %rax
	negq	%rcx
	sbbq	%r15, %r15
	orq	%rax, %r15
	movq	%r15, %rdi
	callq	_Znam
	movq	%rax, %r14
	testl	%ebx, %ebx
	movq	$-1, %r15
	movq	%rbp, %rdi
	cmovsq	%r15, %rdi
	callq	_Znam
	movq	%rax, %r13
	imulq	16(%rsp), %r12                  # 8-byte Folded Reload
	movq	%r12, %rdi
	shlq	$2, %rdi
	testl	%r12d, %r12d
	cmovsq	%r15, %rdi
	callq	_Znam
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	testl	%r12d, %r12d
	je	.LBB1_15
# %bb.4:                                # %.lr.ph59.preheader
	movl	8(%rsp), %eax
	xorl	%r15d, %r15d
	movq	%r14, %r12
	movq	%r14, 24(%rsp)                  # 8-byte Spill
.LBB1_5:                                # %.lr.ph59
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_7 Depth 2
                                        #     Child Loop BB1_10 Depth 2
                                        #     Child Loop BB1_19 Depth 2
	testl	%eax, %eax
	jle	.LBB1_14
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB1_5 Depth=1
	movl	%eax, %ecx
	xorl	%edx, %edx
.LBB1_7:                                # %.lr.ph
                                        #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%edx, (%r13,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB1_7
# %bb.8:                                # %.preheader51
                                        #   in Loop: Header=BB1_5 Depth=1
	cmpl	$1, %ecx
	je	.LBB1_14
# %bb.9:                                # %.lr.ph54.preheader
                                        #   in Loop: Header=BB1_5 Depth=1
	movq	%rbp, %r14
	movq	%rbx, %rbp
	movl	$1, %ebx
.LBB1_10:                               # %.lr.ph54
                                        #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	leaq	1(%rbx), %rcx
	cltd
	idivl	%ecx
	movl	(%r13,%rbx,4), %eax
	movslq	%edx, %rdx
	movl	(%r13,%rdx,4), %esi
	movl	%esi, (%r13,%rbx,4)
	movl	%eax, (%r13,%rdx,4)
	movslq	8(%rsp), %rax
	movq	%rcx, %rbx
	cmpq	%rax, %rcx
	jl	.LBB1_10
# %bb.11:                               # %.preheader
                                        #   in Loop: Header=BB1_5 Depth=1
	movl	%eax, %eax
	cmpl	$1, %eax
	jle	.LBB1_12
# %bb.18:                               # %.lr.ph56.preheader
                                        #   in Loop: Header=BB1_5 Depth=1
	movl	$1, %ecx
	movq	%rbp, %rbx
.LBB1_19:                               # %.lr.ph56
                                        #   Parent Loop BB1_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ecx, -4(%r12,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB1_19
	jmp	.LBB1_13
.LBB1_12:                               # %.preheader.._crit_edge_crit_edge
                                        #   in Loop: Header=BB1_5 Depth=1
	movq	%rbp, %rbx
.LBB1_13:                               # %._crit_edge.loopexit
                                        #   in Loop: Header=BB1_5 Depth=1
	movq	%r14, %rbp
	movq	24(%rsp), %r14                  # 8-byte Reload
.LBB1_14:                               # %._crit_edge
                                        #   in Loop: Header=BB1_5 Depth=1
	movq	%r15, %rcx
	imulq	%rbx, %rcx
	leaq	(%r14,%rcx,4), %rcx
	movslq	%eax, %rdx
	movl	$0, -4(%rcx,%rdx,4)
	incq	%r15
	movslq	4(%rsp), %rcx
	movslq	(%rsp), %rdx
	imulq	%rcx, %rdx
	addq	%rbp, %r12
	cmpq	%rdx, %r15
	jb	.LBB1_5
.LBB1_15:                               # %._crit_edge60
	leaq	48(%rsp), %r13
	movq	%r13, %rdi
	movq	40(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	4(%rsp), %edi
	movl	(%rsp), %edx
	btsq	$32, %rdi
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.16:
	movq	48(%rsp), %rdi
	movl	12(%rsp), %edx
	movq	32(%rsp), %rcx
	movq	%rbx, %rsi
	callq	_Z19__device_stub__racePVimiPi
.LBB1_17:
	movq	32(%rsp), %rsi
	movslq	4(%rsp), %rax
	movslq	(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4racePVimiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4racePVimiPi,@object          # @_Z4racePVimiPi
	.section	.rodata,"a",@progbits
	.globl	_Z4racePVimiPi
	.p2align	3, 0x0
_Z4racePVimiPi:
	.quad	_Z19__device_stub__racePVimiPi
	.size	_Z4racePVimiPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"size = %zd KB\n"
	.size	.L.str.1, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z4racePVimiPi"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__racePVimiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4racePVimiPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4racePVimiPi          ; -- Begin function _Z4racePVimiPi
	.globl	_Z4racePVimiPi
	.p2align	8
	.type	_Z4racePVimiPi,@function
_Z4racePVimiPi:                         ; @_Z4racePVimiPi
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_cmp_lt_i32 s2, 1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_u64_e32 vcc_lo, s[6:7], v[1:2]
	v_cndmask_b32_e32 v3, 0, v1, vcc_lo
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_mul_lo_u32 v0, v2, s6
	v_mul_lo_u32 v6, v1, s7
	v_mad_u64_u32 v[4:5], null, v1, s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v6, v0
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v4, vcc_lo
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %Flow26
	s_load_b64 s[0:1], s[0:1], 0x18
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4racePVimiPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4racePVimiPi, .Lfunc_end0-_Z4racePVimiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4racePVimiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4racePVimiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
