
extern "C"

//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64

#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7

#define PI 3.14159265359f

//__device__ float calc_p(float rho){
//    return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}

__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
    //int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z

    int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
    int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];

    for (int i = istart; i < iend; i += Block_Size)
    {
        int id = i + threadIdx.x;

        float xi[3];
        float vi[3];
        float rhoi;

        if (id < iend)
        {
            xi[0] = x[3 * id + 0];
            xi[1] = x[3 * id + 1];
            xi[2] = x[3 * id + 2];
            vi[0] = v[3 * id + 0];
            vi[1] = v[3 * id + 1];
            vi[2] = v[3 * id + 2];
            rhoi = rho[id];
        }

        float dx[3];
        float dv[3];
        float r2;
        float r;
        float dW;

        //float pi = calc_p(rhoi);
        float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
        float pj;

        float dV[3] = {0,0,0};

        __shared__ float xj[Block_Size * 3];
        __shared__ float vj[Block_Size * 3];
        __shared__ float rhoj[Block_Size];


        for (int a = -1; a < 2; a++)
        {
            for (int b = -1; b < 2; b++)
            {
                if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
                {
                    continue;
                }

                int Zstart = max((int)blockIdx.z - 1, 0);
                int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);

                int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
                int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];

                for (int j = jstart; j < jend; j += Block_Size)
                {
                    int jd = j + threadIdx.x;
                    if (jd < jend)
                    {
                        xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
                        xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
                        xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
                        vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
                        vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
                        vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
                        rhoj[threadIdx.x] = rho[jd];
                    }
                    __syncthreads();
                    if (id < iend)
                    {
                        for (int k = 0; k < Block_Size; k++)
                        {
                            if (j + k < jend)
                            {
                                dx[0] = xj[3 * k + 0] - xi[0];
                                dx[1] = xj[3 * k + 1] - xi[1];
                                dx[2] = xj[3 * k + 2] - xi[2];

                                dv[0] = vj[3 * k + 0] - vi[0];
                                dv[1] = vj[3 * k + 1] - vi[1];
                                dv[2] = vj[3 * k + 2] - vi[2];

                                r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
                                if (r2 < 1.0)
                                {
                                    r = sqrtf(r2+0.001*h*h);

                                    dW = (1.0 - r);
                                    dW *= dW*dW; //(1-r)^3
                                    dW = -dW*r*20; 
                                    dW *= 21.0 / (2.0 * PI * h * h * h * h);
                                    
                                    //pj = calc_p(rhoj[k]);
                                    pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
                                    
                                    float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
                                    
                                    d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
                                    
                                    d *= m*dW/r;

                                    dV[0] += d*dx[0];
                                    dV[1] += d*dx[1];
                                    dV[2] += d*dx[2];
                                }
                            }
                        }
                    }
                    __syncthreads();
                }
                //ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
            }
        }

        if (id < iend)
        {
            out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
            out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
            out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
        }
    }
}

	.file	"tmpxft_0033ef7f_00000000-6_ker_dv.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
	.type	_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, @function
_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	ker_dv(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, .-_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
	.globl	ker_dv
	.type	ker_dv, @function
ker_dv:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
	.cfi_endproc
.LFE2033:
	.size	ker_dv, .-ker_dv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"ker_dv"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	ker_dv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

extern "C"

//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64

#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7

#define PI 3.14159265359f

//__device__ float calc_p(float rho){
//    return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}

__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
    //int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z

    int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
    int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];

    for (int i = istart; i < iend; i += Block_Size)
    {
        int id = i + threadIdx.x;

        float xi[3];
        float vi[3];
        float rhoi;

        if (id < iend)
        {
            xi[0] = x[3 * id + 0];
            xi[1] = x[3 * id + 1];
            xi[2] = x[3 * id + 2];
            vi[0] = v[3 * id + 0];
            vi[1] = v[3 * id + 1];
            vi[2] = v[3 * id + 2];
            rhoi = rho[id];
        }

        float dx[3];
        float dv[3];
        float r2;
        float r;
        float dW;

        //float pi = calc_p(rhoi);
        float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
        float pj;

        float dV[3] = {0,0,0};

        __shared__ float xj[Block_Size * 3];
        __shared__ float vj[Block_Size * 3];
        __shared__ float rhoj[Block_Size];


        for (int a = -1; a < 2; a++)
        {
            for (int b = -1; b < 2; b++)
            {
                if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
                {
                    continue;
                }

                int Zstart = max((int)blockIdx.z - 1, 0);
                int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);

                int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
                int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];

                for (int j = jstart; j < jend; j += Block_Size)
                {
                    int jd = j + threadIdx.x;
                    if (jd < jend)
                    {
                        xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
                        xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
                        xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
                        vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
                        vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
                        vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
                        rhoj[threadIdx.x] = rho[jd];
                    }
                    __syncthreads();
                    if (id < iend)
                    {
                        for (int k = 0; k < Block_Size; k++)
                        {
                            if (j + k < jend)
                            {
                                dx[0] = xj[3 * k + 0] - xi[0];
                                dx[1] = xj[3 * k + 1] - xi[1];
                                dx[2] = xj[3 * k + 2] - xi[2];

                                dv[0] = vj[3 * k + 0] - vi[0];
                                dv[1] = vj[3 * k + 1] - vi[1];
                                dv[2] = vj[3 * k + 2] - vi[2];

                                r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
                                if (r2 < 1.0)
                                {
                                    r = sqrtf(r2+0.001*h*h);

                                    dW = (1.0 - r);
                                    dW *= dW*dW; //(1-r)^3
                                    dW = -dW*r*20; 
                                    dW *= 21.0 / (2.0 * PI * h * h * h * h);
                                    
                                    //pj = calc_p(rhoj[k]);
                                    pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
                                    
                                    float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
                                    
                                    d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
                                    
                                    d *= m*dW/r;

                                    dV[0] += d*dx[0];
                                    dV[1] += d*dx[1];
                                    dV[2] += d*dx[2];
                                }
                            }
                        }
                    }
                    __syncthreads();
                }
                //ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
            }
        }

        if (id < iend)
        {
            out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
            out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
            out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
        }
    }
}

	.text
	.file	"ker_dv.hip"
	.globl	__device_stub__ker_dv           # -- Begin function __device_stub__ker_dv
	.type	__device_stub__ker_dv,@function
__device_stub__ker_dv:                  # @__device_stub__ker_dv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$ker_dv, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__ker_dv, .Lfunc_end0-__device_stub__ker_dv
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$ker_dv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	ker_dv,@object                  # @ker_dv
	.section	.rodata,"a",@progbits
	.globl	ker_dv
	.p2align	3, 0x0
ker_dv:
	.quad	__device_stub__ker_dv
	.size	ker_dv, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"ker_dv"
	.size	.L__unnamed_1, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__ker_dv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym ker_dv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	ker_dv                  ; -- Begin function ker_dv
	.globl	ker_dv
	.p2align	8
	.type	ker_dv,@function
ker_dv:                                 ; @ker_dv
; %bb.0:
	s_clause 0x1
	s_load_b64 s[16:17], s[0:1], 0x34
	s_load_b64 s[18:19], s[0:1], 0x20
	s_add_u32 s20, s0, 48
	s_addc_u32 s21, s1, 0
	s_lshl_b32 s2, s15, 1
	s_mov_b32 s23, 0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s12, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_mul_i32 s28, s12, s16
	s_mul_i32 s3, s12, s14
	s_mul_i32 s4, s28, s13
	s_add_i32 s2, s3, s2
	s_add_i32 s22, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[22:23], 2
	s_add_u32 s2, s18, s2
	s_addc_u32 s3, s19, s3
	s_load_b64 s[24:25], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s24, s25
	s_cbranch_scc1 .LBB0_25
; %bb.1:                                ; %.lr.ph220
	s_load_b32 s29, s[0:1], 0x28
	s_brev_b32 s2, 6
	s_mov_b32 s3, 0x401921fb
	s_load_b256 s[4:11], s[0:1], 0x0
	s_max_i32 s0, s15, 1
	s_add_i32 s15, s15, 1
	s_add_i32 s1, s17, -1
	s_lshl_b32 s0, s0, 1
	s_min_i32 s1, s15, s1
	v_lshl_add_u32 v19, v0, 2, 0x600
	s_add_i32 s15, s0, -2
	s_lshl_b32 s17, s1, 1
	s_mov_b32 s26, 0xa0b5ed8d
	s_add_u32 s30, s18, 4
	s_mov_b32 s27, 0xbea0c6f7
	s_addc_u32 s31, s19, 0
	s_mov_b32 s33, 0x3e76c4e1
                                        ; implicit-def: $vgpr22
	v_mov_b32_e32 v21, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_f32_e32 v[1:2], s29
	v_mul_f32_e64 v20, s29, s29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[1:2], s[2:3]
	s_mov_b32 s2, 0xd2f1a9fc
	s_mov_b32 s3, 0x3f50624d
	v_mul_f64 v[3:4], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], v[1:2]
	v_mul_f64 v[3:4], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], 0x40350000
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_div_scale_f64 v[9:10], vcc_lo, 0x40350000, v[3:4], 0x40350000
	v_mul_f64 v[11:12], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
	v_mul_f64 v[9:10], v[1:2], s[2:3]
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[9:10], v[1:2]
	v_mul_u32_u24_e32 v1, 3, v0
	v_lshlrev_b32_e32 v17, 2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v18, 0x300, v17
	v_div_fixup_f64 v[9:10], v[5:6], v[3:4], 0x40350000
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr6
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	v_add_nc_u32_e32 v13, s24, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v11, v13, 1, v13
	v_cmp_gt_i32_e64 s0, s25, v13
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[11:12]
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[3:4], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v15, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v4, vcc_lo
	global_load_b96 v[1:3], v[5:6], off
	global_load_b96 v[4:6], v[13:14], off
	global_load_b32 v22, v[15:16], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v13, |v22|
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v13
	v_cndmask_b32_e64 v14, 0, 1, vcc_lo
	v_ldexp_f32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, -1.0, v13
	v_add_f32_e32 v14, 1.0, v13
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v23, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v25, v14, v23 :: v_dual_add_f32 v24, -1.0, v14
	v_fma_f32 v14, v23, v14, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v24
	v_fmac_f32_e32 v14, v23, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v25, v14
	v_sub_f32_e32 v24, v16, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v16, v24 :: v_dual_sub_f32 v25, v13, v25
	v_dual_sub_f32 v13, v16, v13 :: v_dual_sub_f32 v14, v25, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v14, v13
	v_add_f32_e32 v13, v24, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v15, v13
	v_add_f32_e32 v14, v23, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v14, v23
	v_dual_mul_f32 v16, v14, v14 :: v_dual_sub_f32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v14, v14, -v16
	v_add_f32_e32 v23, v13, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v14, v23
	v_add_f32_e32 v23, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v23, v16
	v_dual_fmaak_f32 v24, s33, v23, 0x3e91f4c4 :: v_dual_sub_f32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v24, v23, v24, 0x3ecccdef
	v_mul_f32_e32 v25, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, v23, v24, -v25
	v_fmac_f32_e32 v16, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v24, v25, v16
	v_dual_sub_f32 v25, v24, v25 :: v_dual_add_f32 v26, 0x3f2aaaaa, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v16, v16, v25 :: v_dual_mul_f32 v27, v14, v23
	v_add_f32_e32 v16, 0x31739010, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, v23, v14, -v27
	v_dual_add_f32 v25, 0xbf2aaaaa, v26 :: v_dual_fmac_f32 v28, v23, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v24, v25
	v_ldexp_f32 v13, v13, 1
	v_fmac_f32_e32 v28, v15, v14
	v_ldexp_f32 v14, v14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v27, v28
	v_add_f32_e32 v16, v16, v24
	v_add_f32_e32 v15, v26, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v24, v26, v15
	v_sub_f32_e32 v26, v23, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v26, v28, v26 :: v_dual_mul_f32 v25, v23, v15
	v_add_f32_e32 v16, v16, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v23, v15, -v25
	v_fmac_f32_e32 v24, v23, v16
	v_frexp_exp_i32_f32_e32 v16, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v24, v26, v15
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v25, v24
	v_cvt_f32_i32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v14, v16
	v_dual_sub_f32 v25, v16, v25 :: v_dual_sub_f32 v14, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v24, v24, v25
	v_mul_f32_e32 v26, 0x3f317218, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v16, v14 :: v_dual_add_f32 v13, v13, v24
	v_fma_f32 v25, 0x3f317218, v15, -v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v13, v14
	v_fmac_f32_e32 v25, 0xb102e308, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v23, v13
	v_dual_add_f32 v14, v26, v25 :: v_dual_sub_f32 v23, v15, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v23
	v_add_f32_e32 v16, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v24, v16, v14
	v_dual_sub_f32 v15, v15, v24 :: v_dual_sub_f32 v26, v14, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v25, v26
	v_add_f32_e32 v23, v25, v13
	v_sub_f32_e32 v27, v16, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v27
	v_add_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v23, v25
	v_dual_sub_f32 v13, v13, v15 :: v_dual_add_f32 v14, v23, v14
	v_sub_f32_e32 v23, v23, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v25, v23 :: v_dual_add_f32 v24, v16, v14
	v_dual_add_f32 v13, v13, v15 :: v_dual_sub_f32 v16, v24, v16
	v_cndmask_b32_e64 v15, 0x40e00000, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v16
	v_add_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v24, v13
	v_dual_sub_f32 v16, v14, v24 :: v_dual_mul_f32 v23, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v16
	v_fma_f32 v14, v15, v14, -v23
	v_cmp_class_f32_e64 vcc_lo, v23, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v15, v13
	v_add_f32_e32 v13, v23, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, v13, v23, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v16
	v_cndmask_b32_e64 v24, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v16, v24
	v_dual_mul_f32 v26, 0x3fb8aa3b, v25 :: v_dual_sub_f32 v13, v13, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, 0x3fb8aa3b, v25, -v26
	v_sub_f32_e32 v13, v14, v13
	v_rndne_f32_e32 v28, v26
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v16|
	v_trunc_f32_e32 v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v27, 0x32a5705f, v25 :: v_dual_sub_f32 v26, v26, v28
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cvt_i32_f32_e32 v23, v28
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	v_dual_add_f32 v26, v26, v27 :: v_dual_add_f32 v13, v24, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v26, v26
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v14, v26, v23
	v_dual_mul_f32 v23, 0.5, v15 :: v_dual_cndmask_b32 v14, 0, v14
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v26, v23
	v_cndmask_b32_e32 v14, 0x7f800000, v14, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s1, v26, v23
	v_fma_f32 v13, v14, v13, v14
	v_cmp_eq_f32_e64 s2, 0x7f800000, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	v_cndmask_b32_e64 v15, 1.0, v22, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, v14, s2
	v_cmp_eq_f32_e64 s2, 0, v22
	v_bfi_b32 v13, 0x7fffffff, v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0x7f800000, 0, s2
	v_cndmask_b32_e64 v15, 0, v22, s1
	v_cmp_class_f32_e64 s1, v22, 0x204
	v_cndmask_b32_e32 v16, 0x7fc00000, v13, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v14, 0x7fffffff, v14, v15
	v_cndmask_b32_e32 v13, v13, v16, vcc_lo
	s_or_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	v_add_f32_e32 v13, -1.0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, 0x42c80000, v13
	v_div_scale_f32 v14, null, 0x40e00000, 0x40e00000, v13
	v_div_scale_f32 v23, vcc_lo, v13, 0x40e00000, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v14, v15, 1.0
	v_fmac_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, v23, v15
	v_fma_f32 v24, -v14, v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v24, v15
	v_fma_f32 v14, -v14, v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v14, v14, v15, v16
	v_cmp_o_f32_e32 vcc_lo, v22, v22
	v_mul_f32_e32 v15, v22, v22
	v_div_fixup_f32 v13, v14, 0x40e00000, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, 1.0, v13
	v_cndmask_b32_e32 v16, 0x7fc00000, v13, vcc_lo
	v_cvt_f64_f32_e32 v[13:14], v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v23, null, v15, v15, v16
	v_div_scale_f32 v26, vcc_lo, v16, v15, v16
	v_rcp_f32_e32 v24, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v23, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v25, v24
	v_mul_f32_e32 v25, v26, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v27, -v23, v25, v26
	v_fmac_f32_e32 v25, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v23, v25, v26
	v_div_fmas_f32 v25, v23, v24, v25
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v23, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fixup_f32 v26, v25, v15, v16
	v_mov_b32_e32 v25, 0
.LBB0_5:                                ; %.preheader193
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	s_add_i32 s34, s3, s13
	s_mov_b32 s37, -1
	s_cmp_gt_i32 s34, -1
	s_mul_i32 s35, s34, s28
	s_cselect_b32 s36, -1, 0
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s36
	s_cbranch_vccnz .LBB0_20
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	s_load_b32 s1, s[20:21], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s34, s1
	s_cbranch_scc1 .LBB0_20
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=3
	s_add_i32 s1, s37, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s1, 0
	s_cselect_b32 s2, -1, 0
	s_cmp_ge_i32 s1, s16
	s_cselect_b32 s22, -1, 0
	s_or_b32 s2, s2, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_20
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=3
	s_mul_i32 s1, s1, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s1, s1, s35
	s_add_i32 s22, s15, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[38:39], s[22:23], 2
	s_add_u32 s38, s18, s38
	s_addc_u32 s39, s19, s39
	s_add_i32 s22, s1, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[40:41], s[22:23], 2
	s_add_u32 s40, s30, s40
	s_addc_u32 s41, s31, s41
	s_clause 0x1
	global_load_b32 v27, v21, s[38:39]
	global_load_b32 v28, v21, s[40:41]
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v27, v28
	s_cbranch_vccnz .LBB0_20
.LBB0_10:                               ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_14 Depth 5
	v_add_nc_u32_e32 v15, v27, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v15, v28
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=4
	v_lshl_add_u32 v29, v15, 1, v15
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_add_co_u32 v31, vcc_lo, s6, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v32, vcc_lo, s7, v30, vcc_lo
	v_add_co_u32 v33, vcc_lo, s8, v29
	v_add_co_ci_u32_e32 v34, vcc_lo, s9, v30, vcc_lo
	v_add_co_u32 v15, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
	global_load_b96 v[29:31], v[31:32], off
	global_load_b96 v[32:34], v[33:34], off
	global_load_b32 v15, v[15:16], off
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v18, v29, v30 offset1:1
	ds_store_b32 v18, v31 offset:8
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v17, v32, v33 offset1:1
	ds_store_b32 v17, v34 offset:8
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v15
.LBB0_12:                               ;   in Loop: Header=BB0_10 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_19
; %bb.13:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_10 Depth=4
	s_mov_b32 s38, 0
	s_mov_b32 s39, 0
	s_movk_i32 s40, 0x600
.LBB0_14:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ;       Parent Loop BB0_6 Depth=3
                                        ;         Parent Loop BB0_10 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_add_nc_u32_e32 v15, s39, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v15, v28
	s_cbranch_vccnz .LBB0_18
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=5
	v_mov_b32_e32 v15, s38
	s_mov_b32 s41, exec_lo
	ds_load_2addr_b32 v[29:30], v15 offset0:192 offset1:193
	ds_load_b32 v16, v15 offset:776
	s_waitcnt lgkmcnt(1)
	v_sub_f32_e32 v29, v29, v1
	s_waitcnt lgkmcnt(0)
	v_dual_sub_f32 v15, v30, v2 :: v_dual_sub_f32 v16, v16, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v30, v15, v15
	v_fmac_f32_e32 v30, v29, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v16, v16
	v_div_scale_f32 v31, null, v20, v20, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, v30, v20, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v34, v33, v32
	v_fma_f32 v35, -v31, v34, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v34, v35, v32
	v_fma_f32 v31, -v31, v34, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v31, v31, v32, v34
	v_div_fixup_f32 v30, v31, v20, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 1.0, v30
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=5
	v_cvt_f64_f32_e32 v[31:32], v30
	v_mov_b32_e32 v30, s40
	v_mov_b32_e32 v44, s38
	ds_load_b32 v30, v30
	s_waitcnt lgkmcnt(0)
	v_frexp_mant_f32_e64 v33, |v30|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v33
	v_cndmask_b32_e64 v34, 0, 1, vcc_lo
	v_add_f64 v[31:32], v[7:8], v[31:32]
	v_ldexp_f32 v33, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v37, -1.0, v33
	v_add_f32_e32 v34, 1.0, v33
	v_add_f32_e32 v39, -1.0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v33, v33, v39
	v_rcp_f32_e32 v35, v34
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v38, v37, v35
	v_mul_f32_e32 v40, v34, v38
	v_cvt_f32_f64_e32 v36, v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, v38, v34, -v40
	v_fmac_f32_e32 v34, v38, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v33, v40, v34
	v_sub_f32_e32 v39, v37, v33
	v_sub_f32_e32 v40, v33, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v37, v37, v39 :: v_dual_sub_f32 v34, v40, v34
	v_sub_f32_e32 v33, v37, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v33, v34, v33
	v_add_f32_e32 v33, v39, v33
	v_cmp_gt_f32_e64 s1, 0xf800000, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v35, v35, v33
	v_add_f32_e32 v37, v38, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v41, 0x4f800000, v36 :: v_dual_sub_f32 v38, v37, v38
	v_cndmask_b32_e64 v36, v36, v41, s1
	v_mul_f32_e32 v42, v37, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v38, v35, v38
	v_sqrt_f32_e32 v34, v36
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v33, -1, v34
	v_add_nc_u32_e32 v39, 1, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v40, -v33, v34, v36
	v_fma_f32 v41, -v39, v34, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v40
	v_cndmask_b32_e64 v40, v34, v33, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s2, 0, v41
	v_cvt_f64_f32_e32 v[33:34], v30
	v_cndmask_b32_e64 v35, v40, v39, s2
	v_fma_f32 v39, v37, v37, -v42
	v_add_f32_e32 v40, v38, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v37, v40
	v_add_f32_e32 v40, v42, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v41, 0x37800000, v35 :: v_dual_sub_f32 v42, v40, v42
	v_cndmask_b32_e64 v35, v35, v41, s1
	v_cmp_class_f32_e64 s1, v36, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v39, v39, v42
	v_cndmask_b32_e64 v43, v35, v36, s1
	v_fmaak_f32 v35, s33, v40, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmaak_f32 v45, v40, v35, 0x3ecccdef
	ds_load_2addr_b32 v[35:36], v44 offset1:1
	ds_load_b32 v44, v44 offset:8
	v_sub_f32_e32 v41, 1.0, v43
	v_mul_f64 v[31:32], v[31:32], v[33:34]
	v_mul_f32_e32 v47, v40, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v42, v40, v45, -v47
	v_fmac_f32_e32 v42, v39, v45
	s_waitcnt lgkmcnt(1)
	v_sub_f32_e32 v36, v36, v5
	v_mul_f32_e32 v46, v41, v41
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v44, v44, v6 :: v_dual_mul_f32 v41, v46, v41
	v_mul_f32_e32 v41, v43, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v33, 0x41a00000, v41
	v_add_f32_e32 v41, v47, v42
	v_mul_f64 v[31:32], v[31:32], v[13:14]
	v_dual_sub_f32 v45, v41, v47 :: v_dual_add_f32 v46, 0x3f2aaaaa, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v47, v37, v40 :: v_dual_sub_f32 v42, v42, v45
	v_add_f32_e32 v45, 0xbf2aaaaa, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v48, v40, v37, -v47
	v_sub_f32_e32 v41, v41, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v35, v35, v4 :: v_dual_fmac_f32 v48, v40, v38
	v_ldexp_f32 v38, v38, 1
	v_dual_mul_f32 v35, v29, v35 :: v_dual_fmac_f32 v48, v39, v37
	v_ldexp_f32 v37, v37, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v35, v15, v36 :: v_dual_add_f32 v36, 0x31739010, v42
	v_fmac_f32_e32 v35, v16, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v40, v36, v41 :: v_dual_add_f32 v41, v47, v48
	v_add_f32_e32 v39, v46, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v45, v41, v47
	v_sub_f32_e32 v42, v46, v39
	v_cvt_f64_f32_e32 v[33:34], v33
	v_mul_f32_e32 v44, v41, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v40, v40, v42
	v_fma_f32 v42, v41, v39, -v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v45, v48, v45 :: v_dual_fmac_f32 v42, v41, v40
	v_frexp_exp_i32_f32_e32 v40, v30
	v_fmac_f32_e32 v42, v45, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v39, vcc_lo, 0, v40, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v30
	v_add_f32_e32 v40, v44, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v39, v39
	v_add_f32_e32 v41, v37, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v44, v40, v44 :: v_dual_mul_f32 v45, 0x3f317218, v39
	v_dual_sub_f32 v37, v41, v37 :: v_dual_sub_f32 v42, v42, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, 0x3f317218, v39, -v45
	v_sub_f32_e32 v40, v40, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v42, v38, v42
	v_mul_f64 v[33:34], v[9:10], v[33:34]
	v_dual_fmac_f32 v44, 0xb102e308, v39 :: v_dual_add_f32 v39, v42, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v40, v[33:34]
	v_add_f32_e32 v33, v45, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v34, v41, v39
	v_add_f32_e32 v35, v35, v35
	v_sub_f32_e32 v45, v33, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v42, v33, v34
	v_cvt_f64_f32_e32 v[35:36], v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v44, v44, v45
	v_sub_f32_e32 v46, v42, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v47, v42, v46
	v_sub_f32_e32 v41, v34, v41
	v_dual_sub_f32 v34, v34, v46 :: v_dual_sub_f32 v33, v33, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v41, v39, v41
	v_add_f32_e32 v39, v34, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v45, v44, v41
	v_sub_f32_e32 v46, v45, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v47, v45, v39
	v_cvt_f64_f32_e32 v[39:40], v40
	v_dual_sub_f32 v45, v45, v46 :: v_dual_add_f32 v48, v42, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v44, v44, v45
	v_sub_f32_e32 v42, v48, v42
	v_div_scale_f64 v[37:38], null, v[31:32], v[31:32], v[35:36]
	v_cndmask_b32_e64 v45, 0x40e00000, 1.0, vcc_lo
	v_sub_f32_e32 v41, v41, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v42, v47, v42 :: v_dual_add_f32 v41, v41, v44
	v_add_f32_e32 v41, v41, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v42, v48, v41
	v_sub_f32_e32 v44, v42, v48
	v_mul_f32_e32 v46, v45, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v47, v41, v44
	v_fma_f32 v48, v45, v42, -v46
	v_cvt_f64_f32_e32 v[43:44], v43
	v_mul_f64 v[39:40], v[39:40], s[26:27]
	v_cmp_class_f32_e64 vcc_lo, v46, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v48, v45, v47
	v_rcp_f64_e32 v[33:34], v[37:38]
	v_add_f32_e32 v47, v46, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v49, v47, v46, vcc_lo
	v_sub_f32_e32 v46, v47, v46
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v49
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v46, v48, v46
	v_trunc_f32_e32 v48, v45
	v_cndmask_b32_e64 v50, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v49|
	v_sub_f32_e32 v51, v49, v50
	v_cndmask_b32_e32 v46, 0, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v52, 0x3fb8aa3b, v51
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v51
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v51
	v_fma_f32 v53, 0x3fb8aa3b, v51, -v52
	v_rndne_f32_e32 v54, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_dual_fmac_f32 v53, 0x32a5705f, v51 :: v_dual_sub_f32 v52, v52, v54
	v_cvt_i32_f32_e32 v47, v54
	v_fma_f64 v[41:42], -v[37:38], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v52, v52, v53
	v_exp_f32_e32 v52, v52
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v47, v52, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v52, 0.5, v45 :: v_dual_cndmask_b32 v47, 0, v47
	v_trunc_f32_e32 v49, v52
	v_cmp_eq_f32_e32 vcc_lo, v48, v45
	v_add_f32_e32 v48, v50, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v50, 0x7f800000, v47, s1
	v_cmp_neq_f32_e64 s1, v49, v52
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v49, v50, v48, v50
	v_cmp_eq_f32_e64 s2, 0x7f800000, v50
	s_and_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v51, 1.0, v30, s1
	v_fma_f64 v[33:34], v[33:34], v[41:42], v[33:34]
	v_div_scale_f64 v[41:42], null, v[43:44], v[43:44], v[39:40]
	v_cndmask_b32_e64 v49, v49, v50, s2
	v_cmp_eq_f32_e64 s2, 0, v30
	v_bfi_b32 v49, 0x7fffffff, v49, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v50, 0x7f800000, 0, s2
	v_cndmask_b32_e64 v51, 0, v30, s1
	v_cmp_class_f32_e64 s1, v30, 0x204
	v_cndmask_b32_e32 v52, 0x7fc00000, v49, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v50, 0x7fffffff, v50, v51
	v_cndmask_b32_e32 v49, v49, v52, vcc_lo
	s_or_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v49, v49, v50, vcc_lo
	v_add_f32_e32 v49, -1.0, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v53, 0x42c80000, v49
	v_div_scale_f64 v[49:50], s1, v[35:36], v[31:32], v[35:36]
	v_fma_f64 v[45:46], -v[37:38], v[33:34], 1.0
	v_rcp_f64_e32 v[47:48], v[41:42]
	v_div_scale_f32 v54, null, 0x40e00000, 0x40e00000, v53
	v_div_scale_f32 v56, vcc_lo, v53, 0x40e00000, v53
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v55, v54
	s_waitcnt_depctr 0xfff
	v_fma_f32 v51, -v54, v55, 1.0
	v_fmac_f32_e32 v55, v51, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v57, v56, v55
	v_fma_f32 v51, -v54, v57, v56
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v57, v51, v55
	v_fma_f64 v[33:34], v[33:34], v[45:46], v[33:34]
	v_fma_f64 v[45:46], -v[41:42], v[47:48], 1.0
	v_fma_f32 v54, -v54, v57, v56
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[51:52], v[49:50], v[33:34]
	v_fma_f64 v[45:46], v[47:48], v[45:46], v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v47, v54, v55, v57
	v_cmp_o_f32_e32 vcc_lo, v30, v30
	v_div_fixup_f32 v47, v47, 0x40e00000, v53
	v_mul_f32_e32 v53, v30, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v47, 1.0, v47
	v_cndmask_b32_e32 v30, 0x7fc00000, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v54, null, v53, v53, v30
	v_rcp_f32_e32 v55, v54
	v_fma_f64 v[37:38], -v[37:38], v[51:52], v[49:50]
	s_waitcnt_depctr 0xfff
	v_fma_f32 v49, -v54, v55, 1.0
	v_div_scale_f32 v50, vcc_lo, v30, v53, v30
	v_fma_f64 v[47:48], -v[41:42], v[45:46], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v55, v49, v55
	v_mul_f32_e32 v49, v50, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v56, -v54, v49, v50
	v_fmac_f32_e32 v49, v56, v55
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v50, -v54, v49, v50
	v_div_fmas_f32 v49, v50, v55, v49
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v30, v49, v53, v30
	v_div_fmas_f64 v[33:34], v[37:38], v[33:34], v[51:52]
	v_div_scale_f64 v[37:38], vcc_lo, v[39:40], v[43:44], v[39:40]
	v_add_f32_e32 v30, v26, v30
	v_fma_f64 v[45:46], v[45:46], v[47:48], v[45:46]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[47:48], v30
	v_div_fixup_f64 v[30:31], v[33:34], v[31:32], v[35:36]
	v_mul_f64 v[32:33], v[37:38], v[45:46]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[47:48], -v[30:31]
	v_fma_f64 v[34:35], -v[41:42], v[32:33], v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v36, v[30:31]
	v_div_fmas_f64 v[30:31], v[34:35], v[45:46], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[32:33], v36
	v_div_fixup_f64 v[30:31], v[30:31], v[43:44], v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[30:31], v[32:33]
	v_cvt_f32_f64_e32 v30, v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v24, v15, v30
	v_fmac_f32_e32 v25, v29, v30
	v_fmac_f32_e32 v23, v16, v30
.LBB0_17:                               ; %Flow
                                        ;   in Loop: Header=BB0_14 Depth=5
	s_or_b32 exec_lo, exec_lo, s41
.LBB0_18:                               ;   in Loop: Header=BB0_14 Depth=5
	s_add_i32 s39, s39, 1
	s_add_i32 s38, s38, 12
	s_add_i32 s40, s40, 4
	s_cmp_lg_u32 s39, 64
	s_cbranch_scc1 .LBB0_14
.LBB0_19:                               ; %Flow250
                                        ;   in Loop: Header=BB0_10 Depth=4
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v27, 64, v27
	s_barrier
	buffer_gl0_inv
	v_cmp_lt_i32_e32 vcc_lo, v27, v28
	s_cbranch_vccnz .LBB0_10
.LBB0_20:                               ; %.loopexit192
                                        ;   in Loop: Header=BB0_6 Depth=3
	s_add_i32 s37, s37, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s37, 2
	s_cbranch_scc0 .LBB0_6
; %bb.21:                               ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, 2
	s_cbranch_scc0 .LBB0_5
; %bb.22:                               ;   in Loop: Header=BB0_2 Depth=1
	s_and_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_2 Depth=1
	v_max_f32_e64 v13, -v1, -v1
	v_max_f32_e64 v15, -v2, -v2
	v_add_f32_e32 v14, -2.0, v1
	v_max_f32_e64 v26, -v3, -v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v16, -1.0, v2 :: v_dual_max_f32 v13, 0, v13
	v_dual_max_f32 v15, 0, v15 :: v_dual_max_f32 v14, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_max_f32 v16, 0, v16 :: v_dual_mul_f32 v13, 0x447a0000, v13
	v_mul_f32_e32 v15, 0x447a0000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v27, null, s29, s29, v13
	v_div_scale_f32 v32, null, s29, s29, v15
	v_div_scale_f32 v30, vcc_lo, v13, s29, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v29, v27
	v_rcp_f32_e32 v36, v32
	v_div_scale_f32 v39, s1, v15, s29, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v27, v29, 1.0
	v_mul_f32_e32 v14, 0x447a0000, v14
	v_fma_f32 v41, -v32, v36, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v29, v34, v29
	v_div_scale_f32 v28, null, s29, s29, v14
	v_div_scale_f32 v35, s0, v14, s29, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v36, v41, v36
	v_rcp_f32_e32 v31, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v38, -v28, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_max_f32 v26, 0, v26 :: v_dual_fmac_f32 v31, v38, v31
	v_dual_mul_f32 v16, 0x447a0000, v16 :: v_dual_mul_f32 v43, v35, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v33, null, s29, s29, v16
	v_div_scale_f32 v45, s2, v16, s29, v16
	v_fma_f32 v41, -v28, v43, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v37, v33
	v_dual_mul_f32 v38, v30, v29 :: v_dual_fmac_f32 v43, v41, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, -v27, v38, v30
	v_fma_f32 v28, -v28, v43, v35
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v33, v37, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v26, 0x447a0000, v26 :: v_dual_fmac_f32 v37, v42, v37
	v_div_scale_f32 v34, null, s29, s29, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v40, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v42, -v34, v40, 1.0
	v_fmac_f32_e32 v40, v42, v40
	v_fmac_f32_e32 v38, v44, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v27, -v27, v38, v30
	v_div_scale_f32 v30, s3, v26, s29, v26
	v_mul_f32_e32 v41, v30, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v27, v27, v29, v38
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v28, v28, v31, v43
	s_mov_b32 vcc_lo, s1
	v_div_fixup_f32 v13, v27, s29, v13
	v_mul_f32_e32 v44, v39, v36
	v_fma_f32 v27, -v34, v41, v30
	v_div_fixup_f32 v14, v28, s29, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v13, v25
	v_lshlrev_b64 v[12:13], 2, v[11:12]
	v_fma_f32 v29, -v32, v44, v39
	v_sub_f32_e32 v11, v25, v14
	v_dual_mul_f32 v46, v45, v37 :: v_dual_fmac_f32 v41, v27, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v44, v29, v36
	v_fma_f32 v38, -v33, v46, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v34, v41, v30
	v_fma_f32 v29, -v32, v44, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v46, v38, v37
	v_div_fmas_f32 v29, v29, v36, v44
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v33, v46, v45
	v_div_fixup_f32 v15, v29, s29, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v27, v27, v37, v46
	s_mov_b32 vcc_lo, s3
	v_add_f32_e32 v24, v15, v24
	v_div_fmas_f32 v30, v30, v40, v41
	v_add_co_u32 v14, vcc_lo, s4, v12
	v_div_fixup_f32 v16, v27, s29, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v26, v30, s29, v26
	v_dual_sub_f32 v12, v24, v16 :: v_dual_add_f32 v23, v26, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v13, -1.0, v23
	global_store_b96 v[14:15], v[11:13], off
.LBB0_24:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_add_i32 s24, s24, 64
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s24, s25
	s_cbranch_scc0 .LBB0_2
.LBB0_25:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel ker_dv
		.amdhsa_group_segment_fixed_size 1792
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 42
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	ker_dv, .Lfunc_end0-ker_dv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5056
; NumSgprs: 44
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1792 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 44
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1792
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           ker_dv
    .private_segment_fixed_size: 0
    .sgpr_count:     44
    .sgpr_spill_count: 0
    .symbol:         ker_dv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
