/*
 ============================================================================
 Name        : CudaProject.cu
 Author      : Adrianna Urbańska, Gabriel Chęć
 Version     :
 Copyright   : 
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
#define BLOCK_SIZE 32

class CudaObject {

public:
	int size_x;
	int size_y;
	int *data;
	int stride;
	int bytes;
	
	__host__ __device__
	CudaObject(int x, int y, int stride ): size_x(x), size_y(y),stride(stride){}
	
	__host__ __device__	
	CudaObject(const CudaObject &a): size_x(a.size_x), size_y(a.size_y),data(a.data),stride(a.stride){}
	
	__device__ 
	int getElement(int row, int col){
		return data[row * stride + col];
	}

	__device__
	 void setElement(int row, int col, int val){
		data[row * stride + col] = val;
	}
	
	__device__
	CudaObject cutMatrix(int row, int col){
		CudaObject tmp(BLOCK_SIZE, BLOCK_SIZE, stride);
		
		tmp.data = &data[stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
		return tmp;
	}
	
	__host__  
	 void writeOut(){
		for(int i = 0; i < size_x; i++){
			std::cout<<"| ";
		 	for(int j = 0; j < size_y; j++){
		 		std::cout<<data[i * size_y + j]<<" ";
		 	}
			std::cout<<"|"<<std::endl;
		 }
		std::cout<<"\n";
	}

	void setSize(int x, int y){
		this->size_x = x;
		this->size_y = y;
		this->bytes = x * y * sizeof(int);
		cudaMallocManaged(&this->data, this->bytes);
	}


	void addCpu(CudaObject &fData, CudaObject &sData){
		if(fData.size_x == sData.size_x && fData.size_y == sData.size_y){
			cudaMemPrefetchAsync(this->data, this->bytes, cudaCpuDeviceId);
			cudaMemPrefetchAsync(fData.data, fData.bytes, cudaCpuDeviceId);
			cudaMemPrefetchAsync(sData.data, sData.bytes, cudaCpuDeviceId);

			this->setSize(sData.size_x, sData.size_y);

			for(int i = 0; i < sData.size_x; i++){
				for(int j = 0; j < sData.size_y; j++){
					this->data[i * this->size_x + j] = fData.data[i * this->size_x + j] + sData.data[i * this->size_x + j];
				}
			}
		}
	}

	void subCpu(CudaObject &fData, CudaObject &sData){
		if(fData.size_x == sData.size_x && fData.size_y == sData.size_y){
			cudaMemPrefetchAsync(this->data, this->bytes, cudaCpuDeviceId);
			cudaMemPrefetchAsync(fData.data, fData.bytes, cudaCpuDeviceId);
			cudaMemPrefetchAsync(sData.data, sData.bytes, cudaCpuDeviceId);

			this->setSize(sData.size_x, sData.size_y);

			for(int i = 0; i < sData.size_x; i++){
				for(int j = 0; j < sData.size_y; j++){
					this->data[i * this->size_x + j] = fData.data[i * this->size_x + j] - sData.data[i * this->size_x + j];
				}
			}
		}
	}

	void mulCpu(CudaObject &fData, CudaObject &sData){
		int y_s = sData.size_y;
		int y_f = fData.size_y;
  		for(int i = 0; i < size_x; i++ ){
    		for(int j = 0; j < size_y; j++ ){
      			int s = 0;
      			for(int k = 0; k < y_f; k++ ) 
					s += fData.data[i * y_f + k] * sData.data[k * y_s + j];
				this->data[i * y_s + j] = s;
    		}
		}
	}

	void tranCpu(CudaObject &iData){

	 	int x = iData.size_x;
		int y = iData.size_y;

		this->setSize(y,x);

		for(int n = 0; n < x * y; n++){
			int i = n/x;
			int j = n%x;
			this->data[n] = iData.data[y * j + i];
		}
	}

};

__global__ void add(int *fData, int *sData, int *oData, int x, int y){

	int index = threadIdx.x + blockIdx.x * blockDim.x;
	int stride = blockDim.x * gridDim.x;
	
	for(int i = index; i < x*y; i += stride)
	{
		oData[i] = fData[i] + sData[i];
	}
}

__global__ void sub(int *fData, int *sData, int *oData, int x, int y){

	  int index = threadIdx.x + blockIdx.x * blockDim.x;
	  int stride = blockDim.x * gridDim.x;

	  for(int i = index; i < x * y; i += stride)
	  {
	    oData[i] = fData[i] - sData[i];
	  }
}


__global__ void mul(CudaObject a,CudaObject b, CudaObject c) {
	int cutRow = blockIdx.y ;
	int cutCol = blockIdx.x;

	int fRow = blockIdx.y * blockDim.y + threadIdx.y;
	int fCol = blockIdx.x * blockDim.x + threadIdx.x;	
	int row = threadIdx.y;
	int col = threadIdx.x;
	
	int temp = 0;
	
	CudaObject cutMatC = c.cutMatrix(cutRow, cutCol);
	
	for( int v = 0; v < ((a.size_y + BLOCK_SIZE - 1)/BLOCK_SIZE); ++v){
		CudaObject cutMatA = a.cutMatrix(cutRow, v);	//cut input matrix vector which can fit inside block
		CudaObject cutMatB = b.cutMatrix(v, cutCol);	
	
		__shared__ int A[BLOCK_SIZE][BLOCK_SIZE];	//Matrix wchich can share memory between threads
		__shared__ int B[BLOCK_SIZE][BLOCK_SIZE];
		if((row  < a.size_x) && ((col + v * BLOCK_SIZE) < a.size_y)){ 		
			A[row][col] = cutMatA.getElement(row, col);
		}
		else{
			A[row][col] = 0;
		}

		if((col < b.size_y) && ((row + v * BLOCK_SIZE) < b.size_x)){
			B[row][col] = cutMatB.getElement(row, col);
		}
		else{
			B[row][col] = 0;
		}

		__syncthreads();				//make sure that every metrix is filled
	
		for (int i = 0; i < BLOCK_SIZE; ++i){
			temp += A[row][i] * B[i][col];
		}		
		__syncthreads();
	
	}

	if(fRow < c.size_x && fCol < c.size_y)
		c.setElement(fRow, fCol, temp);
}

__global__ void tran(CudaObject iData, CudaObject oData){

	int index = threadIdx.x + blockIdx.x * blockDim.x;
	int stride = blockDim.x * gridDim.x;
	int x = iData.size_x;
	int y = iData.size_y;

	for(int n = index; n < x * y; n += stride){
		int i = n/x;
		int j = n%x;
		oData.data[n] = iData.data[y * j + i];
	}
}

void OperationsInfo()
{
	std::cout<<"Choose an operation:"<<std::endl;
	std::cout<<"1. Matrix addition on CPU"<<std::endl;
	std::cout<<"2. Matrix addition on GPU"<<std::endl;
	std::cout<<"3. Matrix substraction on CPU"<<std::endl;
	std::cout<<"4. Matrix substraction on GPU"<<std::endl;
	std::cout<<"5. Matrix multiplication on CPU"<<std::endl;
	std::cout<<"6. Matrix multiplication on GPU"<<std::endl;
	std::cout<<"7. Matrix transposition on CPU"<<std::endl;
	std::cout<<"8. Matrix transposition on GPU"<<std::endl;
}


void Init(CudaObject &oData, int val)
{
	int x = oData.size_x;
	int y = oData.size_y;

	for(int i = 0; i < y; i++){
		for(int j = 0; j<x; j++){
			oData.data[i*x+j] = val;  
		}
	}
}

int main(){

	int operation;
	int N_1, N_2, M_1, M_2;
	int val_1, val_2;

	std::cout<<"Enter the values of size_x, size_y of the first matrix and value to filled matrix:"<<std::endl;
	std::cin>>N_1;
	std::cin>>M_1;
	std::cin>>val_1;

	std::cout<<"Enter the values of size_x, size_y of the second matrix and value to filled matrix:"<<std::endl;
	std::cin>>N_2;
	std::cin>>M_2;
	std::cin>>val_2;

	CudaObject fData(N_1, M_1, M_1), sData(N_2, M_2, M_2), oData(N_1, M_2, M_2);

	cudaMallocManaged(&fData.data,N_1 * M_1 * sizeof(int));
	cudaMallocManaged(&sData.data, N_2 * M_2 * sizeof(int));
	cudaMallocManaged(&oData.data, N_1 * M_2 * sizeof(int));

	Init(fData,val_1);
	Init(sData,val_2);

	fData.writeOut();	
	sData.writeOut();

	OperationsInfo();
	std::cin>>operation;

	dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE);
	dim3 blocksPerGrid((fData.size_y + threadsPerBlock.x - 1)/threadsPerBlock.x, (sData.size_x + threadsPerBlock.y - 1)/threadsPerBlock.y);

	switch(operation)
	{
		case 1:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				oData.addCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 2:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				add<<<blocksPerGrid,threadsPerBlock>>>(fData.data, sData.data, oData.data, oData.size_x, oData.size_y);
				cudaDeviceSynchronize();
				oData.writeOut();
			}
			break;
		case 3:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				oData.subCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 4:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				sub<<<blocksPerGrid,threadsPerBlock>>>(fData.data, sData.data, oData.data, oData.size_x, oData.size_y);
				cudaDeviceSynchronize();
				oData.writeOut();
			}
			break;
		case 5:
			if(fData.size_y != sData.size_x){
				std::cout<<"Size_x of the first matrix and size_y of the second matrix have to be equal!"<<std::endl;
			}
			else{
				oData.mulCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 6:
			if(fData.size_y != sData.size_x){
				std::cout<<"Size_x of the first matrix and size_y of the second matrix have to be equal!"<<std::endl;
			}
			else{
				mul<<<blocksPerGrid, threadsPerBlock>>>(fData, sData, oData);	
				cudaDeviceSynchronize();
				oData.writeOut();
			}			
			break;
		case 7:
			std::cout<<"Transposition of the first matrix: "<<std::endl;
			oData.tranCpu(fData);
			oData.writeOut();

			std::cout<<"Transposition of the second matrix: "<<std::endl;	
			oData.tranCpu(sData);
			oData.writeOut();
		
			break;
		case 8:
			std::cout<<"Transposition of the first matrix: "<<std::endl;
			oData.setSize(M_1,N_1);
			tran<<<blocksPerGrid, threadsPerBlock>>>(fData, oData);	
			cudaDeviceSynchronize();
			oData.writeOut();

			std::cout<<"Transposition of the second matrix: "<<std::endl;
			oData.setSize(M_2,N_2);
			tran<<<blocksPerGrid, threadsPerBlock>>>(sData, oData);	
			cudaDeviceSynchronize();
			oData.writeOut();
		
			break;
		default:
			std::cout<<"Wrong number entered!"<<std::endl;
			break;
	}
	
	cudaError_t err = cudaSuccess;	
		
	if (err != cudaSuccess){	
        	fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
        	exit(EXIT_FAILURE);
    	}
			
	cudaFree(fData.data);
	cudaFree(sData.data);
	cudaFree(oData.data);
}	

	.file	"tmpxft_00300d4a_00000000-6_main.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3655:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3655:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4319:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4319:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.section	.rodata._ZN10CudaObject8writeOutEv.str1.1,"aMS",@progbits,1
.LC0:
	.string	"| "
.LC1:
	.string	" "
.LC2:
	.string	"|"
.LC3:
	.string	"\n"
	.section	.text._ZN10CudaObject8writeOutEv,"axG",@progbits,_ZN10CudaObject8writeOutEv,comdat
	.align 2
	.weak	_ZN10CudaObject8writeOutEv
	.type	_ZN10CudaObject8writeOutEv, @function
_ZN10CudaObject8writeOutEv:
.LFB3644:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	leaq	_ZSt4cout(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%rdi, %rbx
.L4:
	cmpl	%r12d, (%rbx)
	jle	.L10
	leaq	.LC0(%rip), %rsi
	movq	%rbp, %rdi
	xorl	%r14d, %r14d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC1(%rip), %r13
.L5:
	movl	4(%rbx), %eax
	cmpl	%r14d, %eax
	jle	.L11
	imull	%r12d, %eax
	movq	8(%rbx), %rdx
	movq	%rbp, %rdi
	addl	%r14d, %eax
	incl	%r14d
	cltq
	movl	(%rdx,%rax,4), %esi
	call	_ZNSolsEi@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	jmp	.L5
.L11:
	leaq	.LC2(%rip), %rsi
	movq	%rbp, %rdi
	incl	%r12d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	jmp	.L4
.L10:
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%rbp, %rdi
	leaq	.LC3(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	.cfi_endproc
.LFE3644:
	.size	_ZN10CudaObject8writeOutEv, .-_ZN10CudaObject8writeOutEv
	.section	.text._ZN10CudaObject7setSizeEii,"axG",@progbits,_ZN10CudaObject7setSizeEii,comdat
	.align 2
	.weak	_ZN10CudaObject7setSizeEii
	.type	_ZN10CudaObject7setSizeEii, @function
_ZN10CudaObject7setSizeEii:
.LFB3645:
	.cfi_startproc
	endbr64
	movl	%esi, (%rdi)
	imull	%edx, %esi
	addq	$8, %rdi
	movl	%edx, -4(%rdi)
	movl	$1, %edx
	sall	$2, %esi
	movl	%esi, 12(%rdi)
	movslq	%esi, %rsi
	jmp	cudaMallocManaged@PLT
	.cfi_endproc
.LFE3645:
	.size	_ZN10CudaObject7setSizeEii, .-_ZN10CudaObject7setSizeEii
	.section	.text._ZN10CudaObject7tranCpuERS_,"axG",@progbits,_ZN10CudaObject7tranCpuERS_,comdat
	.align 2
	.weak	_ZN10CudaObject7tranCpuERS_
	.type	_ZN10CudaObject7tranCpuERS_, @function
_ZN10CudaObject7tranCpuERS_:
.LFB3649:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rsi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 48
	movl	(%rsi), %ebp
	movl	4(%rsi), %r13d
	movl	%ebp, %edx
	movl	%r13d, %esi
	call	_ZN10CudaObject7setSizeEii
	movl	%ebp, %esi
	xorl	%ecx, %ecx
	imull	%r13d, %esi
.L14:
	movl	%ecx, %eax
	cmpl	%ecx, %esi
	jle	.L17
	cltd
	idivl	%ebp
	imull	%r13d, %edx
	addl	%eax, %edx
	movq	8(%rbx), %rax
	movslq	%edx, %rdx
	movl	(%rax,%rdx,4), %edx
	movq	8(%r12), %rax
	movl	%edx, (%rax,%rcx,4)
	incq	%rcx
	jmp	.L14
.L17:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3649:
	.size	_ZN10CudaObject7tranCpuERS_, .-_ZN10CudaObject7tranCpuERS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Choose an operation:"
.LC5:
	.string	"1. Matrix addition on CPU"
.LC6:
	.string	"2. Matrix addition on GPU"
.LC7:
	.string	"3. Matrix substraction on CPU"
.LC8:
	.string	"4. Matrix substraction on GPU"
.LC9:
	.string	"5. Matrix multiplication on CPU"
.LC10:
	.string	"6. Matrix multiplication on GPU"
.LC11:
	.string	"7. Matrix transposition on CPU"
.LC12:
	.string	"8. Matrix transposition on GPU"
	.text
	.globl	_Z14OperationsInfov
	.type	_Z14OperationsInfov, @function
_Z14OperationsInfov:
.LFB3650:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZSt4cout(%rip), %rbx
	leaq	.LC4(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC5(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC6(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC7(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC9(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC10(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC11(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbx, %rdi
	leaq	.LC12(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 8
	movq	%rax, %rdi
	jmp	_ZNSolsEPFRSoS_E.isra.0
	.cfi_endproc
.LFE3650:
	.size	_Z14OperationsInfov, .-_Z14OperationsInfov
	.globl	_Z4InitR10CudaObjecti
	.type	_Z4InitR10CudaObjecti, @function
_Z4InitR10CudaObjecti:
.LFB3651:
	.cfi_startproc
	endbr64
	movl	(%rdi), %r9d
	movl	4(%rdi), %r10d
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
.L21:
	cmpl	%r10d, %r8d
	jge	.L20
	movslq	%ecx, %rax
	xorl	%edx, %edx
	salq	$2, %rax
.L24:
	cmpl	%r9d, %edx
	jge	.L25
	movq	8(%rdi), %r11
	incl	%edx
	movl	%esi, (%r11,%rax)
	addq	$4, %rax
	jmp	.L24
.L25:
	incl	%r8d
	addl	%r9d, %ecx
	jmp	.L21
.L20:
	ret
	.cfi_endproc
.LFE3651:
	.size	_Z4InitR10CudaObjecti, .-_Z4InitR10CudaObjecti
	.globl	_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
	.type	_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii:
.LFB3677:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3addPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
	.globl	_Z3addPiS_S_ii
	.type	_Z3addPiS_S_ii, @function
_Z3addPiS_S_ii:
.LFB3678:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3678:
	.size	_Z3addPiS_S_ii, .-_Z3addPiS_S_ii
	.globl	_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii
	.type	_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii:
.LFB3679:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3subPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L31:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3679:
	.size	_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii
	.globl	_Z3subPiS_S_ii
	.type	_Z3subPiS_S_ii, @function
_Z3subPiS_S_ii:
.LFB3680:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3680:
	.size	_Z3subPiS_S_ii, .-_Z3subPiS_S_ii
	.globl	_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_
	.type	_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_, @function
_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_:
.LFB3681:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 72(%rsp)
	leaq	16(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movq	%rdx, 80(%rsp)
	movq	%rsp, %rdx
	movq	%rax, 16(%rsp)
	movl	$1, 24(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	8(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z3mul10CudaObjectS_S_(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 128
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L36:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3681:
	.size	_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_, .-_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_
	.globl	_Z3mul10CudaObjectS_S_
	.type	_Z3mul10CudaObjectS_S_, @function
_Z3mul10CudaObjectS_S_:
.LFB3682:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_
	.cfi_endproc
.LFE3682:
	.size	_Z3mul10CudaObjectS_S_, .-_Z3mul10CudaObjectS_S_
	.globl	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_
	.type	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_, @function
_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_:
.LFB3683:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rcx
	movq	%rdi, 72(%rsp)
	movabsq	$4294967297, %rax
	movq	%rsi, 80(%rsp)
	leaq	8(%rsp), %rdx
	leaq	36(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movq	%rax, 24(%rsp)
	movl	$1, 32(%rsp)
	movq	%rax, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	16(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z4tran10CudaObjectS_(%rip), %rdi
	pushq	16(%rsp)
	.cfi_def_cfa_offset 128
	movq	52(%rsp), %rcx
	movl	60(%rsp), %r8d
	movq	40(%rsp), %rsi
	movl	48(%rsp), %edx
	leaq	88(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L41:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3683:
	.size	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_, .-_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_
	.globl	_Z4tran10CudaObjectS_
	.type	_Z4tran10CudaObjectS_, @function
_Z4tran10CudaObjectS_:
.LFB3684:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_
	.cfi_endproc
.LFE3684:
	.size	_Z4tran10CudaObjectS_, .-_Z4tran10CudaObjectS_
	.section	.rodata.str1.1
.LC13:
	.string	"Enter the values of size_x, size_y of the first matrix and value to filled matrix:"
.LC14:
	.string	"Enter the values of size_x, size_y of the second matrix and value to filled matrix:"
.LC15:
	.string	"Matrices sizes have to be equal!"
.LC16:
	.string	"Size_x of the first matrix and size_y of the second matrix have to be equal!"
.LC17:
	.string	"Transposition of the first matrix: "
.LC18:
	.string	"Transposition of the second matrix: "
.LC19:
	.string	"Wrong number entered!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3652:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC13(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	_ZSt3cin(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	_ZSt4cout(%rip), %rbx
	movq	%rbx, %rdi
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %r12
	leaq	96(%rsp), %r13
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	24(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	leaq	32(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	leaq	40(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	28(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	leaq	36(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	leaq	44(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	movl	24(%rsp), %edx
	movl	32(%rsp), %esi
	leaq	80(%rsp), %rdi
	movl	28(%rsp), %ecx
	movl	36(%rsp), %eax
	movl	%esi, 76(%rsp)
	movl	%esi, 88(%rsp)
	imull	%edx, %esi
	movl	%edx, 72(%rsp)
	movl	%edx, 120(%rsp)
	movl	$1, %edx
	movslq	%esi, %rsi
	movl	%ecx, 96(%rsp)
	salq	$2, %rsi
	movl	%eax, 100(%rsp)
	movl	%eax, 112(%rsp)
	movl	%eax, 124(%rsp)
	movl	%eax, 136(%rsp)
	call	cudaMallocManaged@PLT
	movl	28(%rsp), %esi
	imull	36(%rsp), %esi
	leaq	104(%rsp), %rdi
	movl	$1, %edx
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	24(%rsp), %esi
	imull	36(%rsp), %esi
	movl	$1, %edx
	leaq	128(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movl	40(%rsp), %esi
	movq	%r12, %rdi
	call	_Z4InitR10CudaObjecti
	movl	44(%rsp), %esi
	movq	%r13, %rdi
	call	_Z4InitR10CudaObjecti
	movq	%r12, %rdi
	call	_ZN10CudaObject8writeOutEv
	movq	%r13, %rdi
	call	_ZN10CudaObject8writeOutEv
	call	_Z14OperationsInfov
	leaq	20(%rsp), %rsi
	movq	%rbp, %rdi
	call	_ZNSirsERi@PLT
	movl	76(%rsp), %eax
	movl	96(%rsp), %ecx
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	leal	31(%rax), %edx
	shrl	$5, %edx
	movl	%edx, 60(%rsp)
	leal	31(%rcx), %edx
	shrl	$5, %edx
	movl	%edx, 64(%rsp)
	movl	20(%rsp), %edx
	decl	%edx
	cmpl	$7, %edx
	ja	.L47
	leaq	.L49(%rip), %rsi
	movslq	(%rsi,%rdx,4), %rdx
	addq	%rsi, %rdx
	notrack jmp	*%rdx
	.section	.rodata
	.align 4
	.align 4
.L49:
	.long	.L56-.L49
	.long	.L55-.L49
	.long	.L54-.L49
	.long	.L53-.L49
	.long	.L52-.L49
	.long	.L51-.L49
	.long	.L50-.L49
	.long	.L48-.L49
	.section	.text.startup
.L56:
	movq	96(%rsp), %rax
	cmpq	%rax, 72(%rsp)
	je	.L57
.L62:
	leaq	.LC15(%rip), %rsi
	jmp	.L84
.L57:
	movslq	140(%rsp), %rsi
	movq	128(%rsp), %rdi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	call	cudaMemPrefetchAsync@PLT
	movslq	92(%rsp), %rsi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	movq	80(%rsp), %rdi
	call	cudaMemPrefetchAsync@PLT
	movslq	116(%rsp), %rsi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	movq	104(%rsp), %rdi
	call	cudaMemPrefetchAsync@PLT
	movl	100(%rsp), %edx
	movl	96(%rsp), %esi
	leaq	120(%rsp), %rdi
	call	_ZN10CudaObject7setSizeEii
	movq	80(%rsp), %rdi
	movq	104(%rsp), %r8
	xorl	%edx, %edx
	movq	128(%rsp), %r9
.L59:
	cmpl	96(%rsp), %edx
	jge	.L87
	xorl	%ecx, %ecx
.L61:
	cmpl	100(%rsp), %ecx
	jge	.L88
	movl	120(%rsp), %eax
	imull	%edx, %eax
	addl	%ecx, %eax
	incl	%ecx
	cltq
	movl	(%r8,%rax,4), %esi
	addl	(%rdi,%rax,4), %esi
	movl	%esi, (%r9,%rax,4)
	jmp	.L61
.L88:
	incl	%edx
	jmp	.L59
.L55:
	movq	96(%rsp), %rax
	cmpq	%rax, 72(%rsp)
	jne	.L62
	movl	56(%rsp), %ecx
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdx
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L77
	movl	124(%rsp), %r8d
	movl	120(%rsp), %ecx
	movq	128(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z28__device_stub__Z3addPiS_S_iiPiS_S_ii
	jmp	.L77
.L54:
	movq	96(%rsp), %rax
	cmpq	%rax, 72(%rsp)
	jne	.L62
	movslq	140(%rsp), %rsi
	movq	128(%rsp), %rdi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	call	cudaMemPrefetchAsync@PLT
	movslq	92(%rsp), %rsi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	movq	80(%rsp), %rdi
	call	cudaMemPrefetchAsync@PLT
	movslq	116(%rsp), %rsi
	xorl	%ecx, %ecx
	orl	$-1, %edx
	movq	104(%rsp), %rdi
	call	cudaMemPrefetchAsync@PLT
	movl	100(%rsp), %edx
	movl	96(%rsp), %esi
	leaq	120(%rsp), %rdi
	call	_ZN10CudaObject7setSizeEii
	movq	80(%rsp), %rdi
	movq	104(%rsp), %r8
	xorl	%edx, %edx
	movq	128(%rsp), %r9
.L65:
	cmpl	96(%rsp), %edx
	jge	.L87
	xorl	%ecx, %ecx
.L67:
	cmpl	100(%rsp), %ecx
	jge	.L89
	movl	120(%rsp), %eax
	imull	%edx, %eax
	addl	%ecx, %eax
	incl	%ecx
	cltq
	movl	(%rdi,%rax,4), %esi
	subl	(%r8,%rax,4), %esi
	movl	%esi, (%r9,%rax,4)
	jmp	.L67
.L89:
	incl	%edx
	jmp	.L65
.L53:
	movq	96(%rsp), %rax
	cmpq	%rax, 72(%rsp)
	jne	.L62
	movl	56(%rsp), %ecx
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdx
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L77
	movl	124(%rsp), %r8d
	movl	120(%rsp), %ecx
	movq	128(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z28__device_stub__Z3subPiS_S_iiPiS_S_ii
	jmp	.L77
.L52:
	cmpl	%eax, %ecx
	je	.L70
.L76:
	leaq	.LC16(%rip), %rsi
	jmp	.L84
.L70:
	movslq	100(%rsp), %rdx
	movq	80(%rsp), %r12
	xorl	%esi, %esi
	xorl	%edi, %edi
	movq	128(%rsp), %r14
	movq	104(%rsp), %r15
	xorl	%r8d, %r8d
	leaq	0(,%rdx,4), %rcx
	movq	%rdx, %rbx
	movq	%rcx, 8(%rsp)
.L71:
	cmpl	120(%rsp), %r8d
	jge	.L87
	movslq	%edi, %rdx
	leaq	(%r14,%rdx,4), %r13
	movslq	%esi, %rdx
	leaq	(%r12,%rdx,4), %rbp
	xorl	%edx, %edx
.L75:
	cmpl	%edx, 124(%rsp)
	jle	.L73
	leaq	(%r15,%rdx,4), %r10
	xorl	%ecx, %ecx
	xorl	%r9d, %r9d
.L74:
	cmpl	%ecx, %eax
	jle	.L90
	movl	0(%rbp,%rcx,4), %r11d
	imull	(%r10), %r11d
	incq	%rcx
	addl	%r11d, %r9d
	movq	8(%rsp), %r11
	addq	%r11, %r10
	jmp	.L74
.L90:
	movl	%r9d, 0(%r13,%rdx,4)
	incq	%rdx
	jmp	.L75
.L73:
	incl	%r8d
	addl	%ebx, %edi
	addl	%eax, %esi
	jmp	.L71
.L51:
	cmpl	%eax, %ecx
	jne	.L76
	movl	56(%rsp), %ecx
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdx
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L77
	movq	120(%rsp), %rax
	leaq	192(%rsp), %rdx
	leaq	168(%rsp), %rsi
	leaq	144(%rsp), %rdi
	movq	%rax, 192(%rsp)
	movq	128(%rsp), %rax
	movq	%rax, 200(%rsp)
	movl	136(%rsp), %eax
	movl	%eax, 208(%rsp)
	movq	96(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	104(%rsp), %rax
	movq	%rax, 176(%rsp)
	movl	112(%rsp), %eax
	movl	%eax, 184(%rsp)
	movq	72(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	80(%rsp), %rax
	movq	%rax, 152(%rsp)
	movl	88(%rsp), %eax
	movl	%eax, 160(%rsp)
	call	_Z36__device_stub__Z3mul10CudaObjectS_S_R10CudaObjectS0_S0_
.L77:
	call	cudaDeviceSynchronize@PLT
.L87:
	leaq	120(%rsp), %rdi
	jmp	.L85
.L50:
	movq	%rbx, %rdi
	leaq	.LC17(%rip), %rsi
	leaq	120(%rsp), %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r12, %rsi
	movq	%rbp, %rdi
	call	_ZN10CudaObject7tranCpuERS_
	movq	%rbp, %rdi
	call	_ZN10CudaObject8writeOutEv
	movq	%rbx, %rdi
	leaq	.LC18(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r13, %rsi
	movq	%rbp, %rdi
	call	_ZN10CudaObject7tranCpuERS_
	jmp	.L86
.L48:
	leaq	.LC17(%rip), %rsi
	movq	%rbx, %rdi
	leaq	120(%rsp), %rbp
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	24(%rsp), %edx
	movl	32(%rsp), %esi
	movq	%rbp, %rdi
	call	_ZN10CudaObject7setSizeEii
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdx
	movq	%rdx, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L78
	movq	120(%rsp), %rax
	leaq	192(%rsp), %rsi
	leaq	168(%rsp), %rdi
	movq	%rax, 192(%rsp)
	movq	128(%rsp), %rax
	movq	%rax, 200(%rsp)
	movl	136(%rsp), %eax
	movl	%eax, 208(%rsp)
	movq	72(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	movl	88(%rsp), %eax
	movl	%eax, 184(%rsp)
	call	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_
.L78:
	call	cudaDeviceSynchronize@PLT
	movq	%rbp, %rdi
	call	_ZN10CudaObject8writeOutEv
	leaq	.LC18(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	28(%rsp), %edx
	movl	36(%rsp), %esi
	movq	%rbp, %rdi
	call	_ZN10CudaObject7setSizeEii
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	movq	120(%rsp), %rax
	leaq	192(%rsp), %rsi
	leaq	168(%rsp), %rdi
	movq	%rax, 192(%rsp)
	movq	128(%rsp), %rax
	movq	%rax, 200(%rsp)
	movl	136(%rsp), %eax
	movl	%eax, 208(%rsp)
	movq	96(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	104(%rsp), %rax
	movq	%rax, 176(%rsp)
	movl	112(%rsp), %eax
	movl	%eax, 184(%rsp)
	call	_Z35__device_stub__Z4tran10CudaObjectS_R10CudaObjectS0_
.L79:
	call	cudaDeviceSynchronize@PLT
.L86:
	movq	%rbp, %rdi
.L85:
	call	_ZN10CudaObject8writeOutEv
	jmp	.L58
.L47:
	leaq	.LC19(%rip), %rsi
.L84:
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L58:
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L80
	call	__stack_chk_fail@PLT
.L80:
	addq	$232, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3652:
	.size	main, .-main
	.section	.rodata.str1.1
.LC20:
	.string	"_Z4tran10CudaObjectS_"
.LC21:
	.string	"_Z3mul10CudaObjectS_S_"
.LC22:
	.string	"_Z3subPiS_S_ii"
.LC23:
	.string	"_Z3addPiS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3686:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z4tran10CudaObjectS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3mul10CudaObjectS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3subPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3addPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3686:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 ============================================================================
 Name        : CudaProject.cu
 Author      : Adrianna Urbańska, Gabriel Chęć
 Version     :
 Copyright   : 
 Description : CUDA compute reciprocals
 ============================================================================
 */

#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 32

class CudaObject {

public:
	int size_x;
	int size_y;
	int *data;
	int stride;
	int bytes;
	
	__host__ __device__
	CudaObject(int x, int y, int stride ): size_x(x), size_y(y),stride(stride){}
	
	__host__ __device__	
	CudaObject(const CudaObject &a): size_x(a.size_x), size_y(a.size_y),data(a.data),stride(a.stride){}
	
	__device__ 
	int getElement(int row, int col){
		return data[row * stride + col];
	}

	__device__
	 void setElement(int row, int col, int val){
		data[row * stride + col] = val;
	}
	
	__device__
	CudaObject cutMatrix(int row, int col){
		CudaObject tmp(BLOCK_SIZE, BLOCK_SIZE, stride);
		
		tmp.data = &data[stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
		return tmp;
	}
	
	__host__  
	 void writeOut(){
		for(int i = 0; i < size_x; i++){
			std::cout<<"| ";
		 	for(int j = 0; j < size_y; j++){
		 		std::cout<<data[i * size_y + j]<<" ";
		 	}
			std::cout<<"|"<<std::endl;
		 }
		std::cout<<"\n";
	}

	void setSize(int x, int y){
		this->size_x = x;
		this->size_y = y;
		this->bytes = x * y * sizeof(int);
		hipMallocManaged(&this->data, this->bytes);
	}


	void addCpu(CudaObject &fData, CudaObject &sData){
		if(fData.size_x == sData.size_x && fData.size_y == sData.size_y){
			hipMemPrefetchAsync(this->data, this->bytes, hipCpuDeviceId);
			hipMemPrefetchAsync(fData.data, fData.bytes, hipCpuDeviceId);
			hipMemPrefetchAsync(sData.data, sData.bytes, hipCpuDeviceId);

			this->setSize(sData.size_x, sData.size_y);

			for(int i = 0; i < sData.size_x; i++){
				for(int j = 0; j < sData.size_y; j++){
					this->data[i * this->size_x + j] = fData.data[i * this->size_x + j] + sData.data[i * this->size_x + j];
				}
			}
		}
	}

	void subCpu(CudaObject &fData, CudaObject &sData){
		if(fData.size_x == sData.size_x && fData.size_y == sData.size_y){
			hipMemPrefetchAsync(this->data, this->bytes, hipCpuDeviceId);
			hipMemPrefetchAsync(fData.data, fData.bytes, hipCpuDeviceId);
			hipMemPrefetchAsync(sData.data, sData.bytes, hipCpuDeviceId);

			this->setSize(sData.size_x, sData.size_y);

			for(int i = 0; i < sData.size_x; i++){
				for(int j = 0; j < sData.size_y; j++){
					this->data[i * this->size_x + j] = fData.data[i * this->size_x + j] - sData.data[i * this->size_x + j];
				}
			}
		}
	}

	void mulCpu(CudaObject &fData, CudaObject &sData){
		int y_s = sData.size_y;
		int y_f = fData.size_y;
  		for(int i = 0; i < size_x; i++ ){
    		for(int j = 0; j < size_y; j++ ){
      			int s = 0;
      			for(int k = 0; k < y_f; k++ ) 
					s += fData.data[i * y_f + k] * sData.data[k * y_s + j];
				this->data[i * y_s + j] = s;
    		}
		}
	}

	void tranCpu(CudaObject &iData){

	 	int x = iData.size_x;
		int y = iData.size_y;

		this->setSize(y,x);

		for(int n = 0; n < x * y; n++){
			int i = n/x;
			int j = n%x;
			this->data[n] = iData.data[y * j + i];
		}
	}

};

__global__ void add(int *fData, int *sData, int *oData, int x, int y){

	int index = threadIdx.x + blockIdx.x * blockDim.x;
	int stride = blockDim.x * gridDim.x;
	
	for(int i = index; i < x*y; i += stride)
	{
		oData[i] = fData[i] + sData[i];
	}
}

__global__ void sub(int *fData, int *sData, int *oData, int x, int y){

	  int index = threadIdx.x + blockIdx.x * blockDim.x;
	  int stride = blockDim.x * gridDim.x;

	  for(int i = index; i < x * y; i += stride)
	  {
	    oData[i] = fData[i] - sData[i];
	  }
}


__global__ void mul(CudaObject a,CudaObject b, CudaObject c) {
	int cutRow = blockIdx.y ;
	int cutCol = blockIdx.x;

	int fRow = blockIdx.y * blockDim.y + threadIdx.y;
	int fCol = blockIdx.x * blockDim.x + threadIdx.x;	
	int row = threadIdx.y;
	int col = threadIdx.x;
	
	int temp = 0;
	
	CudaObject cutMatC = c.cutMatrix(cutRow, cutCol);
	
	for( int v = 0; v < ((a.size_y + BLOCK_SIZE - 1)/BLOCK_SIZE); ++v){
		CudaObject cutMatA = a.cutMatrix(cutRow, v);	//cut input matrix vector which can fit inside block
		CudaObject cutMatB = b.cutMatrix(v, cutCol);	
	
		__shared__ int A[BLOCK_SIZE][BLOCK_SIZE];	//Matrix wchich can share memory between threads
		__shared__ int B[BLOCK_SIZE][BLOCK_SIZE];
		if((row  < a.size_x) && ((col + v * BLOCK_SIZE) < a.size_y)){ 		
			A[row][col] = cutMatA.getElement(row, col);
		}
		else{
			A[row][col] = 0;
		}

		if((col < b.size_y) && ((row + v * BLOCK_SIZE) < b.size_x)){
			B[row][col] = cutMatB.getElement(row, col);
		}
		else{
			B[row][col] = 0;
		}

		__syncthreads();				//make sure that every metrix is filled
	
		for (int i = 0; i < BLOCK_SIZE; ++i){
			temp += A[row][i] * B[i][col];
		}		
		__syncthreads();
	
	}

	if(fRow < c.size_x && fCol < c.size_y)
		c.setElement(fRow, fCol, temp);
}

__global__ void tran(CudaObject iData, CudaObject oData){

	int index = threadIdx.x + blockIdx.x * blockDim.x;
	int stride = blockDim.x * gridDim.x;
	int x = iData.size_x;
	int y = iData.size_y;

	for(int n = index; n < x * y; n += stride){
		int i = n/x;
		int j = n%x;
		oData.data[n] = iData.data[y * j + i];
	}
}

void OperationsInfo()
{
	std::cout<<"Choose an operation:"<<std::endl;
	std::cout<<"1. Matrix addition on CPU"<<std::endl;
	std::cout<<"2. Matrix addition on GPU"<<std::endl;
	std::cout<<"3. Matrix substraction on CPU"<<std::endl;
	std::cout<<"4. Matrix substraction on GPU"<<std::endl;
	std::cout<<"5. Matrix multiplication on CPU"<<std::endl;
	std::cout<<"6. Matrix multiplication on GPU"<<std::endl;
	std::cout<<"7. Matrix transposition on CPU"<<std::endl;
	std::cout<<"8. Matrix transposition on GPU"<<std::endl;
}


void Init(CudaObject &oData, int val)
{
	int x = oData.size_x;
	int y = oData.size_y;

	for(int i = 0; i < y; i++){
		for(int j = 0; j<x; j++){
			oData.data[i*x+j] = val;  
		}
	}
}

int main(){

	int operation;
	int N_1, N_2, M_1, M_2;
	int val_1, val_2;

	std::cout<<"Enter the values of size_x, size_y of the first matrix and value to filled matrix:"<<std::endl;
	std::cin>>N_1;
	std::cin>>M_1;
	std::cin>>val_1;

	std::cout<<"Enter the values of size_x, size_y of the second matrix and value to filled matrix:"<<std::endl;
	std::cin>>N_2;
	std::cin>>M_2;
	std::cin>>val_2;

	CudaObject fData(N_1, M_1, M_1), sData(N_2, M_2, M_2), oData(N_1, M_2, M_2);

	hipMallocManaged(&fData.data,N_1 * M_1 * sizeof(int));
	hipMallocManaged(&sData.data, N_2 * M_2 * sizeof(int));
	hipMallocManaged(&oData.data, N_1 * M_2 * sizeof(int));

	Init(fData,val_1);
	Init(sData,val_2);

	fData.writeOut();	
	sData.writeOut();

	OperationsInfo();
	std::cin>>operation;

	dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE);
	dim3 blocksPerGrid((fData.size_y + threadsPerBlock.x - 1)/threadsPerBlock.x, (sData.size_x + threadsPerBlock.y - 1)/threadsPerBlock.y);

	switch(operation)
	{
		case 1:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				oData.addCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 2:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				add<<<blocksPerGrid,threadsPerBlock>>>(fData.data, sData.data, oData.data, oData.size_x, oData.size_y);
				hipDeviceSynchronize();
				oData.writeOut();
			}
			break;
		case 3:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				oData.subCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 4:
			if(fData.size_x != sData.size_x || fData.size_y != sData.size_y){
				std::cout<<"Matrices sizes have to be equal!"<<std::endl;
			}
			else{
				sub<<<blocksPerGrid,threadsPerBlock>>>(fData.data, sData.data, oData.data, oData.size_x, oData.size_y);
				hipDeviceSynchronize();
				oData.writeOut();
			}
			break;
		case 5:
			if(fData.size_y != sData.size_x){
				std::cout<<"Size_x of the first matrix and size_y of the second matrix have to be equal!"<<std::endl;
			}
			else{
				oData.mulCpu(fData,sData);
				oData.writeOut();
			}
			break;
		case 6:
			if(fData.size_y != sData.size_x){
				std::cout<<"Size_x of the first matrix and size_y of the second matrix have to be equal!"<<std::endl;
			}
			else{
				mul<<<blocksPerGrid, threadsPerBlock>>>(fData, sData, oData);	
				hipDeviceSynchronize();
				oData.writeOut();
			}			
			break;
		case 7:
			std::cout<<"Transposition of the first matrix: "<<std::endl;
			oData.tranCpu(fData);
			oData.writeOut();

			std::cout<<"Transposition of the second matrix: "<<std::endl;	
			oData.tranCpu(sData);
			oData.writeOut();
		
			break;
		case 8:
			std::cout<<"Transposition of the first matrix: "<<std::endl;
			oData.setSize(M_1,N_1);
			tran<<<blocksPerGrid, threadsPerBlock>>>(fData, oData);	
			hipDeviceSynchronize();
			oData.writeOut();

			std::cout<<"Transposition of the second matrix: "<<std::endl;
			oData.setSize(M_2,N_2);
			tran<<<blocksPerGrid, threadsPerBlock>>>(sData, oData);	
			hipDeviceSynchronize();
			oData.writeOut();
		
			break;
		default:
			std::cout<<"Wrong number entered!"<<std::endl;
			break;
	}
	
	hipError_t err = hipSuccess;	
		
	if (err != hipSuccess){	
        	fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
        	exit(EXIT_FAILURE);
    	}
			
	hipFree(fData.data);
	hipFree(sData.data);
	hipFree(oData.data);
}	

	.text
	.file	"main.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__addPiS_S_ii  # -- Begin function _Z18__device_stub__addPiS_S_ii
	.type	_Z18__device_stub__addPiS_S_ii,@function
_Z18__device_stub__addPiS_S_ii:         # @_Z18__device_stub__addPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__addPiS_S_ii, .Lfunc_end0-_Z18__device_stub__addPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__subPiS_S_ii  # -- Begin function _Z18__device_stub__subPiS_S_ii
	.type	_Z18__device_stub__subPiS_S_ii,@function
_Z18__device_stub__subPiS_S_ii:         # @_Z18__device_stub__subPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3subPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__subPiS_S_ii, .Lfunc_end1-_Z18__device_stub__subPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__mul10CudaObjectS_S_ # -- Begin function _Z18__device_stub__mul10CudaObjectS_S_
	.type	_Z18__device_stub__mul10CudaObjectS_S_,@function
_Z18__device_stub__mul10CudaObjectS_S_: # @_Z18__device_stub__mul10CudaObjectS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	48(%rsp), %rbx
	movq	%rdi, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3mul10CudaObjectS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z18__device_stub__mul10CudaObjectS_S_, .Lfunc_end2-_Z18__device_stub__mul10CudaObjectS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z19__device_stub__tran10CudaObjectS_ # -- Begin function _Z19__device_stub__tran10CudaObjectS_
	.type	_Z19__device_stub__tran10CudaObjectS_,@function
_Z19__device_stub__tran10CudaObjectS_:  # @_Z19__device_stub__tran10CudaObjectS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	48(%rsp), %rbx
	movq	%rdi, (%rbx)
	movq	%rsi, 8(%rbx)
	leaq	32(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4tran10CudaObjectS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z19__device_stub__tran10CudaObjectS_, .Lfunc_end3-_Z19__device_stub__tran10CudaObjectS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z14OperationsInfov             # -- Begin function _Z14OperationsInfov
	.type	_Z14OperationsInfov,@function
_Z14OperationsInfov:                    # @_Z14OperationsInfov
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$29, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$29, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$30, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end4:
	.size	_Z14OperationsInfov, .Lfunc_end4-_Z14OperationsInfov
	.cfi_endproc
                                        # -- End function
	.globl	_Z4InitR10CudaObjecti           # -- Begin function _Z4InitR10CudaObjecti
	.type	_Z4InitR10CudaObjecti,@function
_Z4InitR10CudaObjecti:                  # @_Z4InitR10CudaObjecti
	.cfi_startproc
# %bb.0:
	movl	4(%rdi), %eax
	testl	%eax, %eax
	jle	.LBB5_6
# %bb.1:                                # %.preheader.lr.ph
	movl	(%rdi), %ecx
	movq	8(%rdi), %rdx
	xorl	%edi, %edi
	xorl	%r8d, %r8d
.LBB5_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB5_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB5_2 Depth=1
	movl	%edi, %r9d
	leaq	(%rdx,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB5_4:                                #   Parent Loop BB5_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%esi, (%r9,%r10,4)
	incq	%r10
	cmpq	%r10, %rcx
	jne	.LBB5_4
.LBB5_5:                                # %._crit_edge
                                        #   in Loop: Header=BB5_2 Depth=1
	incq	%r8
	addl	%ecx, %edi
	cmpq	%rax, %r8
	jne	.LBB5_2
.LBB5_6:                                # %._crit_edge16
	retq
.Lfunc_end5:
	.size	_Z4InitR10CudaObjecti, .Lfunc_end5-_Z4InitR10CudaObjecti
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$_ZSt4cout, %r15d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.9, %esi
	movl	$82, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	104(%rsp), %r14
	movl	$_ZSt3cin, %edi
	movq	%r14, %rsi
	callq	_ZNSirsERi
	leaq	96(%rsp), %rbx
	movl	$_ZSt3cin, %edi
	movq	%rbx, %rsi
	callq	_ZNSirsERi
	leaq	88(%rsp), %rsi
	movl	$_ZSt3cin, %edi
	callq	_ZNSirsERi
	movl	$_ZSt4cout, %edi
	movl	$.L.str.10, %esi
	movl	$83, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	100(%rsp), %r13
	movl	$_ZSt3cin, %edi
	movq	%r13, %rsi
	callq	_ZNSirsERi
	leaq	92(%rsp), %r15
	movl	$_ZSt3cin, %edi
	movq	%r15, %rsi
	callq	_ZNSirsERi
	leaq	84(%rsp), %rsi
	movl	$_ZSt3cin, %edi
	callq	_ZNSirsERi
	movl	(%r14), %eax
	movl	(%rbx), %ecx
	leaq	64(%rsp), %r12
	movl	%eax, -8(%r12)
	movl	%ecx, -4(%r12)
	movl	%ecx, 8(%r12)
	movl	(%r13), %edx
	movl	(%r15), %esi
	leaq	40(%rsp), %rbp
	movl	%edx, -8(%rbp)
	movl	%esi, -4(%rbp)
	movl	%esi, 8(%rbp)
	leaq	16(%rsp), %rbx
	movl	%eax, -8(%rbx)
	movl	%esi, -4(%rbx)
	movl	%esi, 8(%rbx)
	imull	%eax, %ecx
	movslq	%ecx, %rsi
	shlq	$2, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	(%r13), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movslq	(%r14), %rax
	movslq	(%r15), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	-4(%r12), %eax
	testl	%eax, %eax
	jle	.LBB6_6
# %bb.1:                                # %.preheader.lr.ph.i
	movl	88(%rsp), %ecx
	movl	56(%rsp), %edx
	xorl	%esi, %esi
	movq	64(%rsp), %rdi
	xorl	%r8d, %r8d
.LBB6_2:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_4 Depth 2
	testl	%edx, %edx
	jle	.LBB6_5
# %bb.3:                                # %.lr.ph.i
                                        #   in Loop: Header=BB6_2 Depth=1
	movl	%esi, %r9d
	leaq	(%rdi,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB6_4:                                #   Parent Loop BB6_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ecx, (%r9,%r10,4)
	incq	%r10
	cmpq	%r10, %rdx
	jne	.LBB6_4
.LBB6_5:                                # %._crit_edge.i
                                        #   in Loop: Header=BB6_2 Depth=1
	incq	%r8
	addl	%edx, %esi
	cmpq	%rax, %r8
	jne	.LBB6_2
.LBB6_6:                                # %_Z4InitR10CudaObjecti.exit
	movl	36(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB6_12
# %bb.7:                                # %.preheader.lr.ph.i55
	movl	84(%rsp), %ecx
	movl	32(%rsp), %edx
	xorl	%esi, %esi
	movq	40(%rsp), %rdi
	xorl	%r8d, %r8d
.LBB6_8:                                # %.preheader.i58
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_10 Depth 2
	testl	%edx, %edx
	jle	.LBB6_11
# %bb.9:                                # %.lr.ph.i63
                                        #   in Loop: Header=BB6_8 Depth=1
	movl	%esi, %r9d
	leaq	(%rdi,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB6_10:                               #   Parent Loop BB6_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ecx, (%r9,%r10,4)
	incq	%r10
	cmpq	%r10, %rdx
	jne	.LBB6_10
.LBB6_11:                               # %._crit_edge.i60
                                        #   in Loop: Header=BB6_8 Depth=1
	incq	%r8
	addl	%edx, %esi
	cmpq	%rax, %r8
	jne	.LBB6_8
.LBB6_12:                               # %_Z4InitR10CudaObjecti.exit69
	leaq	56(%rsp), %rdi
	callq	_ZN10CudaObject8writeOutEv
	leaq	32(%rsp), %rdi
	callq	_ZN10CudaObject8writeOutEv
	callq	_Z14OperationsInfov
	leaq	108(%rsp), %r14
	movl	$_ZSt3cin, %edi
	movq	%r14, %rsi
	callq	_ZNSirsERi
	movl	(%r14), %ecx
	decl	%ecx
	cmpl	$7, %ecx
	ja	.LBB6_43
# %bb.13:                               # %_Z4InitR10CudaObjecti.exit69
	movl	60(%rsp), %eax
	leal	31(%rax), %esi
	shrl	$5, %esi
	movl	32(%rsp), %edx
	leal	31(%rdx), %r14d
	shrl	$5, %r14d
	shlq	$32, %r14
	orq	%rsi, %r14
	jmpq	*.LJTI6_0(,%rcx,8)
.LBB6_14:
	cmpl	%edx, 56(%rsp)
	jne	.LBB6_34
# %bb.15:
	cmpl	36(%rsp), %eax
	jne	.LBB6_34
# %bb.16:
	leaq	8(%rsp), %rbx
	leaq	56(%rsp), %rsi
	leaq	32(%rsp), %rdx
	movq	%rbx, %rdi
	callq	_ZN10CudaObject6addCpuERS_S0_
	jmp	.LBB6_41
.LBB6_17:
	cmpl	%edx, %eax
	jne	.LBB6_39
# %bb.18:
	leaq	8(%rsp), %rbx
	leaq	56(%rsp), %rsi
	leaq	32(%rsp), %rdx
	movq	%rbx, %rdi
	callq	_ZN10CudaObject6mulCpuERS_S0_
	jmp	.LBB6_41
.LBB6_19:
	cmpl	%edx, 56(%rsp)
	jne	.LBB6_34
# %bb.20:
	cmpl	36(%rsp), %eax
	jne	.LBB6_34
# %bb.21:
	leaq	8(%rsp), %rbx
	leaq	56(%rsp), %rsi
	leaq	32(%rsp), %rdx
	movq	%rbx, %rdi
	callq	_ZN10CudaObject6subCpuERS_S0_
	jmp	.LBB6_41
.LBB6_22:
	cmpl	%edx, 56(%rsp)
	jne	.LBB6_34
# %bb.23:
	cmpl	36(%rsp), %eax
	jne	.LBB6_34
# %bb.24:
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_38
# %bb.25:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	8(%rsp), %ecx
	movl	12(%rsp), %r8d
	callq	_Z18__device_stub__subPiS_S_ii
	jmp	.LBB6_38
.LBB6_26:
	movabsq	$137438953504, %r15             # imm = 0x2000000020
	movl	$_ZSt4cout, %r13d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$35, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	96(%rsp), %eax
	movl	104(%rsp), %ecx
	movl	%eax, 8(%rsp)
	movl	%ecx, 12(%rsp)
	imull	%ecx, %eax
	shll	$2, %eax
	movl	%eax, 28(%rsp)
	movslq	%eax, %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_28
# %bb.27:
	movups	56(%rsp), %xmm0
	leaq	184(%rsp), %rdi
	movups	%xmm0, (%rdi)
	movl	72(%rsp), %eax
	movl	%eax, 16(%rdi)
	movups	8(%rsp), %xmm0
	leaq	160(%rsp), %rsi
	movups	%xmm0, (%rsi)
	movl	24(%rsp), %eax
	movl	%eax, 16(%rsi)
	callq	_Z19__device_stub__tran10CudaObjectS_
.LBB6_28:
	callq	hipDeviceSynchronize
	leaq	8(%rsp), %r12
	movq	%r12, %rdi
	callq	_ZN10CudaObject8writeOutEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r13, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	92(%rsp), %eax
	movl	100(%rsp), %ecx
	movl	%eax, (%r12)
	movl	%ecx, 4(%r12)
	imull	%ecx, %eax
	shll	$2, %eax
	movl	%eax, 20(%r12)
	movslq	%eax, %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_38
# %bb.29:
	movups	32(%rsp), %xmm0
	leaq	136(%rsp), %rdi
	movups	%xmm0, (%rdi)
	movl	48(%rsp), %eax
	movl	%eax, 16(%rdi)
	movups	8(%rsp), %xmm0
	leaq	112(%rsp), %rsi
	movups	%xmm0, (%rsi)
	movl	24(%rsp), %eax
	movl	%eax, 16(%rsi)
	callq	_Z19__device_stub__tran10CudaObjectS_
	jmp	.LBB6_38
.LBB6_30:
	cmpl	%edx, 56(%rsp)
	jne	.LBB6_34
# %bb.31:
	cmpl	36(%rsp), %eax
	jne	.LBB6_34
# %bb.32:
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_38
# %bb.33:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	8(%rsp), %ecx
	movl	12(%rsp), %r8d
	callq	_Z18__device_stub__addPiS_S_ii
	jmp	.LBB6_38
.LBB6_34:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.11, %esi
	movl	$32, %edx
	jmp	.LBB6_44
.LBB6_35:
	cmpl	%edx, %eax
	jne	.LBB6_39
# %bb.36:
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movq	%r14, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_38
# %bb.37:
	movups	56(%rsp), %xmm0
	leaq	256(%rsp), %rdi
	movups	%xmm0, (%rdi)
	movl	72(%rsp), %eax
	movl	%eax, 16(%rdi)
	movups	32(%rsp), %xmm0
	leaq	232(%rsp), %rsi
	movups	%xmm0, (%rsi)
	movl	48(%rsp), %eax
	movl	%eax, 16(%rsi)
	movups	8(%rsp), %xmm0
	leaq	208(%rsp), %rdx
	movups	%xmm0, (%rdx)
	movl	24(%rsp), %eax
	movl	%eax, 16(%rdx)
	callq	_Z18__device_stub__mul10CudaObjectS_S_
.LBB6_38:
	callq	hipDeviceSynchronize
	leaq	8(%rsp), %rdi
	jmp	.LBB6_42
.LBB6_39:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$76, %edx
	jmp	.LBB6_44
.LBB6_40:
	movl	$_ZSt4cout, %r14d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$35, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	8(%rsp), %rbx
	leaq	56(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_ZN10CudaObject7tranCpuERS_
	movq	%rbx, %rdi
	callq	_ZN10CudaObject8writeOutEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$36, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	32(%rsp), %rsi
	movq	%rbx, %rdi
	callq	_ZN10CudaObject7tranCpuERS_
.LBB6_41:
	movq	%rbx, %rdi
.LBB6_42:
	callq	_ZN10CudaObject8writeOutEv
	jmp	.LBB6_45
.LBB6_43:
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str.15, %esi
	movl	$21, %edx
.LBB6_44:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB6_45:
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	main, .Lfunc_end6-main
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI6_0:
	.quad	.LBB6_14
	.quad	.LBB6_30
	.quad	.LBB6_19
	.quad	.LBB6_22
	.quad	.LBB6_17
	.quad	.LBB6_35
	.quad	.LBB6_40
	.quad	.LBB6_26
                                        # -- End function
	.section	.text._ZN10CudaObject8writeOutEv,"axG",@progbits,_ZN10CudaObject8writeOutEv,comdat
	.weak	_ZN10CudaObject8writeOutEv      # -- Begin function _ZN10CudaObject8writeOutEv
	.p2align	1, 0x90
	.type	_ZN10CudaObject8writeOutEv,@function
_ZN10CudaObject8writeOutEv:             # @_ZN10CudaObject8writeOutEv
	.cfi_startproc
# %bb.0:
	cmpl	$0, (%rdi)
	jle	.LBB7_7
# %bb.1:                                # %.lr.ph11
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	xorl	%r14d, %r14d
	movl	$_ZSt4cout, %r15d
.LBB7_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_4 Depth 2
	movl	$_ZSt4cout, %edi
	movl	$.L.str.17, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	4(%rbx), %eax
	testl	%eax, %eax
	jle	.LBB7_5
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB7_2 Depth=1
	xorl	%r12d, %r12d
.LBB7_4:                                # %.lr.ph
                                        #   Parent Loop BB7_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	8(%rbx), %rcx
	imull	%r14d, %eax
	cltq
	addq	%r12, %rax
	movl	(%rcx,%rax,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.18, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	4(%rbx), %eax
	incq	%r12
	cmpl	%eax, %r12d
	jl	.LBB7_4
.LBB7_5:                                # %._crit_edge
                                        #   in Loop: Header=BB7_2 Depth=1
	movl	$_ZSt4cout, %edi
	movl	$.L.str.19, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incl	%r14d
	cmpl	(%rbx), %r14d
	jl	.LBB7_2
# %bb.6:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r14
	.cfi_restore %r15
.LBB7_7:                                # %._crit_edge12
	movl	$_ZSt4cout, %edi
	movl	$.L.str.20, %esi
	movl	$1, %edx
	jmp	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end7:
	.size	_ZN10CudaObject8writeOutEv, .Lfunc_end7-_ZN10CudaObject8writeOutEv
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN10CudaObject6addCpuERS_S0_,"axG",@progbits,_ZN10CudaObject6addCpuERS_S0_,comdat
	.weak	_ZN10CudaObject6addCpuERS_S0_   # -- Begin function _ZN10CudaObject6addCpuERS_S0_
	.p2align	1, 0x90
	.type	_ZN10CudaObject6addCpuERS_S0_,@function
_ZN10CudaObject6addCpuERS_S0_:          # @_ZN10CudaObject6addCpuERS_S0_
	.cfi_startproc
# %bb.0:
	movl	(%rsi), %eax
	cmpl	(%rdx), %eax
	jne	.LBB8_10
# %bb.1:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r15
	movl	4(%rsi), %eax
	cmpl	4(%rdx), %eax
	jne	.LBB8_9
# %bb.2:
	movq	%rdi, %r14
	leaq	8(%rdi), %r12
	movq	8(%rdi), %rdi
	movslq	20(%r14), %rsi
	xorl	%r13d, %r13d
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movq	8(%r15), %rdi
	movslq	20(%r15), %rsi
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movq	8(%rbx), %rdi
	movslq	20(%rbx), %rsi
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movl	(%rbx), %eax
	movl	4(%rbx), %ecx
	movl	%eax, (%r14)
	movl	%ecx, 4(%r14)
	imull	%ecx, %eax
	shll	$2, %eax
	movl	%eax, 20(%r14)
	movslq	%eax, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	(%rbx), %edi
	testl	%edi, %edi
	jle	.LBB8_9
# %bb.3:                                # %.preheader.lr.ph
	movq	8(%r15), %rax
	movq	8(%rbx), %rcx
	movq	(%r12), %rdx
	movl	4(%rbx), %esi
.LBB8_4:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB8_6 Depth 2
	testl	%esi, %esi
	jle	.LBB8_8
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB8_4 Depth=1
	movslq	%r13d, %rdi
	xorl	%r8d, %r8d
.LBB8_6:                                # %.lr.ph
                                        #   Parent Loop BB8_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%r14), %rsi
	imulq	%rdi, %rsi
	addq	%r8, %rsi
	movl	(%rcx,%rsi,4), %r9d
	addl	(%rax,%rsi,4), %r9d
	movl	%r9d, (%rdx,%rsi,4)
	movl	4(%rbx), %esi
	incq	%r8
	cmpl	%esi, %r8d
	jl	.LBB8_6
# %bb.7:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB8_4 Depth=1
	movl	(%rbx), %edi
.LBB8_8:                                # %._crit_edge
                                        #   in Loop: Header=BB8_4 Depth=1
	incl	%r13d
	cmpl	%edi, %r13d
	jl	.LBB8_4
.LBB8_9:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB8_10:                               # %.loopexit
	retq
.Lfunc_end8:
	.size	_ZN10CudaObject6addCpuERS_S0_, .Lfunc_end8-_ZN10CudaObject6addCpuERS_S0_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN10CudaObject6subCpuERS_S0_,"axG",@progbits,_ZN10CudaObject6subCpuERS_S0_,comdat
	.weak	_ZN10CudaObject6subCpuERS_S0_   # -- Begin function _ZN10CudaObject6subCpuERS_S0_
	.p2align	1, 0x90
	.type	_ZN10CudaObject6subCpuERS_S0_,@function
_ZN10CudaObject6subCpuERS_S0_:          # @_ZN10CudaObject6subCpuERS_S0_
	.cfi_startproc
# %bb.0:
	movl	(%rsi), %eax
	cmpl	(%rdx), %eax
	jne	.LBB9_10
# %bb.1:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r15
	movl	4(%rsi), %eax
	cmpl	4(%rdx), %eax
	jne	.LBB9_9
# %bb.2:
	movq	%rdi, %r14
	leaq	8(%rdi), %r12
	movq	8(%rdi), %rdi
	movslq	20(%r14), %rsi
	xorl	%r13d, %r13d
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movq	8(%r15), %rdi
	movslq	20(%r15), %rsi
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movq	8(%rbx), %rdi
	movslq	20(%rbx), %rsi
	movl	$-1, %edx
	xorl	%ecx, %ecx
	callq	hipMemPrefetchAsync
	movl	(%rbx), %eax
	movl	4(%rbx), %ecx
	movl	%eax, (%r14)
	movl	%ecx, 4(%r14)
	imull	%ecx, %eax
	shll	$2, %eax
	movl	%eax, 20(%r14)
	movslq	%eax, %rsi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	(%rbx), %edi
	testl	%edi, %edi
	jle	.LBB9_9
# %bb.3:                                # %.preheader.lr.ph
	movq	8(%r15), %rax
	movq	8(%rbx), %rcx
	movq	(%r12), %rdx
	movl	4(%rbx), %esi
.LBB9_4:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB9_6 Depth 2
	testl	%esi, %esi
	jle	.LBB9_8
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB9_4 Depth=1
	movslq	%r13d, %rdi
	xorl	%r8d, %r8d
.LBB9_6:                                # %.lr.ph
                                        #   Parent Loop BB9_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%r14), %rsi
	imulq	%rdi, %rsi
	addq	%r8, %rsi
	movl	(%rax,%rsi,4), %r9d
	subl	(%rcx,%rsi,4), %r9d
	movl	%r9d, (%rdx,%rsi,4)
	movl	4(%rbx), %esi
	incq	%r8
	cmpl	%esi, %r8d
	jl	.LBB9_6
# %bb.7:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB9_4 Depth=1
	movl	(%rbx), %edi
.LBB9_8:                                # %._crit_edge
                                        #   in Loop: Header=BB9_4 Depth=1
	incl	%r13d
	cmpl	%edi, %r13d
	jl	.LBB9_4
.LBB9_9:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB9_10:                               # %.loopexit
	retq
.Lfunc_end9:
	.size	_ZN10CudaObject6subCpuERS_S0_, .Lfunc_end9-_ZN10CudaObject6subCpuERS_S0_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN10CudaObject6mulCpuERS_S0_,"axG",@progbits,_ZN10CudaObject6mulCpuERS_S0_,comdat
	.weak	_ZN10CudaObject6mulCpuERS_S0_   # -- Begin function _ZN10CudaObject6mulCpuERS_S0_
	.p2align	1, 0x90
	.type	_ZN10CudaObject6mulCpuERS_S0_,@function
_ZN10CudaObject6mulCpuERS_S0_:          # @_ZN10CudaObject6mulCpuERS_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -16(%rsp)                 # 8-byte Spill
	movq	%rsi, -24(%rsp)                 # 8-byte Spill
	movl	(%rdi), %ebp
	testl	%ebp, %ebp
	jle	.LBB10_8
# %bb.1:                                # %.preheader26.lr.ph
	movq	-24(%rsp), %rax                 # 8-byte Reload
	movl	4(%rax), %eax
	movq	-16(%rsp), %rcx                 # 8-byte Reload
	movslq	4(%rcx), %rsi
	movq	8(%rdi), %rcx
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	movslq	%eax, %r9
	movl	4(%rdi), %r8d
	shlq	$2, %r9
	leaq	(,%rsi,4), %r10
	xorl	%r11d, %r11d
	xorl	%ebx, %ebx
.LBB10_2:                               # %.preheader26
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB10_4 Depth 2
                                        #       Child Loop BB10_10 Depth 3
	testl	%r8d, %r8d
	jle	.LBB10_7
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB10_2 Depth=1
	movq	-16(%rsp), %rcx                 # 8-byte Reload
	movq	8(%rcx), %rcx
	movq	%rbx, %r8
	imulq	%rsi, %r8
	movq	-8(%rsp), %rdx                  # 8-byte Reload
	leaq	(%rdx,%r8,4), %r15
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	movq	8(%rdx), %r12
	addq	%r11, %r12
	xorl	%r13d, %r13d
.LBB10_4:                               # %.preheader
                                        #   Parent Loop BB10_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB10_10 Depth 3
	testl	%eax, %eax
	jle	.LBB10_5
# %bb.9:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB10_4 Depth=2
	xorl	%ebp, %ebp
	movq	%rcx, %r14
	xorl	%r8d, %r8d
.LBB10_10:                              # %.lr.ph
                                        #   Parent Loop BB10_2 Depth=1
                                        #     Parent Loop BB10_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movl	(%r14), %edx
	imull	(%r12,%rbp,4), %edx
	addl	%edx, %r8d
	incq	%rbp
	addq	%r10, %r14
	cmpq	%rbp, %rax
	jne	.LBB10_10
	jmp	.LBB10_11
.LBB10_5:                               #   in Loop: Header=BB10_4 Depth=2
	xorl	%r8d, %r8d
.LBB10_11:                              # %._crit_edge
                                        #   in Loop: Header=BB10_4 Depth=2
	movl	%r8d, (%r15,%r13,4)
	incq	%r13
	movslq	4(%rdi), %r8
	addq	$4, %rcx
	cmpq	%r8, %r13
	jl	.LBB10_4
# %bb.6:                                # %._crit_edge30.loopexit
                                        #   in Loop: Header=BB10_2 Depth=1
	movl	(%rdi), %ebp
.LBB10_7:                               # %._crit_edge30
                                        #   in Loop: Header=BB10_2 Depth=1
	incq	%rbx
	movslq	%ebp, %rcx
	addq	%r9, %r11
	cmpq	%rcx, %rbx
	jl	.LBB10_2
.LBB10_8:                               # %._crit_edge32
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_ZN10CudaObject6mulCpuERS_S0_, .Lfunc_end10-_ZN10CudaObject6mulCpuERS_S0_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZN10CudaObject7tranCpuERS_,"axG",@progbits,_ZN10CudaObject7tranCpuERS_,comdat
	.weak	_ZN10CudaObject7tranCpuERS_     # -- Begin function _ZN10CudaObject7tranCpuERS_
	.p2align	1, 0x90
	.type	_ZN10CudaObject7tranCpuERS_,@function
_ZN10CudaObject7tranCpuERS_:            # @_ZN10CudaObject7tranCpuERS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movq	%rdi, %rbx
	movl	(%rsi), %ebp
	movl	4(%rsi), %r15d
	movl	%r15d, (%rdi)
	movl	%ebp, 4(%rdi)
	movl	%r15d, %r12d
	imull	%ebp, %r12d
	leal	(,%r12,4), %eax
	movl	%eax, 20(%rdi)
	addq	$8, %rbx
	movslq	%eax, %rsi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%r12d, %r12d
	jle	.LBB11_3
# %bb.1:                                # %.lr.ph
	movq	8(%r14), %rsi
	movq	(%rbx), %rdi
	movl	%r12d, %r8d
	xorl	%ecx, %ecx
.LBB11_2:                               # =>This Inner Loop Header: Depth=1
	movl	%ecx, %eax
	cltd
	idivl	%ebp
	imull	%r15d, %edx
	addl	%eax, %edx
	movslq	%edx, %rax
	movl	(%rsi,%rax,4), %eax
	movl	%eax, (%rdi,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %r8
	jne	.LBB11_2
.LBB11_3:                               # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_ZN10CudaObject7tranCpuERS_, .Lfunc_end11-_ZN10CudaObject7tranCpuERS_
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB12_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB12_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3subPiS_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3mul10CudaObjectS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4tran10CudaObjectS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end12:
	.size	__hip_module_ctor, .Lfunc_end12-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB13_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB13_2:
	retq
.Lfunc_end13:
	.size	__hip_module_dtor, .Lfunc_end13-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addPiS_S_ii,@object          # @_Z3addPiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z3addPiS_S_ii
	.p2align	3, 0x0
_Z3addPiS_S_ii:
	.quad	_Z18__device_stub__addPiS_S_ii
	.size	_Z3addPiS_S_ii, 8

	.type	_Z3subPiS_S_ii,@object          # @_Z3subPiS_S_ii
	.globl	_Z3subPiS_S_ii
	.p2align	3, 0x0
_Z3subPiS_S_ii:
	.quad	_Z18__device_stub__subPiS_S_ii
	.size	_Z3subPiS_S_ii, 8

	.type	_Z3mul10CudaObjectS_S_,@object  # @_Z3mul10CudaObjectS_S_
	.globl	_Z3mul10CudaObjectS_S_
	.p2align	3, 0x0
_Z3mul10CudaObjectS_S_:
	.quad	_Z18__device_stub__mul10CudaObjectS_S_
	.size	_Z3mul10CudaObjectS_S_, 8

	.type	_Z4tran10CudaObjectS_,@object   # @_Z4tran10CudaObjectS_
	.globl	_Z4tran10CudaObjectS_
	.p2align	3, 0x0
_Z4tran10CudaObjectS_:
	.quad	_Z19__device_stub__tran10CudaObjectS_
	.size	_Z4tran10CudaObjectS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Choose an operation:"
	.size	.L.str, 21

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"1. Matrix addition on CPU"
	.size	.L.str.1, 26

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"2. Matrix addition on GPU"
	.size	.L.str.2, 26

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"3. Matrix substraction on CPU"
	.size	.L.str.3, 30

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"4. Matrix substraction on GPU"
	.size	.L.str.4, 30

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"5. Matrix multiplication on CPU"
	.size	.L.str.5, 32

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"6. Matrix multiplication on GPU"
	.size	.L.str.6, 32

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"7. Matrix transposition on CPU"
	.size	.L.str.7, 31

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"8. Matrix transposition on GPU"
	.size	.L.str.8, 31

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Enter the values of size_x, size_y of the first matrix and value to filled matrix:"
	.size	.L.str.9, 83

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Enter the values of size_x, size_y of the second matrix and value to filled matrix:"
	.size	.L.str.10, 84

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Matrices sizes have to be equal!"
	.size	.L.str.11, 33

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Size_x of the first matrix and size_y of the second matrix have to be equal!"
	.size	.L.str.12, 77

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Transposition of the first matrix: "
	.size	.L.str.13, 36

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Transposition of the second matrix: "
	.size	.L.str.14, 37

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"Wrong number entered!"
	.size	.L.str.15, 22

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"| "
	.size	.L.str.17, 3

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	" "
	.size	.L.str.18, 2

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"|"
	.size	.L.str.19, 2

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"\n"
	.size	.L.str.20, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3addPiS_S_ii"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3subPiS_S_ii"
	.size	.L__unnamed_2, 15

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z3mul10CudaObjectS_S_"
	.size	.L__unnamed_3, 23

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z4tran10CudaObjectS_"
	.size	.L__unnamed_4, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addPiS_S_ii
	.addrsig_sym _Z18__device_stub__subPiS_S_ii
	.addrsig_sym _Z18__device_stub__mul10CudaObjectS_S_
	.addrsig_sym _Z19__device_stub__tran10CudaObjectS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addPiS_S_ii
	.addrsig_sym _Z3subPiS_S_ii
	.addrsig_sym _Z3mul10CudaObjectS_S_
	.addrsig_sym _Z4tran10CudaObjectS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addPiS_S_ii          ; -- Begin function _Z3addPiS_S_ii
	.globl	_Z3addPiS_S_ii
	.p2align	8
	.type	_Z3addPiS_S_ii,@function
_Z3addPiS_S_ii:                         ; @_Z3addPiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s6, 0xffff
	s_mul_i32 s12, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[8:9], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_nc_u32_e32 v1, s8, v1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s10
	v_cmp_le_i32_e64 s0, s12, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v6, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow32
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addPiS_S_ii, .Lfunc_end0-_Z3addPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 264
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z3subPiS_S_ii          ; -- Begin function _Z3subPiS_S_ii
	.globl	_Z3subPiS_S_ii
	.p2align	8
	.type	_Z3subPiS_S_ii,@function
_Z3subPiS_S_ii:                         ; @_Z3subPiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x2c
	s_load_b64 s[4:5], s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s6, 0xffff
	s_mul_i32 s12, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[8:9], 2
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_nc_u32_e32 v1, s8, v1
	global_load_b32 v0, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s10
	v_cmp_le_i32_e64 s0, s12, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v0, v0, v6
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow32
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3subPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3subPiS_S_ii, .Lfunc_end1-_Z3subPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 264
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z3mul10CudaObjectS_S_  ; -- Begin function _Z3mul10CudaObjectS_S_
	.globl	_Z3mul10CudaObjectS_S_
	.p2align	8
	.type	_Z3mul10CudaObjectS_S_,@function
_Z3mul10CudaObjectS_S_:                 ; @_Z3mul10CudaObjectS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s13, s[0:1], 0x4
	s_load_b128 s[4:7], s[0:1], 0x30
	s_load_b32 s12, s[0:1], 0x54
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s13, 1
	s_cbranch_scc1 .LBB2_13
; %bb.1:                                ; %.lr.ph
	s_clause 0x4
	s_load_b32 s17, s[0:1], 0x10
	s_load_b32 s16, s[0:1], 0x28
	s_load_b32 s2, s[0:1], 0x0
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[18:19], s[0:1], 0x8
	v_lshlrev_b32_e32 v2, 2, v0
	v_lshlrev_b32_e32 v3, 7, v1
	s_add_i32 s20, s13, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v4, 0x1000, v2
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[6:7], null, s17, v1, v[0:1]
	v_mad_u64_u32 v[8:9], null, s16, v1, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	v_cmp_gt_i32_e64 s2, s9, v0
	s_lshr_b32 s9, s20, 5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_add_nc_u32_e32 v6, v4, v3
	v_lshlrev_b64 v[12:13], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s3, s18, v10
	v_add_co_ci_u32_e64 v8, s3, s19, v11, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v9, s3, s10, v12
	v_add_co_ci_u32_e64 v10, s3, s11, v13, s3
	s_mul_i32 s10, s17, s15
	s_mov_b32 s11, 0
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_11 Depth 2
	v_mov_b32_e32 v11, 0
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_lshl_add_u32 v11, s11, 5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s13, v11
	v_mov_b32_e32 v11, 0
	s_and_saveexec_b32 s18, s3
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s3, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s20, s3, 5
	s_ashr_i32 s21, s20, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[20:21], s[20:21], 2
	v_add_co_u32 v11, s3, v7, s20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v12, s3, s21, v8, s3
	global_load_b32 v11, v[11:12], off
.LBB2_5:                                ; %Flow97
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v12, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v11
	s_and_saveexec_b32 s17, s2
	s_cbranch_execz .LBB2_10
; %bb.7:                                ;   in Loop: Header=BB2_2 Depth=1
	v_lshl_add_u32 v11, s11, 5, v1
	v_mov_b32_e32 v12, 0
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s8, v11
	s_cbranch_execz .LBB2_9
; %bb.8:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mul_i32 s3, s11, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_lshl_b32 s20, s3, 5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s21, s20, 31
	s_lshl_b64 s[20:21], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s3, v9, s20
	v_add_co_ci_u32_e64 v12, s3, s21, v10, s3
	global_load_b32 v12, v[11:12], off
.LBB2_9:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB2_10:                               ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
	v_mov_b32_e32 v11, v4
	s_mov_b32 s3, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_11:                               ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v12, s3, v3
	s_add_i32 s3, s3, 4
	ds_load_b32 v14, v11
	ds_load_b32 v15, v12
	s_cmpk_eq_i32 s3, 0x80
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[12:13], null, v14, v15, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v12 :: v_dual_add_nc_u32 v11, 0x80, v11
	s_cbranch_scc0 .LBB2_11
; %bb.12:                               ;   in Loop: Header=BB2_2 Depth=1
	s_add_i32 s11, s11, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, s9
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_2
	s_branch .LBB2_14
.LBB2_13:
	v_mov_b32_e32 v2, 0
.LBB2_14:                               ; %Flow99
	s_load_b32 s1, s[0:1], 0x40
	s_lshr_b32 s0, s12, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s0, v[1:2]
	s_and_b32 s0, s12, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, s0, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, s5, v4
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB2_16
; %bb.15:
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s1, v[4:5]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3mul10CudaObjectS_S_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z3mul10CudaObjectS_S_, .Lfunc_end2-_Z3mul10CudaObjectS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 760
; NumSgprs: 24
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z4tran10CudaObjectS_   ; -- Begin function _Z4tran10CudaObjectS_
	.globl	_Z4tran10CudaObjectS_
	.p2align	8
	.type	_Z4tran10CudaObjectS_,@function
_Z4tran10CudaObjectS_:                  ; @_Z4tran10CudaObjectS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x3c
	s_load_b64 s[2:3], s[0:1], 0x0
	s_add_u32 s4, s0, 48
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s6, 0xffff
	s_mul_i32 s8, s3, s2
	v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
	s_mov_b32 s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v1
	s_cbranch_execz .LBB3_3
; %bb.1:                                ; %.lr.ph.preheader
	s_ashr_i32 s9, s2, 31
	s_load_b32 s12, s[4:5], 0x0
	s_add_i32 s6, s2, s9
	s_sub_i32 s2, 0, s2
	s_xor_b32 s10, s6, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s4, 0, s10
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s4, v0
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b64 s[6:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s12, s11
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
.LBB3_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v1, v2
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v0
	v_mul_lo_u32 v5, v4, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v5
	v_add_nc_u32_e32 v5, 1, v4
	v_subrev_nc_u32_e32 v6, s10, v3
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_xor_b32_e32 v6, s9, v2
	v_add_nc_u32_e32 v5, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_cndmask_b32_e32 v3, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s2, v3, v[1:2]
	v_mad_u64_u32 v[5:6], null, v4, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v4, v[3:4], off
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_i32_e32 vcc_lo, s8, v1
	v_add_co_u32 v2, s0, s6, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	s_or_b32 s11, vcc_lo, s11
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v4, off
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB3_2
.LBB3_3:                                ; %Flow23
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4tran10CudaObjectS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z4tran10CudaObjectS_, .Lfunc_end3-_Z4tran10CudaObjectS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 424
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
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amdhsa.version:
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...

	.end_amdgpu_metadata
