#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
	int i = max(i0,0) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
	int j = max(j0,0) + 4*(int)(threadIdx.y);

	double (*in)[8200] = (double (*)[8200]) l_in;
	double (*out)[8200] = (double (*)[8200]) l_out;

	if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];

_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;

_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;

outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;

out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
	} 
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	cudaMalloc (&in, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for in\n");
	cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
	double *out;
	cudaMalloc (&out, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 8);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));

	j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);

	cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
	cudaFree (in); 
	cudaFree (out);
}

	.file	"tmpxft_0038f43e_00000000-6_reordered-b.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
	.type	_Z29__device_stub__Z7j2d81ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d81ptPdS_iPdS_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7j2d81ptPdS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z29__device_stub__Z7j2d81ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
	.globl	_Z7j2d81ptPdS_i
	.type	_Z7j2d81ptPdS_i, @function
_Z7j2d81ptPdS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
	.cfi_endproc
.LFE2054:
	.size	_Z7j2d81ptPdS_i, .-_Z7j2d81ptPdS_i
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for in\n"
.LC2:
	.string	"Failed to allocate device memory for out\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%edx, %rbx
	movq	%rbx, %rbp
	imulq	%rbx, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	salq	$3, %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movl	%ebp, %eax
	movl	%ebp, %edx
	movl	$1, 24(%rsp)
	shrl	$5, %eax
	shrl	$4, %edx
	testl	$31, %ebp
	je	.L14
	movl	%ebp, %ecx
	incl	%eax
	andl	$15, %ecx
	cmpl	$1, %ecx
	sbbl	$-1, %edx
.L14:
	movl	%edx, 28(%rsp)
	movl	24(%rsp), %ecx
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	movl	%eax, 32(%rsp)
	movq	28(%rsp), %rdi
	xorl	%r8d, %r8d
	salq	$4, %rdx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%ebp, %edx
	call	_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.L15:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC3:
	.string	"_Z7j2d81ptPdS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7j2d81ptPdS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
	//Determing the block's indices
	int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
	int i = max(i0,0) + (int)(threadIdx.x);
	int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
	int j = max(j0,0) + 4*(int)(threadIdx.y);

	double (*in)[8200] = (double (*)[8200]) l_in;
	double (*out)[8200] = (double (*)[8200]) l_out;

	if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];

_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;

_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;

outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;

out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
	} 
}

extern "C" void host_code (double *h_in, double *h_out, int N) {
	double *in;
	hipMalloc (&in, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for in\n");
	hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
	double *out;
	hipMalloc (&out, sizeof(double)*N*N);
	check_error ("Failed to allocate device memory for out\n");

	dim3 blockconfig (16, 8);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));

	j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);

	hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
	hipFree (in); 
	hipFree (out);
}

	.text
	.file	"reordered-b.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__j2d81ptPdS_i # -- Begin function _Z22__device_stub__j2d81ptPdS_i
	.type	_Z22__device_stub__j2d81ptPdS_i,@function
_Z22__device_stub__j2d81ptPdS_i:        # @_Z22__device_stub__j2d81ptPdS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7j2d81ptPdS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__j2d81ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d81ptPdS_i
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movslq	%edx, %r15
	movq	%r15, %r14
	imulq	%r15, %r14
	shlq	$3, %r14
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movl	%r15d, %eax
	andl	$15, %eax
	movl	%r15d, %ecx
	shrl	$4, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%r15d, %eax
	andl	$31, %eax
	shrl	$5, %r15d
	cmpl	$1, %eax
	sbbl	$-1, %r15d
	shlq	$32, %r15
	orq	%rcx, %r15
	movabsq	$34359738384, %rdx              # imm = 0x800000010
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%ebp, %edx
	callq	_Z22__device_stub__j2d81ptPdS_i
.LBB2_2:
	movq	8(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7j2d81ptPdS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z7j2d81ptPdS_i,@object         # @_Z7j2d81ptPdS_i
	.section	.rodata,"a",@progbits
	.globl	_Z7j2d81ptPdS_i
	.p2align	3, 0x0
_Z7j2d81ptPdS_i:
	.quad	_Z22__device_stub__j2d81ptPdS_i
	.size	_Z7j2d81ptPdS_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for in\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for out\n"
	.size	.L.str.2, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7j2d81ptPdS_i"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__j2d81ptPdS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7j2d81ptPdS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7j2d81ptPdS_i         ; -- Begin function _Z7j2d81ptPdS_i
	.globl	_Z7j2d81ptPdS_i
	.p2align	8
	.type	_Z7j2d81ptPdS_i,@function
_Z7j2d81ptPdS_i:                        ; @_Z7j2d81ptPdS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_lshrrev_b32_e32 v0, 8, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v0, 0xffc, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s4
	s_mul_i32 s15, s15, s2
	s_max_i32 s4, s14, 0
	s_lshl_b32 s2, s15, 2
	v_add_nc_u32_e32 v48, s4, v1
	s_max_i32 s2, s2, 0
	s_add_i32 s3, s3, -9
	v_add_nc_u32_e32 v124, s2, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, v48, v124
	v_cmpx_ge_i32_e64 s3, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v49, 0 :: v_dual_add_nc_u32 v0, 8, v48
	s_mov_b32 s4, 0x18a43bb4
	s_mov_b32 s5, 0xbf74d120
	s_mov_b32 s14, 0xe94ee393
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[40:41], 3, v[48:49]
	v_mov_b32_e32 v1, v49
	s_mov_b32 s15, 0x40097d60
	v_or_b32_e32 v125, 1, v124
	v_mov_b32_e32 v43, v49
	s_mov_b32 s16, 0x8ce352cb
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_mov_b32 s17, 0x3f4523fe
	v_or_b32_e32 v126, 2, v124
	v_mov_b32_e32 v61, v49
	s_mov_b32 s12, 0xce61f843
	s_mov_b32 s13, 0xbfb2837d
	s_mov_b32 s6, 0x47ae147b
	s_mov_b32 s7, 0x3fa47ae1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[50:51], null, 0x10040, v124, s[0:1]
	v_mad_u64_u32 v[82:83], null, 0x10040, v125, s[0:1]
	v_mad_u64_u32 v[72:73], null, 0x10040, v126, s[0:1]
	s_mov_b32 s8, 0x3c21187e
	s_mov_b32 s9, 0x3fe238da
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v44, vcc_lo, v50, v40
	v_add_co_ci_u32_e32 v45, vcc_lo, v51, v41, vcc_lo
	v_or_b32_e32 v127, 3, v124
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, 0x80200, v44
	s_clause 0x4
	global_load_b128 v[28:31], v[44:45], off offset:48
	global_load_b128 v[16:19], v[44:45], off offset:32
	global_load_b128 v[20:23], v[44:45], off offset:16
	global_load_b128 v[36:39], v[44:45], off
	global_load_b64 v[2:3], v[44:45], off offset:64
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v6, vcc_lo, 0x80000, v44
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v32, vcc_lo, 0x40100, v50
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v51, vcc_lo
	s_mov_b32 s11, 0xc01238da
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v32, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v33, v1, vcc_lo
	v_add_co_u32 v32, vcc_lo, v32, v40
	v_add_co_ci_u32_e32 v33, vcc_lo, v33, v41, vcc_lo
	s_mov_b32 s10, s8
	s_mov_b32 s18, 0xae7d566d
	s_mov_b32 s19, 0x401222b6
	s_mov_b32 s20, 0x531db446
	s_mov_b32 s21, 0xbf376577
	s_mov_b32 s23, 0x3f676577
	s_mov_b32 s22, s20
	s_mov_b32 s24, 0x1dd1a21f
	s_mov_b32 s25, 0xbf74cec4
	s_mov_b32 s27, 0x3fa4cec4
	s_mov_b32 s26, s24
	s_mov_b32 s29, 0xbfd47ae1
	s_mov_b32 s28, s6
	s_mov_b32 s30, 0xb8bac711
	s_mov_b32 s31, 0x4020368d
	v_add_nc_u32_e32 v42, 7, v48
	v_add_nc_u32_e32 v60, 6, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[42:43], 3, v[42:43]
	v_lshlrev_b64 v[60:61], 3, v[60:61]
	s_waitcnt vmcnt(2)
	v_add_f64 v[20:21], v[20:21], v[28:29]
	s_waitcnt vmcnt(1)
	v_add_f64 v[30:31], v[38:39], v[30:31]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[36:37], v[2:3]
	s_clause 0x5
	global_load_b128 v[34:37], v[6:7], off offset:512
	global_load_b128 v[24:27], v[4:5], off offset:48
	global_load_b128 v[8:11], v[4:5], off offset:32
	global_load_b128 v[12:15], v[4:5], off offset:16
	global_load_b64 v[4:5], v[4:5], off offset:64
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(5)
	v_add_f64 v[2:3], v[2:3], v[34:35]
	s_waitcnt vmcnt(1)
	v_add_f64 v[66:67], v[34:35], v[4:5]
	global_load_b64 v[34:35], v[32:33], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[16:17], v[0:1]
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_dual_mov_b32 v5, v49 :: v_dual_add_nc_u32 v4, 4, v48
	v_add_f64 v[16:17], v[66:67], v[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], v[34:35]
	v_add_f64 v[70:71], v[0:1], v[34:35]
	v_add_f64 v[34:35], v[16:17], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[6:7], v[8:9]
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[2:3], s[14:15], v[0:1]
	v_dual_mov_b32 v3, v49 :: v_dual_add_nc_u32 v2, 1, v48
	v_lshlrev_b64 v[52:53], 3, v[4:5]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v82, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, v83, v3, vcc_lo
	v_add_co_u32 v46, vcc_lo, v82, v42
	v_add_co_ci_u32_e32 v47, vcc_lo, v83, v43, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	v_add_co_u32 v84, vcc_lo, 0x701c0, v50
	global_load_b64 v[46:47], v[46:47], off
	v_add_co_ci_u32_e32 v85, vcc_lo, 0, v51, vcc_lo
	v_add_co_u32 v2, vcc_lo, v84, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v85, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(2)
	v_add_f64 v[16:17], v[66:67], v[6:7]
	s_waitcnt vmcnt(1)
	v_add_f64 v[6:7], v[6:7], v[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[68:69], v[16:17], v[46:47]
	v_add_co_u32 v16, vcc_lo, v84, v42
	v_add_co_ci_u32_e32 v17, vcc_lo, v85, v43, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[6:7], v[2:3]
	global_load_b64 v[16:17], v[16:17], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[6:7], v[16:17]
	v_add_f64 v[58:59], v[2:3], v[16:17]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[42:43], v[6:7], s[16:17], v[0:1]
	v_add_co_u32 v0, vcc_lo, v82, v52
	v_add_co_ci_u32_e32 v1, vcc_lo, v83, v53, vcc_lo
	s_clause 0x4
	global_load_b64 v[16:17], v[0:1], off
	global_load_b64 v[46:47], v[32:33], off offset:56
	global_load_b128 v[62:65], v[32:33], off offset:40
	global_load_b128 v[4:7], v[32:33], off offset:24
	global_load_b128 v[0:3], v[32:33], off offset:8
	s_waitcnt vmcnt(0)
	v_add_f64 v[32:33], v[16:17], v[0:1]
	v_add_f64 v[94:95], v[2:3], v[64:65]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[32:33], v[32:33], v[46:47]
	v_add_f64 v[46:47], v[0:1], v[46:47]
	v_add_co_u32 v0, vcc_lo, v84, v52
	v_add_co_ci_u32_e32 v1, vcc_lo, v85, v53, vcc_lo
	global_load_b64 v[54:55], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[32:33], v[54:55]
	v_dual_mov_b32 v33, v49 :: v_dual_add_nc_u32 v32, 2, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[32:33], 3, v[32:33]
	v_fma_f64 v[0:1], v[0:1], s[12:13], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, v72, v32
	v_add_co_ci_u32_e32 v43, vcc_lo, v73, v33, vcc_lo
	v_add_co_u32 v74, vcc_lo, v72, v60
	v_add_co_ci_u32_e32 v75, vcc_lo, v73, v61, vcc_lo
	global_load_b64 v[42:43], v[42:43], off
	v_add_co_u32 v110, vcc_lo, 0x60180, v50
	global_load_b64 v[74:75], v[74:75], off
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v51, vcc_lo
	v_add_co_u32 v32, vcc_lo, v110, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, v111, v33, vcc_lo
	v_add_co_u32 v60, vcc_lo, v110, v60
	v_add_co_ci_u32_e32 v61, vcc_lo, v111, v61, vcc_lo
	s_clause 0x1
	global_load_b64 v[60:61], v[60:61], off
	global_load_b64 v[32:33], v[32:33], off
	s_waitcnt vmcnt(3)
	v_add_f64 v[56:57], v[58:59], v[42:43]
	v_add_f64 v[34:35], v[34:35], v[42:43]
	s_waitcnt vmcnt(2)
	v_add_f64 v[78:79], v[42:43], v[74:75]
	s_waitcnt vmcnt(0)
	v_add_f64 v[86:87], v[32:33], v[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[76:77], v[56:57], v[74:75]
	v_add_f64 v[42:43], v[34:35], v[74:75]
	v_add_f64 v[56:57], v[8:9], v[32:33]
	v_add_f64 v[34:35], v[78:79], v[32:33]
	v_add_co_u32 v32, vcc_lo, v72, v52
	v_add_co_ci_u32_e32 v33, vcc_lo, v73, v53, vcc_lo
	v_mad_u64_u32 v[74:75], null, 0x10040, v127, s[0:1]
	s_mov_b32 s1, 0x40047ae1
	global_load_b64 v[78:79], v[32:33], off
	s_mov_b32 s0, s6
	v_add_f64 v[76:77], v[76:77], v[12:13]
	v_add_f64 v[34:35], v[34:35], v[60:61]
	v_add_f64 v[60:61], v[56:57], v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[150:151], v[76:77], v[24:25]
	v_fma_f64 v[0:1], v[34:35], s[6:7], v[0:1]
	v_add_f64 v[34:35], v[86:87], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[80:81], v[34:35], v[64:65]
	s_waitcnt vmcnt(0)
	v_add_f64 v[32:33], v[78:79], v[2:3]
	v_add_co_u32 v2, vcc_lo, v110, v52
	v_add_co_ci_u32_e32 v3, vcc_lo, v111, v53, vcc_lo
	v_add_f64 v[88:89], v[8:9], v[78:79]
	global_load_b64 v[56:57], v[2:3], off
	v_add_f64 v[32:33], v[32:33], v[64:65]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[32:33], v[56:57]
	v_add_f64 v[92:93], v[8:9], v[56:57]
	v_fma_f64 v[64:65], v[2:3], s[8:9], v[0:1]
	v_dual_mov_b32 v1, v49 :: v_dual_add_nc_u32 v0, 3, v48
	v_add_nc_u32_e32 v48, 5, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v74, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v75, v9, vcc_lo
	s_clause 0x1
	global_load_b64 v[2:3], v[0:1], off offset:16
	global_load_b128 v[32:35], v[0:1], off
	v_add_co_u32 v100, vcc_lo, 0x50140, v50
	v_add_co_ci_u32_e32 v101, vcc_lo, 0, v51, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[80:81], v[32:33]
	v_add_f64 v[80:81], v[58:59], v[32:33]
	v_add_f64 v[66:67], v[66:67], v[32:33]
	v_add_f64 v[32:33], v[32:33], v[2:3]
	v_add_f64 v[58:59], v[58:59], v[6:7]
	v_add_f64 v[104:105], v[0:1], v[2:3]
	v_add_co_u32 v0, vcc_lo, v100, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, v101, v9, vcc_lo
	v_add_f64 v[98:99], v[80:81], v[2:3]
	v_add_f64 v[80:81], v[66:67], v[2:3]
	global_load_b64 v[66:67], v[0:1], off
	v_add_co_u32 v0, vcc_lo, v100, v52
	v_add_co_ci_u32_e32 v1, vcc_lo, v101, v53, vcc_lo
	v_add_co_u32 v82, vcc_lo, v82, v40
	v_add_co_ci_u32_e32 v83, vcc_lo, v83, v41, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	v_add_co_u32 v84, vcc_lo, v84, v40
	global_load_b64 v[38:39], v[82:83], off
	v_add_co_ci_u32_e32 v85, vcc_lo, v85, v41, vcc_lo
	global_load_b64 v[102:103], v[84:85], off offset:64
	s_waitcnt vmcnt(3)
	v_add_f64 v[32:33], v[32:33], v[66:67]
	v_add_f64 v[90:91], v[56:57], v[66:67]
	v_add_f64 v[86:87], v[86:87], v[66:67]
	s_waitcnt vmcnt(2)
	v_add_f64 v[106:107], v[66:67], v[2:3]
	v_add_f64 v[66:67], v[54:55], v[34:35]
	s_waitcnt vmcnt(1)
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_add_f64 v[96:97], v[32:33], v[2:3]
	v_add_f64 v[32:33], v[90:91], v[2:3]
	v_add_f64 v[2:3], v[86:87], v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[86:87], v[96:97], s[0:1], v[64:65]
	v_add_f64 v[64:65], v[34:35], v[4:5]
	v_add_f64 v[2:3], v[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[64:65], v[64:65], v[62:63]
	v_add_f64 v[62:63], v[4:5], v[62:63]
	v_add_f64 v[4:5], v[64:65], v[0:1]
	v_add_f64 v[64:65], v[54:55], v[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[4:5], v[4:5], s[10:11], v[86:87]
	global_load_b64 v[86:87], v[82:83], off offset:64
	s_waitcnt vmcnt(0)
	v_add_f64 v[30:31], v[30:31], v[86:87]
	v_add_f64 v[38:39], v[38:39], v[86:87]
	global_load_b64 v[86:87], v[84:85], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[30:31], v[30:31], v[86:87]
	v_add_f64 v[90:91], v[34:35], v[86:87]
	v_add_f64 v[96:97], v[86:87], v[102:103]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[108:109], v[30:31], v[102:103]
	v_add_f64 v[30:31], v[90:91], v[102:103]
	v_add_f64 v[102:103], v[46:47], v[36:37]
	v_add_f64 v[90:91], v[36:37], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[86:87], v[108:109], v[36:37]
	v_add_f64 v[108:109], v[62:63], v[36:37]
	v_add_f64 v[102:103], v[102:103], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[112:113], v[86:87], v[26:27]
	v_add_f64 v[86:87], v[108:109], v[26:27]
	v_add_co_u32 v108, vcc_lo, v72, v40
	v_add_co_ci_u32_e32 v109, vcc_lo, v73, v41, vcc_lo
	v_add_co_u32 v28, vcc_lo, v110, v40
	v_add_co_ci_u32_e32 v29, vcc_lo, v111, v41, vcc_lo
	s_clause 0x1
	global_load_b128 v[118:121], v[108:109], off
	global_load_b128 v[128:131], v[108:109], off offset:56
	v_add_f64 v[110:111], v[14:15], v[10:11]
	global_load_b128 v[134:137], v[28:29], off offset:56
	v_fma_f64 v[4:5], v[112:113], s[18:19], v[4:5]
	s_waitcnt vmcnt(2)
	v_add_f64 v[20:21], v[20:21], v[118:119]
	v_add_f64 v[26:27], v[68:69], v[118:119]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[130:131]
	v_add_f64 v[68:69], v[26:27], v[130:131]
	v_add_f64 v[26:27], v[118:119], v[130:131]
	global_load_b128 v[130:133], v[28:29], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[20:21], v[20:21], v[130:131]
	v_add_f64 v[36:37], v[70:71], v[130:131]
	v_add_f64 v[72:73], v[78:79], v[130:131]
	v_add_f64 v[78:79], v[80:81], v[130:131]
	v_add_f64 v[34:35], v[34:35], v[132:133]
	v_add_f64 v[86:87], v[86:87], v[132:133]
	v_add_f64 v[80:81], v[20:21], v[136:137]
	v_add_f64 v[148:149], v[36:37], v[136:137]
	v_add_f64 v[20:21], v[72:73], v[136:137]
	v_add_f64 v[72:73], v[78:79], v[136:137]
	v_add_f64 v[78:79], v[94:95], v[12:13]
	v_add_f64 v[36:37], v[80:81], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[78:79], v[24:25]
	v_add_f64 v[80:81], v[36:37], v[24:25]
	v_add_f64 v[36:37], v[2:3], v[24:25]
	v_add_f64 v[2:3], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[76:77], v[80:81], s[20:21], v[4:5]
	v_add_co_u32 v4, vcc_lo, v74, v40
	v_add_co_ci_u32_e32 v5, vcc_lo, v75, v41, vcc_lo
	s_clause 0x1
	global_load_b64 v[114:115], v[4:5], off offset:16
	global_load_b128 v[22:25], v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[18:19], v[2:3], v[22:23]
	s_clause 0x1
	global_load_b64 v[78:79], v[4:5], off offset:64
	global_load_b128 v[2:5], v[4:5], off offset:48
	v_add_f64 v[74:75], v[96:97], v[22:23]
	v_add_f64 v[70:71], v[70:71], v[24:25]
	s_waitcnt vmcnt(1)
	v_add_f64 v[80:81], v[22:23], v[78:79]
	v_add_co_u32 v22, vcc_lo, v100, v40
	v_add_co_ci_u32_e32 v23, vcc_lo, v101, v41, vcc_lo
	s_clause 0x1
	global_load_b64 v[112:113], v[22:23], off offset:16
	global_load_b128 v[136:139], v[22:23], off
	v_add_f64 v[18:19], v[18:19], v[78:79]
	v_add_f64 v[122:123], v[74:75], v[78:79]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[74:75], v[18:19], v[136:137]
	v_add_f64 v[78:79], v[16:17], v[136:137]
	s_clause 0x3
	global_load_b64 v[100:101], v[22:23], off offset:64
	global_load_b128 v[16:19], v[22:23], off offset:48
	global_load_b128 v[140:143], v[82:83], off offset:16
	global_load_b128 v[144:147], v[82:83], off offset:40
	v_add_f64 v[96:97], v[96:97], v[136:137]
	s_waitcnt vmcnt(3)
	v_add_f64 v[22:23], v[74:75], v[100:101]
	v_add_f64 v[74:75], v[78:79], v[100:101]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[118:119], v[96:97], v[100:101]
	v_add_f64 v[78:79], v[46:47], v[14:15]
	v_add_f64 v[96:97], v[62:63], v[14:15]
	v_add_f64 v[116:117], v[136:137], v[100:101]
	v_add_f64 v[22:23], v[22:23], v[14:15]
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[122:123], v[140:141]
	v_add_f64 v[78:79], v[78:79], v[10:11]
	v_add_f64 v[96:97], v[96:97], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], v[10:11]
	s_waitcnt vmcnt(0)
	v_add_f64 v[82:83], v[14:15], v[146:147]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[22:23], s[22:23], v[76:77]
	v_add_f64 v[22:23], v[140:141], v[146:147]
	v_add_f64 v[14:15], v[22:23], v[120:121]
	v_add_f64 v[22:23], v[90:91], v[120:121]
	v_add_f64 v[90:91], v[80:81], v[120:121]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], v[128:129]
	v_add_f64 v[76:77], v[22:23], v[128:129]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[100:101], v[90:91], v[128:129]
	v_add_f64 v[22:23], v[78:79], v[132:133]
	global_load_b128 v[128:131], v[84:85], off offset:16
	v_add_f64 v[78:79], v[34:35], v[134:135]
	v_add_f64 v[14:15], v[14:15], v[132:133]
	v_add_f64 v[122:123], v[22:23], v[134:135]
	v_add_f64 v[22:23], v[86:87], v[134:135]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], v[134:135]
	global_load_b128 v[132:135], v[84:85], off offset:40
	s_waitcnt vmcnt(1)
	v_add_f64 v[14:15], v[14:15], v[128:129]
	v_add_f64 v[34:35], v[96:97], v[128:129]
	v_add_f64 v[86:87], v[0:1], v[128:129]
	v_add_f64 v[96:97], v[24:25], v[4:5]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], v[134:135]
	v_add_f64 v[120:121], v[128:129], v[134:135]
	v_add_f64 v[84:85], v[86:87], v[134:135]
	v_add_f64 v[34:35], v[34:35], v[134:135]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[128:129], v[14:15], s[24:25], v[10:11]
	v_add_f64 v[10:11], v[148:149], v[142:143]
	v_add_f64 v[14:15], v[142:143], v[144:145]
	v_add_f64 v[34:35], v[34:35], v[112:113]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[90:91], v[10:11], v[144:145]
	v_add_f64 v[10:11], v[14:15], v[24:25]
	v_add_f64 v[14:15], v[150:151], v[24:25]
	v_add_f64 v[24:25], v[70:71], v[4:5]
	v_add_f64 v[70:71], v[94:95], v[138:139]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[4:5]
	v_add_f64 v[86:87], v[14:15], v[4:5]
	v_add_f64 v[14:15], v[98:99], v[138:139]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[98:99], v[70:71], v[18:19]
	v_add_f64 v[4:5], v[10:11], v[138:139]
	v_add_f64 v[10:11], v[88:89], v[138:139]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[94:95], v[14:15], v[18:19]
	v_add_f64 v[14:15], v[106:107], v[130:131]
	v_add_f64 v[4:5], v[4:5], v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_f64 v[88:89], v[10:11], v[18:19]
	v_add_f64 v[10:11], v[104:105], v[130:131]
	v_add_f64 v[18:19], v[92:93], v[130:131]
	v_add_f64 v[14:15], v[14:15], v[132:133]
	v_add_f64 v[4:5], v[4:5], v[130:131]
	v_add_f64 v[92:93], v[10:11], v[132:133]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[18:19], v[132:133]
	s_clause 0x1
	global_load_b64 v[18:19], v[108:109], off offset:24
	global_load_b64 v[108:109], v[108:109], off offset:40
	v_add_f64 v[4:5], v[4:5], v[132:133]
	v_fma_f64 v[4:5], v[4:5], s[26:27], v[128:129]
	s_waitcnt vmcnt(1)
	v_add_f64 v[70:71], v[122:123], v[18:19]
	v_add_f64 v[106:107], v[118:119], v[18:19]
	s_waitcnt vmcnt(0)
	v_add_f64 v[18:19], v[18:19], v[108:109]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[104:105], v[70:71], v[108:109]
	v_add_f64 v[70:71], v[106:107], v[108:109]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[114:115]
	v_add_f64 v[106:107], v[120:121], v[114:115]
	v_add_f64 v[108:109], v[102:103], v[114:115]
	v_add_f64 v[114:115], v[116:117], v[114:115]
	v_add_f64 v[18:19], v[18:19], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[102:103], v[106:107], v[2:3]
	v_add_f64 v[106:107], v[108:109], v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[114:115], v[114:115], v[2:3]
	v_add_f64 v[108:109], v[112:113], v[16:17]
	v_add_f64 v[2:3], v[18:19], v[112:113]
	v_add_f64 v[18:19], v[66:67], v[112:113]
	v_add_f64 v[2:3], v[2:3], v[16:17]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[66:67], v[18:19], v[16:17]
	v_add_f64 v[18:19], v[34:35], v[16:17]
	s_clause 0x1
	global_load_b64 v[16:17], v[28:29], off offset:24
	global_load_b64 v[28:29], v[28:29], off offset:40
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[2:3], v[16:17]
	v_add_f64 v[34:35], v[62:63], v[16:17]
	v_add_f64 v[64:65], v[64:65], v[16:17]
	v_add_f64 v[16:17], v[110:111], v[16:17]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[2:3], v[2:3], v[28:29]
	v_add_f64 v[62:63], v[34:35], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[64:65], v[28:29]
	v_add_f64 v[28:29], v[16:17], v[28:29]
	v_add_f64 v[64:65], v[32:33], v[6:7]
	v_add_f64 v[32:33], v[60:61], v[6:7]
	v_fma_f64 v[2:3], v[2:3], s[28:29], v[4:5]
	v_lshlrev_b64 v[4:5], 3, v[48:49]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[16:17], v[6:7], s[30:31], v[2:3]
	v_add_co_u32 v6, vcc_lo, 0x90240, v44
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v2, vcc_lo, 0x90000, v44
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v50, vcc_lo, 0xb02c0, v50
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v51, vcc_lo
	s_clause 0x3
	global_load_b128 v[110:113], v[2:3], off offset:576
	global_load_b128 v[116:119], v[6:7], off offset:48
	global_load_b128 v[120:123], v[6:7], off offset:32
	global_load_b128 v[128:131], v[6:7], off offset:16
	v_add_co_u32 v2, vcc_lo, v50, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, v51, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, v50, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v51, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(5)
	v_add_f64 v[38:39], v[38:39], v[110:111]
	v_add_f64 v[60:61], v[100:101], v[110:111]
	s_waitcnt vmcnt(2)
	v_add_f64 v[36:37], v[36:37], v[130:131]
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[72:73], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[36:37], v[122:123]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_co_u32 v4, vcc_lo, v50, v52
	v_add_co_ci_u32_e32 v5, vcc_lo, v51, v53, vcc_lo
	v_add_co_u32 v48, vcc_lo, v50, v40
	v_add_co_ci_u32_e32 v49, vcc_lo, v51, v41, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	v_mul_f64 v[2:3], v[2:3], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[54:55], s[30:31], v[2:3]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[30:31], v[4:5]
	v_fma_f64 v[8:9], v[4:5], s[4:5], v[2:3]
	global_load_b64 v[2:3], v[48:49], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[30:31], v[80:81], v[2:3]
	s_clause 0x2
	global_load_b64 v[50:51], v[48:49], off offset:64
	global_load_b128 v[2:5], v[48:49], off offset:48
	global_load_b64 v[6:7], v[6:7], off offset:64
	s_waitcnt vmcnt(2)
	v_add_f64 v[30:31], v[30:31], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[50:51], v[30:31], s[14:15], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[38:39], v[6:7]
	v_add_f64 v[30:31], v[60:61], v[6:7]
	v_mul_f64 v[8:9], v[8:9], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[30:31], v[8:9]
	v_add_f64 v[8:9], v[114:115], v[110:111]
	v_add_f64 v[38:39], v[8:9], v[6:7]
	global_load_b128 v[6:9], v[48:49], off offset:8
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[38:39], v[8:9]
	v_add_f64 v[38:39], v[98:99], v[112:113]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[8:9], v[2:3]
	v_fma_f64 v[8:9], v[2:3], s[20:21], v[50:51]
	v_add_f64 v[2:3], v[68:69], v[112:113]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[48:49], v[2:3], v[118:119]
	v_add_f64 v[2:3], v[38:39], v[118:119]
	v_add_f64 v[38:39], v[96:97], v[112:113]
	v_fma_f64 v[0:1], v[48:49], s[18:19], v[0:1]
	v_add_f64 v[48:49], v[82:83], v[128:129]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[38:39], v[118:119]
	v_add_f64 v[48:49], v[48:49], v[116:117]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[38:39], v[38:39], s[16:17]
	v_fma_f64 v[0:1], v[48:49], s[20:21], v[0:1]
	v_add_f64 v[48:49], v[106:107], v[128:129]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[56:57], s[30:31], v[38:39]
	v_add_f64 v[48:49], v[48:49], v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[48:49], s[24:25], v[38:39]
	v_add_f64 v[48:49], v[108:109], v[128:129]
	v_add_f64 v[48:49], v[48:49], v[116:117]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[48:49], s[6:7], v[8:9]
	v_add_f64 v[48:49], v[90:91], v[130:131]
	v_fma_f64 v[8:9], v[36:37], s[28:29], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[48:49], v[48:49], v[122:123]
	v_add_f64 v[36:37], v[78:79], v[120:121]
	v_fma_f64 v[0:1], v[48:49], s[22:23], v[0:1]
	v_add_f64 v[48:49], v[94:95], v[130:131]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[48:49], v[48:49], v[122:123]
	v_fma_f64 v[38:39], v[48:49], s[26:27], v[38:39]
	v_add_f64 v[48:49], v[74:75], v[120:121]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[36:37], s[12:13], v[38:39]
	v_fma_f64 v[0:1], v[48:49], s[4:5], v[0:1]
	v_add_f64 v[38:39], v[84:85], v[120:121]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[76:77], s[16:17], v[0:1]
	v_fma_f64 v[8:9], v[38:39], s[8:9], v[8:9]
	v_add_co_u32 v38, vcc_lo, 0xa0280, v44
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v45, vcc_lo
	v_add_co_u32 v44, vcc_lo, 0xa0000, v44
	v_add_co_ci_u32_e32 v45, vcc_lo, 0, v45, vcc_lo
	v_fma_f64 v[0:1], v[86:87], s[24:25], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[104:105], s[26:27], v[0:1]
	v_fma_f64 v[0:1], v[88:89], s[12:13], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[102:103], s[6:7], v[0:1]
	v_fma_f64 v[0:1], v[92:93], s[28:29], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[66:67], s[8:9], v[0:1]
	v_fma_f64 v[0:1], v[62:63], s[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[64:65], s[10:11], v[0:1]
	s_clause 0x4
	global_load_b128 v[48:51], v[44:45], off offset:640
	global_load_b128 v[52:55], v[38:39], off offset:48
	global_load_b128 v[60:63], v[38:39], off offset:32
	global_load_b128 v[64:67], v[38:39], off offset:16
	global_load_b64 v[38:39], v[38:39], off offset:64
	s_waitcnt vmcnt(4)
	v_add_f64 v[24:25], v[24:25], v[48:49]
	v_add_f64 v[26:27], v[26:27], v[48:49]
	s_waitcnt vmcnt(1)
	v_add_f64 v[2:3], v[2:3], v[64:65]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[38:39]
	v_add_f64 v[26:27], v[26:27], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], v[52:53]
	v_add_f64 v[6:7], v[24:25], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[26:27], s[14:15], v[36:37]
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_f64 v[6:7], v[30:31], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[4:5], s[18:19], v[8:9]
	v_add_f64 v[8:9], v[46:47], v[50:51]
	v_add_f64 v[6:7], v[6:7], v[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[54:55]
	v_fma_f64 v[6:7], v[6:7], s[18:19], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[8:9], s[16:17], v[4:5]
	v_add_f64 v[8:9], v[42:43], v[64:65]
	v_fma_f64 v[2:3], v[2:3], s[24:25], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[52:53]
	v_add_f64 v[4:5], v[70:71], v[66:67]
	v_fma_f64 v[6:7], v[8:9], s[20:21], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[62:63]
	v_add_f64 v[8:9], v[58:59], v[60:61]
	v_fma_f64 v[4:5], v[4:5], s[22:23], v[6:7]
	v_add_f64 v[6:7], v[22:23], v[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], v[62:63]
	v_fma_f64 v[2:3], v[6:7], s[26:27], v[2:3]
	v_add_f64 v[6:7], v[20:21], v[60:61]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[8:9], s[12:13], v[2:3]
	v_fma_f64 v[4:5], v[6:7], s[4:5], v[4:5]
	v_mad_u64_u32 v[6:7], null, 0x10040, v124, s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v40
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v41, vcc_lo
	global_store_b64 v[6:7], v[16:17], off
	v_mad_u64_u32 v[6:7], null, 0x10040, v125, s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v6, v40
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v41, vcc_lo
	global_store_b64 v[6:7], v[0:1], off
	v_mad_u64_u32 v[0:1], null, 0x10040, v126, s[2:3]
	v_fma_f64 v[2:3], v[28:29], s[0:1], v[2:3]
	v_fma_f64 v[4:5], v[12:13], s[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v0, v40
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[2:3], v[10:11], s[10:11], v[2:3]
	v_fma_f64 v[4:5], v[18:19], s[28:29], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[32:33], s[8:9], v[4:5]
	v_fma_f64 v[4:5], v[14:15], s[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[34:35], s[10:11], v[4:5]
	global_store_b64 v[0:1], v[4:5], off
	v_mad_u64_u32 v[0:1], null, 0x10040, v127, s[2:3]
	v_add_co_u32 v0, vcc_lo, v0, v40
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v41, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7j2d81ptPdS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 152
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7j2d81ptPdS_i, .Lfunc_end0-_Z7j2d81ptPdS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4896
; NumSgprs: 34
; NumVgprs: 152
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 18
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 152
; Occupancy: 9
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  read_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7j2d81ptPdS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z7j2d81ptPdS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     152
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
