# Stochastic thermodynamic bounds on logical circuit operation

Phillip Helms  Department of Chemistry, University of California, Berkeley,
California 94720, USA  Chemical Science Division, Lawrence Berkeley National
Laboratory, Berkeley, California 94720, USA  David T. Limmer
<EMAIL_ADDRESS>Department of Chemistry, University of California,
Berkeley, California 94720, USA  Chemical Science Division, Lawrence Berkeley
National Laboratory, Berkeley, California 94720, USA  Materials Science
Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720,
USA  Kavli Energy NanoScience Institute, Berkeley, California 94720, USA

###### Abstract

Using a thermodynamically consistent, mesoscopic model for modern
complementary metal-oxide-semiconductor transistors, we study an array of
logical circuits and explore how their function is constrained by recent
thermodynamic uncertainty relations when operating near thermal energies. For
a single NOT gate, we find operating direction-dependent dynamics, and an
optimal trade-off between dissipated heat and operation time certainty. For a
memory storage device, we find an exponential relationship between the memory
retention time and energy required to sustain that memory state. For a clock,
we find that the certainty in the cycle time is maximized at biasing voltages
near thermal energy, as is the trade-off between this certainty and the heat
dissipated per cycle. We demonstrate that a simple control mechanism for the
clock leads to a monotonic increase in cycle time certainty with biasing
voltage alleviating its degradation at large biasing voltages. These results
provide a framework for assessing thermodynamic costs of realistic computing
devices, allowing for circuits to be designed and controlled for
thermodynamically optimal operation.

While semiconductor-based computational capacity Moore (1965); Moore  _et al._
(1975) and efficiency Dennard  _et al._ (1974); Leiserson  _et al._ (2020);
Shalf (2020) has exhibited sustained exponential growth over the past century,
continued adherence of these trends is being disrupted as feature sizes
approach atomic length scales and energetic scales near those of thermal noise
Leiserson  _et al._ (2020); Shalf (2020). At such small scales, computation
has to reconcile with unavoidable noiseJohnson (1928); Nyquist (1928). This
noisy limit has been termed thermodynamic computing Conte  _et al._ (2019);
Hylton  _et al._ (2021) and requires the development of new principles to
achieve robust and energy-efficient information processing Marković  _et al._
(2020); Kaiser and Datta (2021); Camsari  _et al._ (2019); Wolpert and
Kolchinsky (2020). In this letter, we explore fundamental limitations
encountered when computing in this regime by showing how the function of
realistic logical circuits is bounded by recent thermodynamic uncertainty
relationsBarato and Seifert (2015); Gingrich  _et al._ (2016).

Building upon equilibrium thermodynamics-based limits on computing operations,
such as Landauer’s limit on the cost of bit erasure Landauer (1961),
stochastic thermodynamicsSeifert (2012) provides a framework for exploring the
inherent limits of logical circuit operations on small scales, far from
equilibrium. Recent results like fluctuation theorems, thermodynamic
uncertainty relationships, and speed limits Shiraishi  _et al._ (2018); Ito
(2018); Macieszczak  _et al._ (2018); Falasco and Esposito (2020); Ito and
Dechant (2020); Kuznets-Speck and Limmer (2021); Neri (2022); Horowitz and
Gingrich (2017); Gingrich  _et al._ (2017); Wolpert (2019) can be used to
strengthen bounds on computation within the thermodynamic computing regime,
provided a physically-consistent, stochastic model. Using a recently developed
model for current complementary metal-oxide-semiconductor (CMOS)
transistors,Gao and Limmer (2021) we study the interplay between accuracy,
speed, and heat dissipation of an array of computations performed near thermal
energies, locating optimal trade-offs between thermodynamic and operational
costs.

_Model –_ Many conventional engineering approaches for characterizing the
effects of noise on circuit operation rely on assumptions only valid near
equilibrium or near specific operating conditions Van Der Ziel (1970); Heinen
_et al._ (1991); Rizzoli and Neri (1988); Weiss and Mathis (1998),
guaranteeing neither thermodynamic consistency nor accuracy far from
equilibriumGao and Limmer (2019). To provide a more faithful description of
stochastic circuits, we require models that obey local detailed balance and
exhibit shot noise Scholten  _et al._ (2006), while accurately reproducing
known circuit characteristics. Recently, several stochastic models for CMOS
devices have been proposedGu and Gaspard (2020); Freitas  _et al._ (2021); Gao
and Limmer (2021), enabling the study of noisy circuits and the associated
thermodynamic costs when operating these devices near thermal energiesFreitas
_et al._ (2022); Kuang  _et al._ (2022); Gopal  _et al._ (2022). Here, we
employ one such modelGao and Limmer (2021) to study systems of inverters, or
logical NOT gates, built from single electron tunnel junctions operating
within the classical limit Datta (1997), and using a capacitive charging model
for the readout voltage. This model meets the three criteria emphasized above
and in principle can be parameterized directly from microscopic calculations,
providing a link between circuit performance and the underlying materials
properties.

As shown in Fig. 1 (a), each inverter contains an N-type and a P-type
transistor, each modeled by the band energy of an electron in the transistor
$\epsilon_{\mathrm{N}}\left(V_{\mathrm{in}}\right)$ and
$\epsilon_{\mathrm{P}}\left(V_{\mathrm{in}}\right)$, respectively, with energy
levels controlled by the inverter’s input voltage $V_{\mathrm{in}}$. This form
of $\epsilon_{i}$ is valid in the limit of high gate capacitance. We set
$\epsilon_{\mathrm{N}}=qV_{\mathrm{in}}$ and
$\epsilon_{\mathrm{P}}=\frac{3}{2}qV_{\mathrm{d}}-qV_{\mathrm{in}}$ to
reproduce the characteristic voltage transfer curve of an inverter where $q$
is the unit of chargeGao and Limmer (2021). The transistors are connected to
three electron reservoirs: a source connected to the N-type transistor with
reference voltage $V_{\mathrm{s}}=0$, a drain connected to the P-type
transistor with voltage $V_{\mathrm{d}}>0$ resulting in a cross-voltage, and
an output gate connected to both transistors. While the source and drain are
held fixed, the output gate voltage changes as electrons accumulate in the
gate according to $dV_{\mathrm{g}}/dt=-J_{\mathrm{g}}(t)/C_{\mathrm{g}}$,
where $J_{\mathrm{g}}$ is the current of electrons into the gate and
$C_{\mathrm{g}}$ is the gate capacitance 111We use
$C_{\mathrm{g}}=10q/V_{\mathrm{T}}$ throughout, though we have verified nearly
identical inverter performance at $C_{\mathrm{g}}=510q/V_{\mathrm{T}}$ and
$C_{\mathrm{g}}=1510q/V_{\mathrm{T}}$.

The system evolves stochastically according to a Markovian master equation
$\partial_{t}\mathbf{P}(t)=\mathbf{W}\mathbf{P}(t)$ where $\mathbf{P}$ is the
configurational probability vector and $\mathbf{W}$ is the stochastic
generator, with elements $W_{ij}$ specifying the rate at which an electron
transitions from state $j$ to $i$ and $P_{i}(t)$ being the probability of
being in state $i$ at time $t$. The ratio of forward and reverse rates satisfy
local detailed balance, $W_{ij}/W_{ji}=e^{-\beta(E_{i}-E_{j})}$, where $E_{i}$
is the energy of a given configuration and $\beta=1/k_{\mathrm{B}}T$ is the
inverse temperature defined with Boltzmann’s constant $k_{\mathrm{B}}$ and
temperature $T$. The rates are defined using the Fermi distribution where the
transition rate of an electron from an electrode $j$ to a transistor $i$ is
$W_{ij}=\Gamma\left(e^{\beta(\epsilon_{i}-qV_{j})}+1\right)^{-1}$ and the
reverse is
$W_{ji}=\Gamma-\Gamma\left(e^{\beta(\epsilon_{i}-qV_{j})}+1\right)^{-1}$ where
$\Gamma$ specifies the timescale for transitions and is physically set by the
resistance of the transistor-electrode interface.

We work in units of thermal voltages and times,
$V_{\mathrm{T}}=k_{\mathrm{B}}T/q$ and $\beta\hbar$ respectively, and set
$\Gamma^{-1}=5\beta\hbar$ so the timescale of electron transitions is longer
than the timescale of thermal fluctuations Datta (1997), with $\hbar$ being
Planck’s constant. For reference, at room temperature $V_{\mathrm{T}}\approx
26\ \mathrm{meV}$ and $\beta\hbar\approx 25\ \mathrm{fs}$. In these units, the
model inverter is determined by a specification of the input voltage
$V_{\mathrm{in}}$ and cross-voltage $V_{\mathrm{d}}$.

Figure 1:  Characterization of the NOT gate. (a) Illustration of the logical
symbol and corresponding Markov model. (b) The probability of
$V_{\mathrm{out}}$ with blue and green shading corresponding to different
cross-voltages. The left (right) panel illustrate the dynamics of charging
(discharging) the inverter, with input voltages switched at $t=0$. (c) Trade-
off between first passage time certainty and heat dissipation for discharging
and charging over a range of $V_{\mathrm{d}}$ with $\alpha=0.05$, with the
shaded region forbidden by the thermodynamic uncertainty relation. (d) The
same trade-off as in (c) for the charging process shown as a function of the
probability of a correct gate output in the steady-state with varying accuracy
thresholds $\alpha\in[0,0.05,0.1,0.2]$.

_Inverter –_ We start by considering the operation of a single NOT gate, which
takes an input binary signal $X$ and outputs its logical inverse $Y$ according
to the mapping:

$\displaystyle X=\begin{cases}0,&V_{\mathrm{in}}=0\\\
1,&V_{\mathrm{in}}=V_{\mathrm{d}}\\\ \end{cases},\ \
Y=\begin{cases}0,&V_{\mathrm{out}}\leq\alpha V_{\mathrm{d}}\\\
1,&V_{\mathrm{out}}\geq(1-\alpha)V_{\mathrm{d}}\\\
\emptyset,&\mathrm{otherwise}\\\ \end{cases}\ .$ (1)

In the deterministic limit, when the input is $X=1$, current through the
P-type transistor is inhibited, bringing the capacitor gate into effective
contact with only the source reservoir with $Y=0$. Conversely, when the input
voltage is $X=0$, current is inhibited in the other transistor and the
capacitor is connected to the drain reservoir, with $Y=1$. All calculations
performed for the single inverter are obtained using numerically exact time
evolution, obtained using a Padé approximation Al-Mohy and Higham (2010) with
a truncated Hilbert space of $16C_{\mathrm{g}}(V_{\mathrm{d}}+4)$. For
calculations where simulation times are not explicitly shown, we use time
steps distributed logarithmically up to $10^{16}\beta\hbar$.

Figure 1(b) shows the time dependent response of the inverter to an
alternating input voltage, with the left and right panels corresponding to
setting $X=0$ and $X=1$, respectively at $t=0$. Lower cross-voltages require
less electron accumulation in the capacitor gate, and additionally
fluctuations in the gate output are significantly larger for smaller
$V_{\mathrm{d}}$. These small accumulations and large fluctuations lead to
response times that are orders of magnitude faster at low cross-voltages,
highlighting a trade-off between output certainty and characteristic response
time. While the steady-state statistics of the charged and discharged inverter
are symmetric, we observe that the dynamics are not. As accentuated at larger
$V_{\mathrm{d}}$, the capacitor discharging happens rapidly, while charging
occurs relatively slowly. This difference can be understood energetically.
When discharging the capacitor, its occupation regulates the voltage in such a
way that discharging becomes energetically more favorable as the gate empties.
In the opposite direction, the accumulation of electrons becomes more
energetically unfavorable as the gate charges, causing an exponential slowing
of current into the gate as a function of time. Additionally, this leads to
circulation of electrons between the transistors and capacitor when charging,
while electrons move directly from the capacitor out of the inverter when
discharging. The functionally unnecessary transitions caused by this
circulation cause higher heat dissipation rates during the loading process.

To understand more precisely the interplay between the thermodynamic and
operational costs for the inverter, we can employ a thermodynamic uncertainty
relationship

$\displaystyle\chi_{\mathrm{p}}^{2}=\frac{\langle\tau_{\mathrm{p}}\rangle^{2}}{\langle\delta\tau_{\mathrm{p}}^{2}\rangle}\leq\frac{\langle
Q\rangle}{2qV_{\mathrm{T}}}$ (2)

where brackets indicate an trajectory ensemble average, $\tau_{\mathrm{p}}$ is
the first passage time to an output voltage passing the accuracy threshold
$\alpha$ 222$\tau_{\mathrm{p}}$ is calculated using an initial state
corresponding to the steady-state of the inverter with the inverse input
voltage and using absorbing boundary conditions as is standard Sharpe and
Wales (2021), and $\delta x=(x-\langle x\rangle)$ Gingrich and Horowitz
(2017). The thermodynamic uncertainty relationship is a general result from
stochastic thermodynamics, valid for any Markovian jump process. It states
that the certainty in the first passage time, $\chi_{\mathrm{p}}$, is bounded
from above by the heat dissipated over a trajectory, $Q$, defined as
$Q=\int_{0}^{\tau_{\mathrm{p}}}dt\ \dot{Q}(t)$, with
$\dot{Q}(t)=\sum_{i,j}W_{ij}P_{j}(t)\ln W_{ji}/W_{ij}$ Esposito and Van den
Broeck (2010). The bound relates the minimum thermodynamic cost for a given
desired certainty in the first passage time. In practical terms, higher
certainty in operation time allows for processing input bits at higher rates
with lower probabilities of incorrect or inconclusive readings, while reducing
excess dissipated heat caused by longer operating times. Figure 1 (c) shows
how this bound depends on the cross-voltage. For the discharging process, we
observe an optimal compromise between first passage time certainty and heat
dissipation near $V_{\mathrm{d}}=5V_{\mathrm{T}}$. No such peak is immediately
evident for the charging process and, more strikingly, the bound is
significantly looser due to larger fluctuations in first passage times and the
excess dissipated heat caused by internal cycle currents. That the bound is
not saturated for any $V_{\mathrm{d}}$ implies that the operation of the NOT
gate is not limited by thermodynamic constraints and that observed limits are
products of the particular CMOS design and operation.

In Fig. 1 (d), we vary the cross-voltage and plot the trade-off between first
passage time certainty and heat dissipation, as a function of the probability
of a correct output at long times $P_{\mathrm{correct}}=\langle
Y\rangle_{X=0}$, where the ensemble average is over long-time trajectories
with the specified input. We additionally show multiple curves corresponding
to differing values of $\alpha$ and observe the emergence of an optimal trade-
off, near $V_{\mathrm{d}}=3$. Loosening $\alpha$ moves the curves
significantly towards the bound by dissipating less heat. The combination of
these effects allows for thermodynamically optimal operation at higher
probabilities of correct outputs as $\alpha$ increases, with similar but less
pronounced effects not shown for the discharging process.

Figure 2:  Characterization of the memory device’s behavior and adherence to
thermodynamic speed limits. (a) Probability of $V_{\mathrm{out}}$ as a
function of $V_{\mathrm{d}}$, with crosses locating points of maximum
probability at each $V_{\mathrm{d}}$ illustrating the onset of bistability.
Example trajectories are shown for before and after the onset of bistability.
(b) Mean time for a memory error as a function of the inverter relaxation
time, controlled by increasing $V_{\mathrm{d}}$, as indicated on the top
x-axis label, with the red dashed line indicating
$\langle\tau_{\mathrm{err}}\rangle=\langle\tau_{\mathrm{p}}\rangle$. The
shaded region is forbidden by the dissipation time uncertainty principle.

_Memory Device –_ Next we consider a static random access memory (SRAM) device
built by coupling two inverters, as shown in the inset of Fig. 2 (a). This
device operates using so-called flip-flop circuitry, meaning it exhibits a
bistable steady-state, which is a dynamical consequence of a pitchfork
bifurcation. The inverter’s state can be set by switching on
$V_{\mathrm{set}}^{1}$, employing feedback from $V_{\mathrm{out}}^{1}$ to
$V_{\mathrm{in}}^{2}$. Here, we will focus on memory maintenance, which can be
reliably achieved at sufficiently large cross-voltages by switching both
setting voltages off and both feedback loops on. To simulate the memory
device, we perform an approximate evolution using a fourth-order Runge-Kutta
scheme acting on a truncated Hilbert space using a time step of $\Delta
t=\beta\hbar/10$ until a final time of $t_{\mathrm{f}}\approx
10^{6}\beta\hbar$.

Figure 2 (a) shows the steady-state probability of observing an output voltage
$V_{\mathrm{out}}=V^{\mathrm{out}}_{1}$. The requisite bistability for memory
storage arises at $V_{\mathrm{d}}/V_{\mathrm{T}}\approx 2.5$ where the cross-
voltage overcomes the effects of thermal fluctuations. Notably the bistability
is a unique consequence of the nonequilibrium driving, which disappears in the
absence of a finite cross-voltage. At finite $V_{\mathrm{d}}$, the degeneracy
of the steady-state manifests as a spontaneous switching of $V_{\mathrm{out}}$
as a function of time, illustrated in Fig. 2 (a), as evaluated using Gillespie
simulations Gillespie (1976). For large $V_{\mathrm{d}}$ we observe
$V_{\mathrm{out}}/V_{\mathrm{d}}$ is localized near 0 or 1 for time scales
much larger than individual inverter operation time scales
$\langle\tau_{\mathrm{p}}\rangle$, indicating persistent memory storage. At
long times, however, output voltage is stochastically inverted, corrupting the
memory storage.

We define $\tau_{\mathrm{err}}$ as the time required for a memory device,
initialized in one of the bistable states, to experience a bit flip memory
error. Figure 2 (b) shows the average time required for a bit flip to occur
$\langle\tau_{\mathrm{err}}\rangle$ 333$\langle\tau_{\mathrm{err}}\rangle$ is
computed by initializing the gate in one of the bistable states then using
absorbing boundary conditions as is standard Sharpe and Wales (2021) to
compute the probability distribution of first passage times into the inverse
state. For practical reasons, because the distribution of first passage times
takes the form $P(\tau_{\mathrm{err}})\sim e^{-k\tau_{\mathrm{err}}}$, for
large $V_{\mathrm{d}}$, we use calculations at intermediate times to compute
$k$ from which we calculate $P(\tau_{\mathrm{err}})$ and
$\langle\tau_{\mathrm{err}}\rangle$.  as a function of the characteristic time
of a single inverter. We observe that the rate of memory error occurrences
decreases exponentially with respect to $\langle\tau_{\mathrm{p}}\rangle$,
thus increasing the average memory stability time by roughly five orders of
magnitude, from about $100$ ns to $20$ ms for
$V_{\mathrm{d}}/V_{\mathrm{T}}=2$ to 5. The dissipation time uncertainty
principle Falasco and Esposito (2020) puts a lower bound on the average time
for a bit flip memory error to occur

$\displaystyle\langle\tau_{\mathrm{err}}\rangle\geq\left(\beta\langle\dot{Q}\rangle\right)^{-1}$
(3)

where $\langle\dot{Q}\rangle$ is the average rate of heat dissipation in the
steady-state. The region restricted by this lower bound is shown as the shaded
area in Fig. 2 (b), indicating that the inequality is satisfied, but far from
saturated. This suggests that energy pumped into the SRAM device is
efficiently directed into preserving the memory state. Indeed this can be
quantified using a nonequilibrium version of transition state theoryKuznets-
Speck and Limmer (2021). Transition state theory bounds the rate of a
transition between two metastable states using the stationary distribution
$P_{\mathrm{ss}}(V_{\mathrm{out}})$ and an uncorrelated estimate of the time
to cross a dividing surface between the two states. Taking the dividing
surface to be $V_{\mathrm{out}}=V_{\mathrm{d}}/2$, and the typical time to
cross the barrier as $\langle\tau_{\mathrm{p}}\rangle$, a nonequilibrium
transition state theory estimate for $\langle\tau_{\mathrm{err}}\rangle$ is

$\displaystyle\langle\tau_{\mathrm{err}}\rangle\gtrsim\langle\tau_{\mathrm{p}}\rangle\frac{P_{\mathrm{ss}}(V_{\mathrm{out}}/V_{\mathrm{d}}\leq\alpha)}{P_{\mathrm{ss}}(V_{\mathrm{out}}/V_{\mathrm{d}}=1/2)}$
(4)

which is shown in Fig. 2 (b). Here the steady-state has been evaluated
numerically with $\alpha=0.4$. The nonequilibrium transition state theory
provides a very accurate estimate of the memory time, reflecting the
likelihood of observing a fluctuation of $V_{\mathrm{out}}=1/2$ as becoming
exponentially unlikely with increasing $V_{\mathrm{d}}$ in accord with recent
large deviation function analysisFreitas  _et al._ (2022). The accuracy of the
transition state theory estimate demonstrates that little energy is wasted
speeding up transitionsKuznets-Speck and Limmer (2021).

Figure 3:  Adherence to thermodynamic bounds of the logical clock. (a)
Rescaled voltage autocorrelation function
$C_{V_{i},V_{i}}^{*}(t)=C_{V_{i},V_{i}}(t)/C_{V_{i},V_{i}}(0)$ as a function
of applied cross-voltage. Example trajectories at
$V_{\mathrm{d}}=[2.1V_{\mathrm{T}},7V_{\mathrm{T}},12.1V_{\mathrm{T}}]$, with
each curve representing how the output voltage of one of the inverters
evolves. (b) The certainty in clock operation time $\chi_{\mathrm{mem}}$ as a
function of average clock cycle time $\langle\tau_{\mathrm{c}}\rangle$ and
applied cross-voltage (top axis) (green squares), with the shaded regions
indicating the forbidden regions from the uncertainty relations. The red
dashed line indicates where
$\langle\tau_{\mathrm{c}}\rangle^{2}=\langle\delta\tau_{\mathrm{c}}^{2}\rangle$.
(c) The certainty in clock operation as in (b) with the simple threshold
control mechanism.

_Clock –_ An uneven number of inverters coupled sequentially in a ring creates
a system with a frustrated steady-state, because all inverters cannot
simultaneously output the logical inverses of their inputs. This frustration
causes cyclic oscillations, whose period is controlled by inverter operation
times, making the device operate as a clock under deterministic conditions and
providing an example of circuitry with non-trivial functionality. To simulate
the dynamics of such a clock, we perform kinetic Monte Carlo simulations using
the Gillespie algorithm. We define the time for the clock to undergo a single
cycle $\tau_{\mathrm{c}}$ as the time for the output, $Y$, to cycle from
$1-\alpha$ to $\alpha$ and back again to $1-\alpha$, using $\alpha=0.4$. All
results are averaged over simulations containing at least 50,000 clock cycles.

In Fig. 3 (a), we show the output voltage autocorrelation function
$C_{V_{i},V_{i}}(t)=\langle\delta V_{i}(0)\delta V_{i}(t)\rangle$, as a
function of time and cross-voltage. At low cross-voltages, the three output
voltages evolve nearly independently, with $C_{V_{i},V_{i}}(t)$ revealing
exponential correlations. Above $V_{\mathrm{d}}\approx 3V_{\mathrm{T}}$
persistent oscillations emerge but are damped by the stochasticity of the
evolution. We find a maximal persistence in the autocorrelation function
oscillation at $V_{\mathrm{d}}\approx 7V_{\mathrm{T}}$, where the clock
undergoes approximately 3.5 cycles. In this region oscillations are persistent
for long times and the fluctuations in $\tau_{\mathrm{c}}$ are small relative
to the mean cycle time. Above $V_{\mathrm{d}}\approx 10V_{\mathrm{T}}$, the
autocorrelation exhibits oscillation for only 1/2 of a cycle because, while
oscillations are persistent for long times, the fluctuations in
$\tau_{\mathrm{c}}$ are large relative to the mean cycle time as anticipated
from Fig. 1 (c) and the single NOT gate. In this regime, we find the cycle
time to be inversely proportional to to voltage output amplitude, which
evolves stochastically.

We define the certainty in the cycle time as
$\chi_{\mathrm{mem}}=\sqrt{\langle\tau_{\mathrm{c}}\rangle^{2}/\langle\delta\tau_{\mathrm{c}}^{2}\rangle}$,
and plot this for $V_{\mathrm{d}}\in[1V_{\mathrm{T}},20V_{\mathrm{T}}]$ in
Fig. 3 (b). The red dashed line indicates where the cycle time’s fluctuations
are equal to its mean, where we find a narrow range of cross-voltages where
there is reliable cycling. The thermodynamic uncertainty relationships
expressed in Eqs. 2 and 3 can be adapted to give upper and lower bounds on
this quantity

$\displaystyle\sqrt{\frac{\langle
Q\rangle}{2}}\geq\chi_{\mathrm{mem}}\geq\sqrt{\frac{\langle\tau_{\mathrm{c}}\rangle}{\beta\langle\dot{Q}\rangle\langle\delta\tau_{\mathrm{c}}^{2}\rangle}},$
(5)

where $\langle Q\rangle$ is the average heat dissipated over a cycle, and
$\langle\dot{Q}\rangle$ is the average rate of heat dissipation in the steady-
state. The upper and lower bounds are shown as the shaded regions in Fig. 3
(b), showing that the upper bound is best saturated when $\chi_{\mathrm{mem}}$
is maximized. This occurs for a large enough cross-voltage that the coupled
inverters exhibit bistability, but not so large that the fluctuations in the
transition time are large.

To expand the range of reliable cycle times, we propose a simple control
mechanism acting between each of the inverters. If the output voltage from an
inverter is greater than $1-\alpha$, then a thresholding mechanism exerts work
on the system and provides an input voltage of exactly $V_{\mathrm{d}}$ to the
next inverter in the cycle, with an analogous threshold setting the input to
$0$ if the output is less than $\alpha$. By doing this, the inverter is always
driven with an optimal input voltage amplitude, circumventing the slow
response observed when voltage amplitudes are small. Figure 3 (c) shows the
resulting performance of $\chi_{\mathrm{mem}}$. As the cross-voltage
increases, $\chi_{\mathrm{mem}}$ increases monotonically, avoiding the loss in
cycle time certainty at large cross-voltages, plateauing to provide constant
clock reliability across a broad range of cycle times. The uncertainty
relationships continue to be best saturated at intermediate values of
$V_{\mathrm{d}}$, indicating optimal heat dissipation costs for cycle
certainty remains in a similar range as without control.

_Conclusion –_ We have used a Markovian model for realistic logical inverters
in the regime of thermodynamic computing to explore the interplay between
operating characteristics, like accuracy and time, and thermodynamic
properties, particularly heat dissipation. Our results demonstrate the
theoretical limits of CMOS circuits using bounds derived from stochastic
thermodynamics. As we have shown, this provides a framework for simultaneously
exploring the fundamental behavior of noisy computational circuits,
characterizing their optimality, and using the gained insight to propose more
efficient operating procedures and circuits. We expect this work will provide
a foundation for future work towards understanding and designing efficient
thermodynamic computers. Current techniques should allow for the improvement
of thermodynamic efficiencies by adapting principles from optimal control
theory to operational control schemes Das and Limmer (2019); Lucero  _et al._
(2019); Engel  _et al._ (2022); Boyd  _et al._ (2022); Guéry-Odelin  _et al._
(2022); Wimsatt  _et al._ (2021) and by exploring the effects of circuit
layout Wolpert and Kolchinsky (2020). To extend this approach to larger
circuits, more scalable simulation techniques, such as tensor network methods
Orús (2014); Helms and Chan (2020); Causer  _et al._ (2022); Bañuls and
Garrahan (2019); Strand  _et al._ (2022), can be adapted.

_Acknowledgments –_ We thank Gavin Crooks for useful discussions. This work
was supported by NSF Grant CHE-1954580.

_Data availability –_ The source code for the calculations done and all data
presented in this work are openly available on Zenodo at
https://doi.org/10.5281/zenodo.7251316 Helms and Limmer (2022).

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