# High Performance and Optimal Configuration of Accurate Heterogeneous Block-
Based Approximate Adder

Ebrahim Farahmand1, , Ali Mahani1, Muhammad Abdullah Hanif2,
Muhammad Shafique3 Manuscript received 2021. Corresponding author: A. Mahani
(email<EMAIL_ADDRESS>1Department of Electrical Engineering, Shahid
Bahonar University of Kerman, Iran  2Institute of Computer
Engineering,Technische Universität Wien, Vienna, Austria  3 Division of
Engineering, New York University Abu Dhabi, UAE

###### Abstract

Approximate computing is an emerging paradigm to improve power and performance
efficiency for error-resilient application. Recent approximate adders have
significantly extended the design space of accuracy-power configurable
approximate adders, and find optimal designs by exploring the design space. In
this paper, a new energy-efficient heterogeneous block-based approximate adder
(HBBA) is proposed; which is a generic/configurable model that can be
transformed to a particular adder by defining some configurations. An HBBA, in
general, is composed of heterogeneous sub-adders, where each sub-adder can
have a different configuration. A set of configurations of all the sub-adders
in an HBBA defines its configuration. The block-based adders are approximated
through inexact logic configuration and truncated carry chains. HBBA increases
design space providing additional design points that fall on the Pareto-front
and offer better power-accuracy trade-off compared to other configurations.
Furthermore, to avoid Mont-Carlo simulations, we propose an analytical
modelling technique to evaluate the probability of error and Probability Mass
Function (PMF) of error value. Moreover, the estimation method estimates
delay, area and power of heterogeneous block-based approximate adders. Thus,
based on the analytical model and estimation method, the optimal configuration
under a given error constraint can be selected from the whole design space of
the proposed adder model by exhaustive search. The simulation results show
that our HBBA provides improved accuracy in terms of error metrics compared to
some state-of-the-art approximate adders. HBBA with 32 bits length serves
about $15\%$ reduction in area and up to $17\%$ reduction in energy compared
to state-of-the-art approximate adders.

###### Index Terms:

Approximate adders, Error analysis, Performance estimation, Low power, Low
latency.

##  I Introduction

Nowadays, due to high computational requirements of advanced applications,
computing systems are becoming more-and-more resource hungry. Based on
energy/power, area and cost requirements issues computing systems cannot be
used in edge-based applications. Approximate computing has achieved notable
attention for its potential to increase computing efficiency in terms of
performance, power, and area [1], specifically for error-resilient
applications. Recent investigations have shown that approximate computing is
an emerging paradigm for error-tolerant application, such as multimedia, image
processing, deep learning, and data mining, which do not necessarily need full
precision output.

Adders are essential blocks in arithmetic circuits, as they are one of the
fundamental building blocks of other arithmetic operations, such as a
multiplication, division and subtraction. Hence, the approximation of adders
may significantly improve the performance and energy/power efficiency of
applications. Typically the critical path in adders is on the carry
computation chain [2]. State-of-the-art low-latency and low power approximate
adders exploit carry chain truncation and logic simplification to offer
quality-efficiency trade-off. A variety of approximate adders were proposed in
[3].

Key Design Challenges: The following constraint shows the importance of
approximate adders and their statistical analysis hardware implementation:

  * •

Adder’s hardware design bottleneck: In digital design, power, area and delay
of the circuit are considered as the key performance metrics. Generally, for
adders, these metrics increase rapidly with bit-width ($N$). From delay
prospective, delay is determined by the length of carry propagation. In
practical applications, the average length of carry propagation is shorter
than $log_{2}N$ as equating to bit-width [4]. Since the length of carry
propagation is considered as the key criterion for designing low-latency
approximate adders in the research works.

  * •

Limitations of Exhaustive Simulations: The exact evaluation of the adder’s
error metrics needs to simulate all possible inputs combinations, i.e.
$2^{2N}$ for $N$-bit adder. Hence, simulation time exponentially increases
with adder bit-width. The statistical analysis prevents the high computational
burden and provides an insight into the relationship between adder structure
and error.

  * •

Optimal Configuration Selection: Selecting the optimal configuration, which
offers the lowest area, power and delay while meeting the desired application
accuracy, is a design space exploration problem and may be challenging if the
number of potential adder configurations is large. To select the best
configuration for a predefined accuracy constraint, different adder
configurations must be compared, which leads to prolonged and practically-
infeasible computational time. To select optimal configuration, the design
space takes the following things into account:

    * –

Error metrics, e.g., error rate, MED and MSE, that can be computed using the
Probability Mass Function (PMF) of error value.

    * –

Hardware design metrics, i.e., area, power and delay

Related Works and Their Limitations: In the earlier approaches, researchers
have focused on transistor-level modifications to approximate the circuit [5],
[6]. The well-known techniques, such as voltage over-scaling (VOS) technique
[7]-[8], clock overgating [9] and transistors number reduction [10], are used
to approximate the adder circuit. The researchers need to implement a circuit
layout for these methods, which takes effort.

The next step in designing approximate adders is architectural-level
modifications for quality-efficiency trade-off. In this step, adders can be
classified into three categories.

  * •

Variable Latency Adder (VLA), in which the carry for each individual bit
location is dependent on its previous $K$ bits instead of all $N$ prior bits
[11].

  * •

Inexact Logic Configuration Adder (ILCA), in which the less significant bits
(LSBs) are computed using approximate logic. The primary approximation adders
that fall in this category are Lower-Part-OR Adder (LOA) [12] and approximate
XOR/XNOR-based adders for inexact computing (AXA) [13]. The LOA uses OR gates
instead of full adders at the LSB locations of the adder. The LOA’s design
space is limited and contains only a limited number of configurations,
equivalent to the bit-width of the adder.

  * •

Block-Based Adder (BBA), in which the adders are constructed using smaller
approximate and accurate sub-adders that have smaller carry chain than the
carry chain of the corresponding accurate adder. The approximate blocks can be
formed by homogeneous approximate blocks or heterogeneous. The adder which
utilizes homogeneous approximate blocks is called Homogeneous Block-Based
Adder (Homo-BBA), and the heterogeneous approximate blocks are called
Heterogeneous Block-Based Adder (HBBA). HBBA can further be classified into
two sub-categories based on whether the adder contains redundant blocks or
disjoint blocks. In redundant blocks sub-category, blocks have some
overlapping region (in term of bit locations) with other blocks. Therefore,
the size of the carry chain that defines the critical path depends on the
length of the largest block. In disjoint blocks sub-category, the blocks are
disjoint and the critical path depends on the length of the largest block. The
BBA is commonly used due to its lower error ratio than the rest of adders
type. Some adder designs that fall in this category are Almost Correct Adder
(ACA-I) [14], Carry-Skip Approximate Adder (CSAA) [15] and Gracefully
Degrading Adder (GDA) [16].

The BBAs have emerged as a promising architecture of approximate adder. Zhu et
al. have proposed 4 variants of error-tolerant BBAs ,i.e, ETAI and ETAII [17],
ETA III [18], ETAIIM [19]. The Carry Cut-Back Adder (CCBA) [20] is monitored
to detect the long path of the carry chain followed by cutting the carry
chain. Another BBA has proposed in [2]. In this technique the non-overlapping
sub-adders uses a carry predictor unit and a selector unit to decide whether
the carry out of each sub-adder is propagated or not. Generic Accuracy
Configurable Adder (GeAr) [21] utilizes redundant blocks leading to excessive
hardware overhead. The Reverse Carry Propagate Adder (RCPA) [22] propagates
the carry-in a counter-flow manner from the MSB, i.e. carry-in, to the LSB,
i.e. carry-out. The RCPA is not efficient in case of delay. In general, it
should be noted that these methods have fixed configurations with limited
flexibility and a massive error value.

On the other hand, Some methods contribute to flexibility in design by
supporting multiple configurations. QuAd [23] is an enhanced model of GeAr
with flexibility. In the QuAd adder, the sub-adders have different sizes as
well as size of carry prediction which is part of sub-adders inside block-
based adders. A reconfigurable approximate adder is proposed in [24], and it
employs the carry look ahead (CLA) method. The adder is split into two
disjoint segments, i.e., approximate part and augment part. This adder is
reconfigurable, and it is possible to switch between the accurate and
approximate operation by using a multiplexer. This technique imposes hardware
overhead; henceforth, Xu et al. proposed another reconfigurable adder called
Simple Accuracy-Reconfigurable Adder (SARA) [25]. In SARA, the adder is
divided to $K$ disjoint sub-adders. Moreover, it uses an error recovery
circuit to reduce the error, which imposes additional hardware overhead.
Additionally, the utilized ripple carry adder in sub-adder causes a long
critical path. Note that in [23], [24] and [25], the flexibility offered by
design comes with additional hardware cost, and moreover, these designs only
consider homogeneous blocks.

Besides all the discussed methods, the other crucial factors in approximate
computing are error probability and its evaluation. An analytical model for
homogeneous overlapping blocks is proposed in [26]. In this article, in
addition to proposing the generic methodology for error probability, the PMF
of error value is also evaluated. Another analytical model is proposed in [27]
which focuses on error metrics of adders with two segments, one accurate and
the other inaccurate segment. In [28], error metrics are obtained based on an
analytical model and generalized analytical model for equal redundant segments
with homogeneous blocks. The authors have used optimization technique to
optimize the design’s estimated parameters such as delay, power, and area.
Also, the given accuracy is considered as a constraint in the optimization
framework. However, the adverse drawback of these analytical methods is not
considering heterogeneous approximate blocks in precise evaluation of
probability of approximate adders error. Moreover, estimation model for error
metrics, e.g MSE, is proposed by the PEAL [29]. It estimated the error metrics
by evaluating carry-out probability for each approximate FA. The PEMACx [30]
is a novel analytical method for efficiently computing the error’s PMF of
adder that consist of cascaded approximate adder units. In this article, the
probability of carry-out error is evaluated for each cascaded approximate
adder unit and these probabilities are used recursively as carry-in
probabilities for next stages to recursively evaluate the probability of
carry-out error for last stage. We have proposed an analytical model to cover
the internal errors and the errors between the heterogeneous approximate
blocks, allowing the blocks to be of various architectures in order to address
the following limitations.

Summary of Key Limitation: In general, all the above-mentioned approaches
suffer from the following limitations:

  * •

The methods focused on homogeneous block-based adders, and they did not
consider heterogeneous block-based adder.

  * •

The methods have either fixed configurations with limited flexibility, which
results fixed configuration adder neglects different configurations with the
same accuracy. Furthermore, in the case of flexible configuration design, they
have high hardware complexity and high computational burden.

  * •

The error metrics are computed by exhaustive simulation and computer
simulations, which are feasible for small sized adders. Moreover, the methods
do not consider the use of inexact logic in BBA design, which is defined as
internal block error.

Overview of Our Novel Concept and Design Space: In this paper, we focus on
heterogeneous block-based approximate adders. In the proposed structure, the
adder is segmented into disjoint blocks, in which the carry-in depends only on
carry generation part of the previous block. Also, the block’s carry-in is
predicted considering only some of the previous bits to reach the small carry
chain. The prediction of carry for the next block is selective based on the
accuracy level. For approximating the LSB part, we replace the full adders
with OR gates, which results in logic simplification but at the cost of some
accuracy loss. We consider logic simplification as an internal error in the
approximate block. For our HBBA each approximate sub-adder can have any number
of inexact logic configuration (OR gates) $L$ and carry chains $S$ bits. An
$N-bit$ HBBA adder consist of $k$ approximate sub-adder is defined using a
inexact logic configuration vector, $L_{vec}=[L_{1},L_{2},...,L_{k}]$ and
carry chain vector, $S_{vec}=[S_{1},S_{2},...,S_{k}]$ where, $L_{i}$ and
$S_{i}$ represent the number of inexact logic and carry chain bits in the
$i^{t}h$ sub-adder, respectively. Hence, the generic HBBA representation,
$HBBA\\{[L_{1},L_{2},...,L_{k}],[S_{1},S_{2},...,S_{k}]\\}$ fully defines any
possible adder configuration. HBBA approximate adder provides a configuration
that is still not considered by any prior adders, such as LOA configurations.
Consider an example where we would like to develop an 8-bit approximate adder
using 4-bit sub-adders. Figure1 illustrates the complete design space of HBBA
against LOA. Here, MED and delay are used as error metric and digital design
metric, respectively.

Figure 1: Design Space of an 8 bits approximate adder with 4 bits sub-adders

Figure1 shows that different design configurations are overlooked in LOA, as
these configurations may provide design points with less delay in the same
accuracy. The optimal hardware configuration can lead to efficient and goal-
oriented design based on accuracy-hardware metrics trade-off. Here, the trade-
off is modelled by a hybrid methodology, including a statistical and
analytical estimation model to improve the performance of the designed
circuit. The statistical model is used to calculate error metrics, including
the probability of error and probability mass function (PMF) of error value in
the output of the approximate adder. In our proposed analytical model, we are
able to reorder blocks to attain accuracy. Besides, the analytical estimation
model is proposed to estimate delay, power and area in hardware design.

Key Novel Contributions: The overall flow of our contribution is illustrated
in figure 2. The steps are summarized in the following novel contributions:

  * •

Heterogeneous block-based approximate adder design: We focus on heterogeneous
block-based approximate adders, making the design flexible and improving
hardware metrics such as area, delay, and power.

  * •

Analytical analysis of error metrics and Estimate Model for Design Metrics: A
generic methodology is proposed for analytical modelling of probability mass
function (PMF) of error in the output of the approximate adder. The analytical
model helps avoid the computer simulation. Moreover, estimation model is
developed to estimate the delay, power and area as design metrics.

  * •

Explore in flexible configuration of BBA: Proposed models help in fast
exploration of the design space and in identifying the Pareto-optimal
configurations for an $N$ bits adder.

Figure 2: Diagram of Proposed adder

##  II Proposed Methodology

An HBBA adder operates on two N-bit inputs
$A=(a_{N},a_{N-1},...,a_{i},...,a_{1})$ and
$B=(b_{N},b_{N-1},...,b_{i},...,b_{1})$. It is segmented to k disjoint blocks,
as illustrated in Figure 3.

Figure 3: General block diagram of a segmented adder

To explain our proposed adder design, we start by explaining the conventional
carry look ahead (CLA) and then our modifications that generates a while new
design space. In the CLA, carry-out of each BBA’s block is calculated based on
Eq. 1 in which it is assessed by generate and propagate signals of each bit
location. The generate and propagate signals are described by Eq. 2 for each
bit, $i(1\leq i\leq N)$.

$c_{i+1}=g_{i}+p_{i}g_{i-1}+...+g_{1}\prod_{j=2}^{i}p_{j}+g_{0}\prod_{j=1}^{i}p_{j}+c_{i}\prod_{j=0}^{i}p_{j}$
(1) $p_{i}=a_{i}\oplus b_{i},g_{i}=a_{i}.b_{i}$ (2)

Where, $c_{j}$ is carry-in of $j$-th block, $c_{j+1}$ is carry-out of each
block, and $g_{i}$ and $p_{i}$ respectively correspond to generate bit and
propagate bit. The carry-out logic circuit is illustrated in figure 4.

Figure 4: Logic expression of carry out generation

###  II-A The proposed adder

The proposed adder is segmented to $S$ blocks where each block is an $H$ bits
sub-adder and $S=\lceil N/H\rceil$. The blocks used in this adder are not
homogeneous and fall into two types, i.e., accurate and approximate blocks.
The accurate block is mainly used for MSBs and the approximate block is used
for LSBs. The accurate blocks add the $H$ bits of the two inputs using a carry
look ahead (CLA). The approximate blocks use combined logic simplification (OR
gates replacement), full adders and carry look ahead to add the $H$ bits of
the inputs. In the calculation of the approximate block’s carry-out, the
number of bits in use is varied. Consequently, we are free to define the
length of carry generations and propagation in every approximate block. For
instance, Figure 5 shows a 4-bit approximate block with 3 bits to propagate
the carry, and lower 2 FAs are replace with OR gates for computing the
corresponding sum bits.

Figure 5: Approximate block with H bits (H=4) length

We have heterogeneous approximate blocks with various configurations placed in
different position in the proposed adder. As an example, a 16 bits adder with
two heterogeneous approximate blocks is shown in figure 6. In order to obtain
the output of sixteenth bit in figure 6, only ten bits are needed to propagate
carry. However, in CLA, all sixteen bits are required to propagate carry.

Figure 6: 16 bits approximate adder

Follow up on the proposed HBBA; we elaborate on the analytical analysis method
for heterogeneous approximate blocks. Afterwards, these analysis results are
used in obtaining PMF of approximate adder error, which are further discussed
in section II-F. Furthermore, the estimation model is developed for estimating
the hardware metrics of HBBA. Finally, the optimal configurations are chosen
for heterogeneous approximate blocks based on quality-efficiency trade-off.

###  II-B Error Analysis

In approximate adders, besides the conventional performance metrics such as
delay, area and power, the error metrics are used to compare adders. The
conventional error metrics: error rate (ER), error distance (ED), mean error
distance (MED), mean square error (MSE), mean relative ED (MRED), and
normalized ED (NED) [28]. Among these metrics, the error distance (ED), error
rate (ER), and mean error distance (MED) are more important and applicable for
comparison the adders [31]. These metrics can be calculated either through
computer simulation or an analytical model. Due to the greater benefits of
analytical model, an analytical model is proposed in this work. The primary
advantages of a proposed analytical model consist of:

  * •

It facilitates the comparison between the different accuracy level without
compromising the computational time.

  * •

This proposed analytical model is used in exploring design space in order to
obtain optimal circuit parameters such as carry chain length, number of
approximate blocks and accurate blocks.

In this respect, it provides insight into the relation between circuit
specifications and error statistics, which is helpful for the designers to
tune circuit parameters based on the desired accuracy level.

In the following, we introduce the analytical analysis on the adder’s error
and compare them with numerical tests. The error in each approximate block is
propagated to the final adder’s output, in which the sources of error is the
prediction of carry or inaccurate computation (internal block error). The
error in the prediction of carry-out in the $i$-th approximate block is due to
a truncation in the carry chain. Moreover, another error of inaccurate
computation is due to the substitution of the OR gate instead of the full
adder. So the probability of error in approximate adder’s output corresponds
to Eq.3

$Probability(Error)=Probability(S_{app}\neq A+B)$ (3)

Where $A$ and $B$ indicate inputs of the adder and $S_{app}$ stands for the
approximate sum calculated by the proposed adder. In addition to the
probability of error, other metrics such as MSE, NMED and NED are considered
for comparison between adders. However, these metrics are not satisfactorily
informative since they are the average of different errors over all the
inputs. So, it is more pertinent to use the PMF of error value as performance
metrics. The PMF of error value indicates the probability of error enormity
and significance of each error value. Hence, to evaluate the PMF of error
value in the proposed heterogeneous approximate block, first, we identify the
source of errors. Next, we evaluate probability error values, and eventually,
we represent the error rate in a generalized form of the heterogeneous
approximate adder. The proposed methodology is shown in figure 7, which
consists of the following stages:

Figure 7: Proposed methodology

  * •

Identification of the error sources (stage 1 and stage 2): The first and
second stages are to identify the sources of errors in the approximate block,
which cause the erroneous output. The analytical model for the approximate
block is identified as the sum of the probability of joint internal block
error and intermediate block error events. The sources of internal and
intermediate block error are logic simplification, which is called $E_{1}$,
and carry truncation called $E_{2}$, respectively. The analytical model of
these errors individually are presented in sub-section II-C

  * •

Find joint error events (stage 3): In this stage the analytical model is
proposed to find the joint error events in approximate blocks. The evaluation
of this stage is explained in figure 7 and elaborated in sub-section II-D.

  * •

PMF of error value Evaluation for the approximate block (stage 4): The PMF of
error value in the approximate block is obtained by evaluating the probability
of the error sources and the joint probability of errors. The description of
this step is presented in sub-section II-D.

  * •

PMF of error value Evaluation in approximate adder (stage 5 and stage 6): PMF
of error value in approximate adder is calculated by independent error events
of all blocks. This is given by the multiplication of error events. The PMF of
error value is calculated by the inclusion-exclusion principle shown in stage
7. This approach is elaborated in sub-section II-F.

Moreover, the analysis for the evaluation of error rate is modeled based on
the stages in figure 7 and the details explain in sub-section II-E.

###  II-C Identification of the sources of error

The calculations of PMF for two error types in figure 7 are explained in the
following sub-sections.

####  II-C1 Replaced OR gates PMF error value evaluation

In order to evaluate PMF of replaced OR gates error value, we evaluate the PMF
of adder inputs. $P_{A}$ and $P_{B}$ are the probability distribution of
adder’s inputs, e.g., $A$ and $B$, respectively. Based on [26], if
$X=[a_{k2},...,a_{k1}]$ is a sub-group of bits in
$A=[a_{N-1},a_{N-2},...,a_{0}]$, where $0<k1<k2<N$, we can drive a probability
distribution of $X$ ($P_{X}(k)$) as follows:

$\begin{split}P_{X}(k)=&\sum_{i=0}^{2^{N-1-k2}-1}\bigg{(}\sum_{j=0}^{2^{k1}-1}P_{A}(2^{k2+1}i+2^{k1}k+j)\bigg{)}\\\
&0<k<2^{k2-k1+1}\end{split}$ (4)

For the other input $B$, $P_{Y}$ is derived from $P_{B}$ similar to $P_{X}$.
Since the two inputs are independent, the PMF of the summation $Z=X+Y$ is
calculated by convolution of $P_{X}$ and $P_{Y}$. Assuming that the
probability distribution of $A$ and $B$ are uniform between $0$ and $2^{N}-1$,
the $X$ and $Y$ are similarly uniform between $0$ and $2^{n}-1$. Therefore,
PMF of the sum is represented as follows:

$\displaystyle P_{Z}(k;n)=P_{X}(k;n)\circledast P_{Y}(k;n)$ (5a)
$\displaystyle P_{Z}(k;n)=\begin{cases}\frac{K+1}{2^{2n}}&\text{$0\leq k\leq
2^{n}-1$}\\\ \frac{2^{n+1}-k-1}{2^{2n}}&\text{$2^{n}-1\leq k\leq
2^{n+1}-2$}\\\ 0&\text{otherwise}\end{cases}$ (5b)

When OR gates embed $L$ bits of approximate block, an error value is obtained
between $0$ to $2^{L}-1$. The probability of error can be calculated by the
binary representation of error values at the bits, where the OR gate replaces
the full adder, and the resulting output bits are calculated after applying OR
gate to the input bits. The value at a given bit location is $1$ when both
values at the corresponding bit location in the inputs are $1$. Conversely,
value $0$ occurs when the corresponding bit location in the inputs are not $1$
simultaneously. Hence, the probability of error value for a given bit location
($k$), which has the value $1$, is evaluated by the probability intersection
of its two inputs in that particular position $(Pr_{x}(k)\cap Pr_{y}(k))$. For
the bit, which has value $0$, the probability of error value is evaluated by
$1-(Pr_{x}(k)\cap Pr_{y}(k))$. Since the inputs of every bit are independent
of each other, the intersection can be replaced by the product of the two
probabilities. In other words, the probability of error value in the position
of $k$ for a corresponding value of $1$ is evaluated by $Pr_{x}(k).Pr_{y}(k)$
and for the value $0$ is evaluated by $1-(Pr_{x}(k).Pr_{y}(k))$.
We present an example to demonstrate the proposed analogy in a particular
case. In the example, we assume uniformly distributed inputs and replace two
bit’s adder with two OR gates. For two bit’s adder, the error value are $1\leq
EV\leq 3$. Figure 8 illustrates the difference between two bits adder and OR
gates.

Figure 8: Error value of OR gates replacement

Based on figure 8 where $L=2$, the probability of error value (EV) in this
example is shown as follow:

$Pr_{EV\\_OR}=\begin{cases}\frac{9}{16}&\text{$x=0$}\\\
\frac{3}{16}&\text{$x=1,x=2$}\\\ \frac{1}{16}&\text{$x=3$}\\\ \end{cases}$ (6)

The probability of error value $1$, which in represented by binary equivalent
of ${}^{\prime}01^{\prime}$ is calculated as follow:

$x=^{\prime}01^{\prime}\Rightarrow Pr_{EV}=Pr(FBI=1)\cap Pr(SIBS\neq 1)$ (7)

Where $FBI=1$ is first bit of inputs are 1 and $SIBS\neq 1$ is second bit of
inputs are not 1 simultaneously. $Pr(FBI=1)$ is evaluated by
$Pr_{X}(first\,bit=1)\cap Pr_{Y}(first\,bit=1)$, and since two inputs are
independent, this expression is simplified to
$Pr_{X}(first\,bit=1).Pr_{Y}(first\,bit=1)$. Due to the uniformity in inputs
distribution, $Pr_{X}(first\,bit=1)=\frac{1}{2}$ and
$Pr_{Y}(first\,bit=1)=\frac{1}{2}$, and as a result, $Pr(FBI=1)=\frac{1}{4}$
and in the same manner, the other term of Eq.7 is given as follow:

$\begin{array}[]{cc}Pr(SIBS\neq 1)=1-(Pr_{X}(SB=1)\cap Pr_{Y}(SB=1))\\\
=1-(Pr_{X}(SB=1).Pr_{Y}(SB=1))=\frac{3}{4}\end{array}$ (8)

Where $SIBS\neq 1$ is second bit of inputs are not 1 simultaneously and $SB=1$
is second bit is 1. Based on Eq.7 and as a result of the independence between
input bits, this equation can be re-written as Eq.9.

$Pr_{EV}=Pr(FI=1).Pr(SIS\neq 1)=\frac{1}{4}.\frac{3}{4}=\frac{3}{16}$ (9)

The PMF of error values formula used for the above example verified by
empirical results is shown in Eq.6. The example discussed above hints at the
calculation of error value in two bits adders replaced with OR gate;
furthermore, we can expand this trend for $n$ bits adder.

According to the above description, we can formulate the summation of the
probability of error values for replaced OR gates ($Pr_{EV\\_OR}$) by Eq.10.

$\begin{array}[]{cc}&\sum_{i=1}^{L}Pr_{EV\\_OR}=\sum_{i=1}^{L}\binom{L}{i}.(Pr(OBI=1))^{i}\\\
&.Pr(OBIS\neq 1)^{L-i}\end{array}$ (10)

Where $OBI=1$ is one bit of inputs are 1 and $OBIS\neq 1$ is one bit of inputs
are not 1 simultaneously.

####  II-C2 Truncated Carry PMF Evaluation

Truncated carry is done from the selected position in $H$ bits approximate
block. If the length of carry chain is $S$ bits, the length of the truncated
carry is $H-S$ bits. In this case, the generated error value is equal to
$2^{H}$, and the probability of error value depends on the position of carry
truncation. In order to evaluate the PMF of error value of truncated carry, we
divide the approximate block into two segments. The first segment has $S$ bits
length from MSB, and the other segment has the remaining bits with $H-S$ bits
length. This segmentation is shown in figure 9. The error of truncated carry
occurs when the first segment generates the carry, and the next segment
propagates the carry.

Figure 9: Truncated carry Approximate block

Based on the above, the probability of error value for each approximate block
has been formulated as Eq. 11.

$Pr_{error\\_carry\\_truncated}=Pr(G_{1}\cap P_{2})$ (11)

Let $G_{1}$ and $P_{2}$ represent the carry generation by the first segment
and propagation carry by the second segment in the approximate block. Since
two segments are independent, the probability of generation and propagation of
carry can be consider as two independent events. Furthermore, the inputs of
two segments are disjoint bits group. Eq.12 can represent the probability of
error value of truncated carry.

$Pr_{error\\_carry\\_truncated}=Pr(G_{1}).Pr(P_{2})$ (12)

Thus, the PMF of the error value of truncated carry is evaluated by Eq. 13.

$Pr_{EV\\_truncate}=\begin{cases}Pr(G_{1}).Pr(P_{2})&\text{$x=2^{H}$}\\\
1-(Pr(G_{1}).Pr(P_{2}))&\text{$x=0$}\\\ \end{cases}$ (13)

Where $Pr_{EV\\_truncate}$ denotes the probability of error value of carry
chain truncation. Propagation of the carry by $S$ bits occurs when the
pairwise inputs bits are unequal. So this condition is satisfied when the
summation of these bits are equal to $2^{S}-1$. Hence, the probability of
propagation for two inputs is depicted as follows:

$Pr(P_{2})=P_{Z}(2^{S}-1,S)$ (14)

Where $P_{Z}$ represents the PMF of the inputs’ summation, the Eq. 5 is used
to calculate $P_{Z}$ when the inputs are uniformly distributed. Consequently,
the probability of carry propagation for the first segment consisting of $S$
bits is given by Eq.15

$Pr(P_{2})=\frac{1}{2^{S}}$ (15)

Probability of carry-out generation of a second segment consisting of $H-S$
bits can be formulated as follows:

$\begin{split}&Pr(G_{1})=Pr(X+Y>2^{H-S}-1)\\\
&=Pr(Z>2^{H-S}-1)=P_{Z}(K>2^{H-S}-1,H-S)\end{split}$ (16)

The probability of carry generation of the first segment is calculated by Eq.
17.

$Pr(G_{1})=\sum_{j=2^{H-S}}^{2^{H-S+1}-2}P_{Z}(j,H-S)$ (17)

By substituting the Eqs. 15 and 17 in the Eq. 13, the PMF of error value of
truncated carry for the approximate block is obtained by Eq. 18.

$\begin{split}&Pr_{EV\\_truncate}=\\\
&\begin{cases}(\sum_{j=2^{H-S}}^{2^{H-S+1}-2}P_{Z}(j,H-S)).(\frac{1}{2^{S}})&\text{$x=2^{H}$}\\\
1-(\sum_{j=2^{H-S}}^{2^{H-S+1}-2}P_{Z}(j,H-S)).(\frac{1}{2^{S}})&\text{$x=0$}\\\
\end{cases}\end{split}$ (18)

###  II-D Approximate block’s PMF Evaluation

In each block, the PMF of error value is expressed by union of the source of
the error event. In the proposed adder, $Pr_{EV\\_OR}$ and
$Pr_{EV\\_carry\\_truncated}$ are the source of errors, hence the error value
of approximate block ($EV_{AppBlock}$) is shown by Eq. 19.

$EV_{App\,Block}=EV_{OR\,Gate}+EV_{Carry\,Truncated}$ (19)

Assuming that the length of OR gates replaced with FAs is $L$ bits, the carry
chain’s length is $S$ bits. The PMF of error value in the approximate block
falls into three cases shown in TABLEI. To obtain the error value in these
three cases, the corresponding ranges in TABLEI should be considered.

Table I: Error value ranges based on different cases

Case Carry chain truncated and OR gates position Error value ranges First
$H-S>L$ $0<error\leq 2^{L}-1$ $error=2^{H}-1$
$2^{H}-1<error\leq(2^{H}-1)+(2^{L}-1)$ Second $H-S=L$ $0<error\leq 2^{L}-1$
Third $H-S<L$ $0<error\leq 2^{L}-1$ $error=2^{L}-X-2^{H},2^{H-S}\leq X\leq
2^{L}-1$

In the following, the PMF of an approximate block error value calculation for
three cases will be explained. In the first case, ($H-S>L$), the length of
truncated carry is greater than the replaced OR gates. In this case, the
approximate block configuration is shown in figure 10.

Figure 10: Truncated carry’s bits greater than OR gates replaced bits

The value of error in the first case is driven by the replacement of OR gates
and the truncated carry. The replacement of OR gates cause error values
between $0$ to $2^{L}-1$, and the truncated carry induce error value equal to
$2^{H}-1$. Hence, the total error value of approximate block ranges from $0$
to $2^{L}-1$ and from $2^{H}-1$ to $(2^{H}-1)+(2^{L}-1)$. We use three stages
to calculate the probability of error value in the approximate block in this
stage, and hence describing these stages in the following paragraphs.

In the first stage, the probability of error value for the value of $2^{H}-1$
is calculated by Eq. 20.

$Pr_{EVAppB}(2^{H}-1)=Pr_{SSBCO}.Pr_{EV\\_OR}(EV=0)$ (20)

$Pr_{EVAppB}$ stands for probability of approximate block. As the assumption
of $H-S>L$ is valid; the approximate block is split into two sub-blocks. The
first sub-block has $L$ bits length, whereas the second sub-block has $H-L$
bits length. $Pr_{EV\\_OR}(EV=0)$ is the probability of error-free in the
first sub-block, which is obtained by Eq. 10, when $x=0$. The $Pr_{SSBCO}$ is
the probability of carry-out generation by second sub-block which is
calculated by Eq. 18.
In the next stage, the probability of error value for the range $EV>2^{H-1}$
is calculated as follow:

$Pr_{EVAppB}(EV>2^{H}-1)=Pr_{SSBCO}.SoP$ (21)

Where $Pr_{SSBCO}$ is computed in the same manner as the prior stage and $SpO$
is summation of probability of error value of replaced OR gates is evaluated
by Eq.22.

$SpO=\sum_{i=1}^{L}Pr_{EV\\_OR}$ (22)

Where $Pr_{EV\\_OR}$ is the probability of error value in the first sub-block,
and $Pr_{SSBCO}$ is computed in the same manner as the prior stage.

In the third stage, the probability of error value for values between $0$ to
$2^{L}-1$ is calculated by Eq. 23

$Pr_{EVAppB}(0<EV<2^{L}-1)=(1-Pr_{SSBCO}).SpO$ (23)

In the second case, ($H-S=L$ bits), the length of truncated carry is equal to
the replaced OR gates. The approximate block configuration, in this case, is
shown in figure 11. the error value ranges in this case is from $0$ to
$2^{L}-1$, where the probability of error value is calculated by Eq. 23. In
this case, $Pr_{SSBCO}$ is equal to zero. Thus, the probability of error is
equal to the probability of the error value of the replaced OR gates.

Figure 11: Truncated carry’s bits equal to OR gates replaced bits

In the last case, ($H-S<L$), the length of the truncated carry chain is
smaller than the replaced OR gates. The approximate block configuration, in
this case, is indicated in figure 12.

Figure 12: Truncated carry’s bits smaller than OR gates replaced bits

The error value in this case has two ranges, from $0$ to $2^{L}-1$ and
$(2^{L}-X)-2^{H}$ where $2^{H-S}\leq X\leq 2^{L}-1$. The corresponding values
in the first range (from $0$ to $2^{L}-1$) are divided into $0$ to $2^{H-S}-1$
and $2^{H-S}$ to $2^{L}-1$. The probability of error values for $0$ to
$2^{H-S}-1$ is equal to the probability of replaced OR gates in the
corresponding values. The probability of error value for values $2^{H-S}$ to
$2^{L}-1$ ($2^{H-S}\leq EV\leq 2^{L}-1$) is similar to the first case by
dividing the approximate block into two sub-blocks, and the probability of
error value for corresponding values is calculated as in Eq. 24

$\begin{array}[]{ll}&Pr_{EV\,Approximate\,Block}(x)=\\\
&\begin{cases}(1-Pr_{PSSB}).(SpO-\frac{1}{2^{H}})+\frac{1}{2^{H}}\hskip
8.53581ptx=2^{H-S},\\\ \hskip 128.0374pt2^{H-S+1},...,2^{L-2}\\\
(1-Pr_{PSSB}).SpO\hskip 14.22636ptOtherwise\\\ \end{cases}\end{array}$ (24)

Where $Pr_{PSSB}$ and $SpO$ are probability of propagate carry with second
sub-block and summation of probability of error value of replaced OR gates
evaluated by Eq.22, respectively. This occurs when the sum of inputs is equal
to $2^{H-L}-1$.

The probability of error value in range $(2^{L}-X)-2^{H}$ is evaluated by Eq.
25. Where $2^{H-S}\leq X\leq 2^{L}-1$ is expressed as follow:

$Pr_{EVAppB}((2^{L}-X)-2^{N})=Pr_{PSSB}.Pr_{EVLC}(X)$ (25)

Where $Pr_{EVLC}$ is probability of error value in last case which is
evaluated by Eq.26.

$\begin{array}[]{ll}Pr_{EVLC}(X)=\\\ \begin{cases}(SpO-\frac{1}{2^{H}})\hskip
14.22636ptX=2^{H-S},2^{H-S+1},...,2^{L-2}\\\ SpO\hskip 48.36967ptOtherwise\\\
\end{cases}\end{array}$ (26)

$SpO$ evaluates by Eq.22. To better describe this proposed analysis, an
example is considered on a 4-bit approximate block. OR gates embed two LSBs,
and the length of the carry chain is two bits, i.e., figure 5. The PMF of the
approximate block error value is evaluated using Eqs.20,21. So the PMF of the
error value of the approximate block is equal to:

$Pr_{EV\,App\,Block}(x)=\begin{cases}\frac{4}{512}&\text{$x=19$}\\\
\frac{12}{512}&\text{$x=17,18$}\\\ \frac{36}{512}&\text{$x=16$}\\\
\frac{28}{512}&\text{$x=3$}\\\ \frac{84}{512}&\text{$x=1,2$}\\\
\frac{252}{512}&\text{$x=0$}\\\ \end{cases}$ (27)

###  II-E Evaluation of Approximate block Error Rate

As described in the sectionII-C, two events, i.e., replaced OR gate and
truncated carry, lead to erroneous blocks. The approximate block error rate
will be evaluated by the union of these events. The error rate is calculated
using the inclusion-exclusion principle [32] based on the Eq.28. Note that the
two events of the approximate block are not mutually exclusive.

$\begin{split}&Pr(ER)=Pr(Event1\cup Event2)=Pr(Event1)+\\\
&Pr(Event2)-Pr(Event1\cap Event2)\end{split}$ (28)

The first event ($Event1$) and the second event ($Event2$) represent the OR
gates replaced and the carry truncated, respectively. The probability of the
first event is calculated by the summation of overall values of the PMF of the
replaced OR gates’ error values, which is calculated by Eq.10. Hence, the
probability of the first event ($Pr(Event1)$) is given as follows:

$Pr(Event1)=\sum_{x=1}^{x=2^{L}-1}Pr_{EV\\_OR}(x)$ (29)

The probability of the second event ($Pr(Event2)$) is calculated by the
summation over all the PMF of carry truncated error values. Hence, the
probability of the second event ($Pr(Event2)$) is calculated as follows:

$Pr(Event2)=\sum_{x=1}^{x=2^{H}}Pr_{EV\\_carry\\_truncated}(x)$ (30)

In order to calculate the probability of the union of error in two events,
according to Eq.28, we need to calculate the probability of the intersection
of events. To compute the probability of events intersection ($Pr(Event1\cap
Event2)$), we consider three different cases as in sub-section II-D based on
$H-S$ and $L$ values. In the first case, $H-S>L$, $H$ bits approximate block
are split into two sub-blocks, The first sub-block has $L$ bits and the second
one has $L-S$ bits. The probability of intersection of these two events, in
this case, is given as follows:

$\begin{split}&Pr(Event1\cap Event2)=Pr_{SSB}(G).Pr(Event1)\\\
&+(Pr_{FSB}(G).Pr_{SSB}(Propagate))\end{split}$ (31)

The $Pr_{FSB}(G)$ and $Pr_{SSB}(G)$ are the probabilities of generation carry-
out by the first sub-block and the second sub-block, respectively. These are
calculated by considering the bit length of the sub-block in Eq.16. The
$Pr_{SSB}(Propagate)$ is the probability of carry propagation by the second
sub-block, which is calculated by Eq.14. In other cases, $H-S=L$ and $H-S<L$,
the intersection of two events is calculated similarly to the first case.
However, in Eq.31, the probability of the generation carry-out by the second
sub-block is equal to zero ($Pr_{second\,sub\,block}(G)=0$). Consequently, the
probability of the intersection of two events in both cases is obtained as
$Pr(Event1\cup Event2)=Pr(Event1)$.

###  II-F Evaluation of the PMF of Heterogeneous BBA

The heterogeneous BBA with $N$ bits is divided into $K$ blocks with $H$-bits
length. $I$ blocks are heterogeneous approximate blocks, and the rest are
accurate blocks. The source of erroneous output is an error in the associated
approximate block, and the blocks’ errors are independent. Hence, the PMF of
error value across the Heterogeneous BBA is calculated by the convolution of
PMFs of error values in each heterogeneous approximate block. The PMF of error
value of approximate adder ($Pr_{EV\\_A}$) is given as follows:

$Pr_{EV\\_A}=Pr_{EVAppB_{1}}\circledast
Pr_{EVAppB_{2}}\circledast...\circledast Pr_{EVAppB_{I}}$ (32)

Where $Pr_{EVAppB_{I}}$ is PMF of error value of $i^{th}$ approximate block.
Beside the PMF of error value, the error rate (ER) in approximate adder with
the same structure discussed above is acquired by the union of the error rate
in all blocks. Henceforth, the probability of the union of such blocks can be
obtained using the inclusion-exclusion principle [32] as in Eq. 33.

$\begin{split}&Pr_{ER\\_A}=Pr[ERB_{1}\cup ERB_{2}\cup....\cup ERB_{K}]=\\\
&\sum_{i=1}^{K}Pr[ERB_{i}]-\sum_{1\leq i<j\leq K}Pr[ERB_{i}\cap ERB_{j}]\\\
&+\sum_{1\leq i<j<l\leq K}Pr[ERB_{i}\cap ERB_{j}\cap ERB_{l}]\\\
&+...+(-1)^{K}Pr[\cap_{i=1}^{K}ERB_{i}]\end{split}$ (33)

Where $Pr_{ER\\_A}$ and $Pr[ERB_{i}]$ are error rate of approximate adder and
the error rate of $i^{th}$ block, discussed in sub-section II-E, respectively.
The error in each block happens independently; so, the probability of error
rate for each block is also independent. The intersection of the error rate of
blocks is simplified into the multiplication of them. So the error rate in
approximate adder is calculated by Eq.34.

$\begin{split}&Pr_{ER\\_A}=\sum_{i=1}^{K}Pr[ERB_{i}]-\sum_{1\leq i<j\leq
K}Pr[ERB_{i}].Pr[ERB_{j}]\\\ &+\sum_{1\leq i<j<l\leq
K}Pr[ERB_{i}].Pr[ERB_{j}].Pr[ERB_{l}]\\\
&+...+(-1)^{K}\prod_{i=1}^{K}Pr[ERB_{i}]\end{split}$ (34)

###  II-G Evaluation of Heterogeneous BBA’s MED

Besides PMF and ER, mean error distance (MED) is considered as a criterion to
compare the adders. MED is calculated by the average value of all error
distance. Hence, it contains the information of ED and ER, and it uses as
common performance parameters in approximate computing. Statistically, it is
calculated by Eq. 35.

$MED=E[ED]=\sum_{i=-\infty}^{\infty}|i|PMF(i)$ (35)

Where $PMF$ is the PMF of Heterogeneous BBA, and $i$ is the value of each
error in Heterogeneous BBA.

##  III Select Optimal configuration

In real error-resilient applications, given an acceptable accuracy level,
which is identified by ED, ER, or MED, must be satisfied. In order to reach an
acceptable accuracy level, the associated optimal configuration should be
designed. The minimal area, delay and power are the main elements identified
as hardware metrics in the optimal configuration. The optimal configuration
selection is modelled as an optimisation problem, including the set of
constraints and objective function. We evaluate ER, ED and MED as the
acceptable accuracy level. These metrics are entered as constraints, and the
hardware metrics are considered as an objective function. We use the
estimation method proposed in [28] to formulate the hardware metrics in
heterogeneous BBA. The detailed of estimation method for hardware metrics is
explained in the following sub-sections.

###  III-A Hardware Metrics Estimation Method

Common architecture is used for speculative adders composes of three parts as
PG part, carry part and sum part. PG part generates propagation and generation
signal. Detailed explanations are presented in [28] and in the textbook [33].
Various abstraction levels of digital design, from the highest behavioural
level to the lowest device level, can be considered to estimate the the design
metrics. In this work, we perform gate-level to estimate the hardware metrics.
We consider 2 inputs gates e.g., AND, OR, NAND and NOR as the basic gates. The
other gates, like XOR and XNOR, are expressed by the basic gates. We neglect
Inverter gates in the delay and area estimation. The circuit is modelled by
2-input gates, and gate-level depth and gate count are used, respectively, to
estimate delay and area. In our estimation model, the XOR gate is constructed
from three 2-input gates such as two 2-input AND and one 2-input OR. Thus, the
gate level depth and gate count of the XOR gate are 2 and 3, respectively.
Gate level implementation for the proposed adder is shown in figure13, where
we can evaluate the gate level depth and gate count.

Figure 13: Gate level speculative adder

####  III-A1 Delay

The proposed adder architecture has shown in figure 13 consists of 3 parts. We
evaluate gate-level depth for each block in the BBA independently. In the PG
part and sum part, the XOR gate is crucial in gate level depth and therefore,
gate-level depth is equal to 2 for both parts. The carry part’s gate-level
depth is dependent on the position of carry truncation and the number of bits
that OR gates are replaced. If the carry truncated position ($H-S$) for $H$
bits block is greater than the OR gates replaced ($L$), the gate level depth
for this part will be $2(H-S-L)$. Thus, the gate level depth for the
approximate block is equal to the summation of the gate-level depth of the PG
part, sum part and carry part. Consequently, Delay for the approximate block
with $H$ bits are given as follows:

$D_{AppB}=\begin{cases}0&\text{$S=0$}\\\ 2C_{d}(S+1)&\text{$H-S<=L$}\\\
2C_{d}(H-S-L)&\text{$H-S>L$}\\\ \end{cases}$ (36)

Where $AppB$, $S$ and $L$ are approximate block, carry chain length and OR
gates replacement, respectively. $C_{d}$ is a constant factor of delay, which
is derived from technology. Besides, delay for an accurate block with $H$ bits
length is evaluated as same as approximate block even though the gate level
depth of carry block is $2(H-1)$. Thus the delay for the accurate block is
estimated by Eq.37.

$D_{Accurate}=2C_{d}(H+1)$ (37)

The estimation of $N$ bits adder delay, which is consisted $AC$ accurate block
and $AP$ approximate block, is obtained by the summation of delay of $AC$
accurate block ($D_{Accurate}$) and the delay of $AP$ approximate block
($D_{Approximate}(AP)$). Consequently, the estimation delay for heterogeneous
BBA is given as follows:

$D=AC.(D_{Accurate})+AP.(D_{Approximate})$ (38)

####  III-A2 Area

The estimate of the area in the proposed adder architecture, which has an
accurate and approximate block, is calculated based on gate count. The
accurate and approximate block consisted of the above three parts.
Accordingly, in the accurate block, the PG part has a $4H$ gate count, the sum
part has $3H+2$ gate count, and the carry part has $2(S-1)$ gate count.

$A_{Accurate}=9H$ (39)

The gate count of each part in approximate block is calculated as follows:

Table II: Approximate block’s gate count

Parts Gate count PG part $Area_{PG}=\begin{cases}4H-3L&\text{$H-S>L$}\\\
4S+L&\text{$Otherwise$}\\\ \end{cases}$ Sum part
$Area_{Sum}=\begin{cases}3(H-L)&\text{$S=0$}\\\ 3(H-L)+2&\text{$Otherwise$}\\\
\end{cases}$ Carry part $Area_{Carry}=\begin{cases}0&\text{$S=0$}\\\
2(S-1)&\text{$H-S<=L$}\\\ 2(H-L-1)&\text{$H-S>L$}\\\ \end{cases}$
$A_{Approximate}$ $Area_{PG}+Area_{sum}+Area_{Carry}$

Where $H$ refer to the bit-width of the approximate block, $L$ and $H-S$ is
the number of bits replaced by OR gates and truncated carry, respectively. The
area estimation for $N$-bits adder are equivalent to the total sum of the area
of the accurate blocks and the approximate blocks. The estimation of area for
heterogeneous BBA is calculated in Eq.40.

$A=C_{a}(AC.(A_{Accurate})+\sum_{i=1}^{AP}A_{Approximate}(i))$ (40)

Where $AC$ and $AP$ is the number of accurate blocks and approximate block,
respectively. $C_{a}$ is a constant factor for the area which depends on
design technology.

####  III-A3 Power

Power consumption in a digital circuit is estimated based on the following two
components:

  * •

Dynamic power consumption: The dynamic power consumption is directly
proportional to its area a delay if the clock frequency is assumed to be fixed
[28]. The dynamic power consumption ($P_{d}$) at a fixed clock frequency for
heterogeneous BBA architecture estimate by Eq. 41.

$P_{d}\mathrel{\raisebox{3.01385pt}{\mbox{$\underset{\vbox{\hbox{$\sim$}}}{\vbox{\hbox{$\propto$}}}$}}}(area.delay)\Rightarrow
P_{d}=C_{pd}(A.D)$ (41)

Where $C_{pd}$ is a constant factor of dynamic power derived from design
technology.

  * •

Static power consumption: According to [28] the static power consumption of a
digital circuit is related to its area. Due to the direct proportional of the
area to the static power consumption ($P_{s}$), the static power consumption
is calculated by Eq.42 for our proposed adder.

$P_{s}\mathrel{\raisebox{3.01385pt}{\mbox{$\underset{\vbox{\hbox{$\sim$}}}{\vbox{\hbox{$\propto$}}}$}}}area\Rightarrow
P_{s}=C_{Ps}(A)$ (42)

Where $C_{Ps}$ is a constant factor of static power which is derived from the
technology of design.

As a result, the total power consumption can be estimated by the sum of
dynamic and static power consumption.

$P=P_{s}+P_{d}$ (43)

Constant factors of delay, area and power are obtained using _Synopsys Hspice
circuit simulator_ with 32 $nm$ technology design. Total consumption power
obtains from the summation of dynamic and static power; therefore, the
constant factor of power is evaluated by summation of those constant factors
($C_{p}=C_{Pd}+C_{Ps}$). Based on [28] these constant factors of which is
derived from 32 $nm$ design technology are demonstrated in Table III

Table III: Constant Factor of 32 $nm$ technology

Constant Factor Value $C_{d}$ 12.14 $ps$ $C_{a}$ 0.70 $\mu m^{2}$ $C_{p}$ 9.24
$\mu W$

##  IV Result

We compare our proposed heterogeneous BBA with recent approximate adder
designs in literature, based on the following aspects:

  * •

Accuracy metrics

  * •

Hardware metrics

  * •

Trade-off between accuracy constraint and hardware metrics

In the following, we describe this aspect and comparison of a proposed adder
with some recent adder.

###  IV-A Accuracy Metrics Aspect

The accuracy of the proposed adder is compared with the five latest cutting
edge approximate adders. These adders are HABA, [34], GeAr [21], RAP-CLA [24],
simple Yet efficient accuracy-configurable adder (SARA) [25] and block-based
carry speculative approximate adder (BCSA) [2]. The error metrics are obtained
using Monte Carlo simulation.

In this study, the error metrics which are used for the comparison of the
proposed adder are Mean Error Distance (MED, mean of all possible EDs),
Normalized Mean Error Distance (NMED, the normalization of MED by the maximum
output), Error Rate (ER) and Mean Relative Error Distance (MRED)[2]. ER and
MED are described above, and NMED and MRED for $n$-bit adder are acquired by:

$NMED=\frac{1}{2^{n}}\sum_{i=1}^{N}MED$ (44)
$MRED=\frac{1}{N}\sum_{i=1}^{N}\frac{|S_{i}-S^{\prime}_{i}|}{S_{i}}$ (45)

Where $S_{i}$ and $S^{\prime}_{i}$ represent the total sum of the accurate
adder and the approximate adder, respectively. Besides, $N$ shows the number
of samples, which is used in the Monte Carlo simulation.

We implement our proposed adder in python for calculating the above error
metrics to compare with other proposed adders. The accuracy of the proposed
adder under the different size of the block and various input bit length is
shown in figure 14.

$0$$20$$40$$60$$80$$100$$120$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$12.42$$12.41$$30.06$$15.54$$14.43$$18.73$$27.47$$57.81$$1.37$$1.36$$5.47$$2.34$$5.46$$0$$5.46$$43.75$$0$$0$$0$$0$$0$$0$$0$$0$8-bit
adderBlock Size-2Block Size-4Block Size-8 (a)

$0$$100$$200$$300$$400$$500$$600$$700$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$607$$151$$605$$606$$379$$167$$395$$87.89$$137$$9$$68$$137$$68$$0$$34$$29.3$$0$$0$$0$$0$$0$$0$$0$$0$8-bit
adderBlock Size-2Block Size-4Block Size-8 (b)

$0$$100$$200$$300$$400$$500$$600$$700$$800$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$621$$155$$707$$646$$484$$185$$428$$118.47$$136$$9$$93$$147$$93$$0$$52$$40.08$$0$$0$$0$$0$$0$$0$$0$$0$8-bit
adderBlock Size-2Block Size-4Block Size-8 (c)

$0$$20$$40$$60$$80$$100$$120$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$33.77$$33.77$$61.77$$36.45$$35.05$$47.86$$60.98$$86.64$$4.29$$4.28$$16.72$$8.54$$16.75$$5.89$$21.15$$80.23$$0.1$$0.1$$0.68$$0.34$$6.09$$0$$6.2$$68.37$16-bit
adder (d)

$0$$100$$200$$300$$400$$500$$600$$700$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$608$$154$$625$$626$$417$$172$$417$$6.44$$155$$10$$156$$129$$83$$20$$56$$2.86$$10$$4\cdot
10^{-2}$$10$$10$$5$$0$$2$$0.57$16-bit adder (e)

$0$$100$$200$$300$$400$$500$$600$$700$$800$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$623$$157$$730$$670$$531$$190$$554$$8.88$$157$$10$$190$$154$$112$$26$$81$$3.96$$10$$4\cdot
10^{-2}$$12$$11$$7$$0$$3$$0.79$16-bit adder (f)

$0$$20$$40$$60$$80$$100$$120$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$51.23$$51.21$$65.37$$55.71$$65.44$$74.66$$87.62$$98.66$$9.18$$9.17$$32.18$$17.17$$35.88$$16.66$$45.94$$97.56$$0.29$$0.29$$2.25$$1.12$$17.45$$0.39$$18.04$$94.68$ER(%)32-bit
adder (g)

$0$$100$$200$$300$$400$$500$$600$$700$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$625$$156$$625$$625$$563$$172$$417$$2.54\cdot
10^{-2}$$156$$10$$156$$130$$83$$20$$55$$1.14\cdot 10^{-2}$$10$$4\cdot
10^{-2}$$10$$10$$5$$0.1$$3$$2.52\cdot 10^{-3}$NMED32-bit adder (h)

$0$$100$$200$$300$$400$$500$$600$$700$$800$HABAHABAERUGeArRAP-
CLASARABCSAERUBCSAHBBA$644$$161$$730$$670$$589$$189$$554$$3.53\cdot
10^{-2}$$158$$10$$190$$154$$112$$26$$81$$1.59\cdot 10^{-2}$$10$$4\cdot
10^{-2}$$12$$11$$7$$7\cdot 10^{-2}$$4$$3.5\cdot 10^{-3}$MRED32-bit adder (i)

Figure 14: Compare Accuracy of Proposed Approximate Adder with State-of-the-
Art Approximate Adders

Hence, the error metrics are obtained using Monte Carlo simulation with 10
million samples with a uniform random number for 16 and 32 bits adders, though
for 8 bits adders using $2^{16}$ input combination in exhaustive simulation.
The adder is divided into half heterogeneous approximate block and half
accurate block. The heterogeneous approximate block is divided into two sub-
groups. The carry is truncated, and half of the LSBs are replaced with OR
gates in the first sub-group, whereas the length of carry chain is half of
MSBs and half of LSBs are replaced with OR gates in the second sub-group.

The error metrics such as NMED and MRED are the lowest in the proposed adders.
In comparison with BCSA, which has the lowest NMED and MRED among the other
adders, we manage to reach, on average, 2 times lower in 8-bits adder, and 28
times and 7400 times lower in 16-bits and 32-bits, respectively. The MRED and
NMED values are decreasing by increasing the size of the adder. In the
proposed adder, every increment in block size causes a 3 times reduction in
MRED and NMED. Similarly to the block size, by increasing the size of an
adder, the accuracy increases; for example, the 16-bits adder has about 15
times NMED and MRED smaller than 32 bits adders. However, the result indicated
that the error rate is the highest in the proposed adder due to the OR gates
replacement. In comparison with HABA, which has the lowest ER among the other
adders, our adder’s ER has about 3 times higher ER for 2-bit blocks size. The
ER increases to 20 times and 300 times higher than HABA for 4 bits and 8 bits
blocks size, respectively.

In order to validate the proposed analytical model of the heterogeneous
approximate adder, we compared the analytical analysis with Monte Carlo
simulation using 10 million uniform randomly inputs. We calculated error
metrics (MED and ER) using Monte Carlo simulation as a benchmark for
comparison. The MED values in the analytical model are obtained based on the
PMF of error values using Eq. (35). Moreover, the ER is calculated based on
the analytical Eq. 32. The comparison is performed for a range of Carry chain
length values ($S$) and the different number of replacement OR gates ($L$).

The figure 15 shows PMF error values in 16-bit heterogeneous BBA, where we
have 4 blocks, including 2 accurate and 2 approximate blocks. The
heterogeneous adders are shown with different values of $S$ and $L$. The PMF
shown in each sub-figure is made up of discrete impulses, which show the
probability of error values.

(a)

(b)

(c)

(d)

Figure 15: PMF of error value in 16-bit proposed adder using 4-bit sub-adder
with uniformly distributed (a) HBBA{[2,2],[0,0]} (b) HBBA{[2,1],[0,2]} (c)
HBBA{[2,2],[0,2]} (d) HBBA{[2,1],[0,3]}

The comparison of MED explained above and the error rate is reported in the
tableIV. The deviation is calculated as a percentage of the difference between
simulation and analysis results. The deviation values represent the marginal
difference between the simulation and analysis values of the heterogeneous
approximate adder.

Table IV: MED Comparison of Simulation and Analysis

Adders type Error metrics Simulation Analysis HBBA{[2,2],[0,0]} MED 114.764395
114.75 HBBA{[2,2],[0,0]} error_rate 0.876526 0.876403809 HBBA{[2,2],[0,1]} MED
50.652665 50.75 HBBA{[2,2],[0,1]} error_rate 0.826809 0.826965332
HBBA{[2,2],[0,2]} MED 18.757755 18.75 HBBA{[2,2],[0,2]} error_rate 0.802274
0.802246094 HBBA{[2,2],[0,3]} MED 29.394021 29.42 HBBA{[2,2],[0,3]} error_rate
0.802088 0.802246094 HBBA{[2,1],[0,2]} MED 26.815995 26.75 HBBA{[2,1],[0,2]}
error_rate 0.752998 0.747314453 HBBA{[2,1][0,3]} MED 10.755323 10.75
HBBA{[2,1],[0,3]} error_rate 0.736438 0.736328125 HBBA{[1,1][0,3]} MED
11.254259 11.25 HBBA{[1,1],[0,3]} error_rate 0.683849 0.68359375

###  IV-B Hardware Metrics Aspect

Verilog HDL is applied to describe our proposed adder and other adders
mentioned in SectionIV-A. The case study is a 32-bit adder with 4 bits sub-
block and synthesized by Synopsys Design Compiler. These studies are
synthesised using nangate $15nm$ FinFET Open Cell Library with $0.8V$
operating voltage level and at a temperature of $25^{o}C$. The hardware
metrics considered as a basis for the adders’ comparison are delay, area,
power and energy. The result of these metrics for 32-bit adder that includes 8
4-bit sub-adder with configuration of HBBA{[4,4,4,2],[0,0,0,2]} is reported in
the tableV. To obtain the adders’ power and energy, we injected 10 million
random inputs into the netlist of synthesized adders to evaluate the internal
activity nodes. We stored them in a VCD format file by ModelSim tool. In
addition, the power is extracted based on the VCD file by using Synopsys
PrimeTime. Delay and area are determined by Synopsys Design Compiler as well.

Table V: Hardware metrics of 32 bits adder consist of 4 bits sub block

Adder Delay (pS) Area ($\mu m2$) Power ($\mu W$) Energy (aJ) CLA 99.44 89.8
58.22 5789 HABAERU 88.3 66.47 51.49 4547 GeAr 48.45 80.61 42.91 2079 RAP-CLA
44.84 65.66 41.8 1874 HBBA 61.87 55.984 25.93 1604

As the table indicates, the delay of the heterogeneous proposed adder is
higher from RAP-CLA and GeAr. However, in area and power, we have the lowest
value among the other adders. The proposed adder has about $38\%$ higher
delay, but $18\%$ and $62\%$ improved in area and power compared to RAP-CLA.
Moreover, the proposed adder has the lowest energy among the other adders.
Comparing to RAP-CLA, the energy of the proposed adder improve about $17\%$.

###  IV-C The trade-off between error and hardware metrics aspect

Design metrics such as hardware and accuracy vary in different applications,
and they depend on $L$ and $S$ in $N$-bits adder. Depending on the
application, we need to perform a trade-off between accuracy identified by MED
or ER and the hardware metrics such as area, delay and power. The optimal
configuration can be modelled as an optimisation framework, including minimum
hardware metrics as an objective function for a given accuracy level, where
accuracy (MED) is modelled as a hard constraint.

The MED is measured by Eq. 35 and delay, area and power are assessed by
Eqs.38, 40 and 43, respectively. Therefore, the designer can find optimal
configuration subjected to specific MED for a given $N$-bit adder based on
optimising framework. The optimal configuration is the value of $L$ and $S$ in
a various number of the approximate block, which is used in $N$-bit adder.

(a) delay

(b) delay

(c) area

(d) power

Figure 16: Optimal configuration for delay, area and power

Figure 16 is shown the design point configurations for 16-bit adder consisting
of 4 blocks with 4 bits length for each possible value of $L$ and $S$. It can
be observed the optimal configuration provide minimal delay, area and power
for each given MED. Figures 16a, 16c and 16d compare the delay, area and power
vs MED design space of LOA with HBBA. It can be observed the optimal HBBA
provide the best possible configuration. Note that in figure 16 the efficient
architecture can be selected from design spaces by considering MED and
priority of delay, area or power for the desired application.

##  V Conclusion

In this paper, we propose the heterogeneous block-based approximate adder
design. It consists of the non-overlap block, which can be an accurate block
or approximate block. The approximate block generates an error which is
consisted the inexact logic configuration and truncation carry chain. The
probability of error analysis for HBBA is presented. The model can be applied
to the different configuration of the proposed adder to evaluate the
occurrence of error and the PMF of error value without the need for the Monte-
Carlo simulation. The analytical model can provide useful error metrics to
compare the various configuration of the approximate adder. We observed
various configuration with the same accuracy. Therefore, in order to find the
optimal configuration, we use the estimation model for hardware metrics such
as delay, area and power. The designer can find the best optimal configuration
by noticing the application’s desire accuracy based on the analytical model
and estimation model as the optimiser framework.

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|  Ebrahim Farahmand (S’20) is a Ph.D. student at the Department of Electrical
Engineering, Shahid Bahonar University of Kerman (SBUK), Iran. He received the
B.Sc. degree in Electrical Engineering- Communication systems in 2012 and the
M.Sc. degree in Electrical Engineering-Electronics in 2016, both from Shahid
Bahonar University of Kerman (SBUK). From 2016 to 2017, he worked as a
Research Associate in the Reliable and Smart System (RSS) lab, SBUK, Iran. His
research interests include brain-inspired computing, approximate computing,
machine learning accelerator, Fault-tolerant design and Network systems.
---|---
|  Ali Mahani received the B.Sc. degree in electronic engineering from Shahid
Bahonar University of Kerman, Iran, in 2001, The M.Sc. and Ph.D. degrees both
in Electronic Engineering from Iran University of Science and Technology
(IUST), Tehran, Iran, in 2003 and 2009 respectively. Since then he has been
with the electrical engineering department of Shahid Bahonar University of
Kerman, where he is currently an associate professor. His research interests
focus on Fault-tolerant design, FPGA-based accelerators, approximate digital
circuits, stochastic computing and Networked System.
---|---
|  Muhammad Abdullah Hanif is a Ph.D. student at the Faculty of Informatics,
Technische Universität Wien (TU Wien), Vienna, Austria. In the past, he has
worked as a Research Associate in Vision Processing (VISpro) lab, Information
Technology University (ITU), Pakistan, and as a Lab Engineer in Ghulam Ishaq
Khan Institute of Engineering Sciences and Technology (GIKI), Pakistan. He
currently holds a Master of Science degree in Electrical Engineering from the
School of Electrical Engineering and Computer Science (SEECS), National
University of Sciences and Technology (NUST), Islamabad, Pakistan, and a
Bachelor of Science degree in Electronic Engineering from GIKI, Pakistan. His
research interests include brain-inspired computing, machine learning,
approximate computing, computer architecture, energy-efficient design, robust
computing, system-on-chip design, and emerging technologies.
---|---
|  Muhammad Shafique received his Ph.D. in computer science from the Karlsruhe
Institute of Technology (KIT), Germany, in 2011. From Oct.2016 to Aug.2020, he
was a full professor at the Institute of Computer Engineering, Faculty of
Informatics, TU Wien, Vienna, Austria. Since Sep.2020, he is with the Division
of Engineering, New York University Abu Dhabi (NYU-AD), United Arab Emirates,
and is a Global Network faculty at the NYU Tandon School of Engineering, USA.
His research interests are in system level design for brain-inspired
computing, AI & machine learning hardware, wearables, autonomous systems,
energy-efficient and robust computing, with applications in Internet-of-Things
and smart Cyber-Physical Systems. Dr. Shafique has given several Keynotes,
Invited Talks, and Tutorials, as well as organized many special sessions at
premier venues. He has served as the PC Chair, General Chair, Track Chair, and
PC member for several prestigious IEEE/ACM conferences. He received the 2015
ACM/SIGDA Outstanding New Faculty Award, AI 2000 Chip Technology Most
Influential Scholar Award in 2020, six gold medals, and several best paper
awards and nominations at prestigious conferences.
---|---