# Sign inversion in the lateral van der Waals force

Edson C. M. Nogueira<EMAIL_ADDRESS>Faculdade de Física,
Universidade Federal do Pará, 66075-110, Belém, Pará, Brazil  Lucas Queiroz
<EMAIL_ADDRESS>Faculdade de Física, Universidade Federal do Pará,
66075-110, Belém, Pará, Brazil  Danilo T. Alves<EMAIL_ADDRESS>Faculdade de
Física, Universidade Federal do Pará, 66075-110, Belém, Pará, Brazil  Centro
de Física, Universidade do Minho, P-4710-057, Braga, Portugal

(August 28, 2024)

###### Abstract

We consider a single slight protuberance in a perfectly conducting plane, and
investigate the van der Waals (vdW) interaction between this surface and a
neutral polarizable particle. When the protuberance is sufficiently smooth, so
that the proximity force approximation (PFA) is well applicable, for a fixed
distance of the particle from the plane, the lateral vdW force always points
to the protuberance. On the other hand, by making calculations valid beyond
the PFA, we show that nontrivial geometric effects arise when we consider an
anisotropic particle, and manipulate the ratio between the characteristic
widths of the protuberance and the fixed particle-plane distance. We predict
that, as this ratio decreases, a sign inversion in the lateral vdW force can
occur, in the sense that, instead of pointing to the protuberance, in certain
situations the lateral force points to the opposite direction. Moreover, we
show that even when such a sign inversion in the lateral vdW force does not
occur for a single protuberance, it can arise when two or more protuberances
are put together, distinguishing between sign inversions originated by
individual or collective effects. In addition, we show that all these effects
have their classical counterparts, involving a neutral particle with a
permanent electric dipole moment. The prediction of such geometric effects on
the lateral vdW force may be relevant for a better controlling of the
interaction between a particle and a corrugated surface in classical and
quantum physics.

##  I Introduction

In 1873, van der Waals proposed an equation of state for real gases, which
included a term related to intermolecular attractive forces [1]. For the case
of two non-polar molecules, the intermolecular forces, usually called
dispersion van der Waals (vdW) forces, are due to the quantum fluctuations in
the distributions of charges and currents in these molecules, and thus, have
an electromagnetic nature [2, 3]. The influence of retardation effects,
related to the speed of light, on these dispersive forces can be derived with
the formalism of quantum electrodynamics [4, 5, 6]. As examples of dispersive
forces, one can cite the attraction between two perfectly conducting parallel
plates [7], and between a neutral polarizable particle and a conducting plane
surface [4, 5, 8], being these forces relevant in physics, chemistry, biology
and engineering [9, 10, 11], with the progress in the precision of the
experiments opening possibilities for applications of these forces in micro
and nanotechnology [12, 13, 14, 15, 16, 17]. In general, dispersive forces
depend on the boundary conditions that material bodies impose on the
electromagnetic field, by means of their material properties and geometry [18,
19, 20, 21, 22, 23, 24, 25] (also see Refs. [26, 27, 28] and references
therein). In this context, nontrivial aspects of the dispersive forces have
attracted growing interest, as, for instance, those related to the control of
the sign of the force, from an attractive to a repulsive behavior [29, 30, 6,
31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49],
existing several situations where the presence of an anisotropic particle has
a fundamental role in such a sign inversion [37, 38, 50, 42, 43].

When corrugations are considered in Casimir interactions, lateral dispersive
forces appear and nontrivial geometric effects can be predicted, whose
understanding can be important, for instance, to achieve a higher degree of
control of the interaction between nanogratings (see, for instance, Refs. [51,
52]), to possibly create micro/nanodevices which operate through the lateral
force (see, for instance, Refs. [53, 54]) or, even, to be used as probes of
the quantum vacuum (see, for instance, Ref. [55]). In the context of the
interaction between a particle and a corrugated surface, nontrivial geometric
effects can be predicted when calculations are made beyond the proximity force
approximation (PFA) [55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 42, 65, 66]. For
example, in Ref. [55], it is shown that for an isotropic particle interacting
with a grooved surface, the PFA predicts that no lateral force acts on the
particle when it is over a plateau of the surface, whereas analyses beyond
this approximation reveal the existence of a lateral force. In the present
paper, we consider a single slight protuberance in a perfectly conducting
plane, and, by making calculations valid beyond the PFA, we predict that sign
inversions and other nontrivial geometric effects related to the lateral vdW
force arise when we consider a neutral anisotropic particle, and manipulate
the ratio between the characteristic widths of the protuberance and the
distance of this particle from the plane. Moreover, we investigate situations
where the sign inversion in the lateral vdW force does not occur for a single
protuberance, but arises when two or more protuberances are put together,
distinguishing between sign inversions originated by individual or collective
effects.

The paper is organized as follows. In Sec. II, we discuss the approach to
compute the vdW interaction between a neutral particle and a general grounded
conducting corrugated surface. In Sec. III, we apply our formulas to the case
of a plane with a single Gaussian protuberance. In Sec. IV, we apply our
formulas to the case of a plane with a single rectangular strip and generalize
this situation to the case of two or more rectangular strips. In Sec. V, we
present our final remarks.

##  II Model and approach

Let us start considering an anisotropic polarizable particle characterized by
a frequency dependent polarizability tensor $\boldsymbol{\alpha}$ given by
(see, for instance, Ref. [67])
$\boldsymbol{\alpha}(\omega)=\alpha_{1}(\omega)\hat{\mathbf{e}}_{1}^{\prime}\hat{\mathbf{e}}_{1}^{\prime}+\alpha_{2}(\omega)\hat{\mathbf{e}}_{2}^{\prime}\hat{\mathbf{e}}_{2}^{\prime}+\alpha_{3}(\omega)\hat{\mathbf{e}}_{3}^{\prime}\hat{\mathbf{e}}_{3}^{\prime}$,
where $\hat{\mathbf{e}}_{1}^{\prime}$, $\hat{\mathbf{e}}_{2}^{\prime}$ and
$\hat{\mathbf{e}}_{3}^{\prime}$ are unit vectors pointing in the directions of
the principal axes of the particle (along any one of them, an applied electric
field induces a dipole moment in the same direction [68]). Denoting the Euler
angles by $(\phi,\theta,\psi)$, according to the convention usually adopted in
quantum mechanics, we have
$\hat{\mathbf{e}}_{i}=\sum_{j}R_{ij}\hat{\mathbf{e}}^{\prime}_{j}$, where
$R_{ij}$ are the elements of the Euler rotation matrix $R(\phi,\theta,\psi)$
[69, 70], $\hat{\mathbf{e}}_{1}=\hat{{\bf x}}$,
$\hat{\mathbf{e}}_{2}=\hat{{\bf y}}$, and $\hat{\mathbf{e}}_{3}=\hat{{\bf z}}$
are unit vectors related to the laboratory coordinate system $xyz$. The
particle is located at ${\bf r}_{0}={\bf r}_{0\parallel}+z_{0}\hat{{\bf z}}$
(with $z_{0}>0$ and ${\bf r}_{0\parallel}=x_{0}\hat{{\bf x}}+y_{0}\hat{{\bf
y}}$), above a grounded conducting corrugated surface described by
$z=h(\mathbf{r}_{\parallel})$, with $h({\bf r}_{||})$ describing a general
small modification $[\text{max}|h({\bf r}_{||})|=a\ll z^{\prime}]$ to a
grounded planar conducting surface at $z=0$ (see Fig. 1).

Figure 1:  Illustration of a neutral polarizable anisotropic particle,
arbitrarily oriented in space, located at ${\bf r}_{0}={\bf
r}_{0\parallel}+z_{0}\hat{{\bf z}}$ (with $z_{0}>0$), interacting with a
general grounded conducting corrugated surface, whose corrugation profile is
described by $z=h(\textbf{r}_{\parallel})$. The unit vectors
$\hat{\mathbf{e}}_{1}^{\prime}$, $\hat{\mathbf{e}}_{2}^{\prime}$ and
$\hat{\mathbf{e}}_{3}^{\prime}$ are those pointing to the directions of the
principal axes of the particle, in whose directions the particle presents the
polarizabilities $\alpha_{1}(\omega)$, $\alpha_{2}(\omega)$, and
$\alpha_{3}(\omega)$, respectively.

To investigate the vdW interaction energy $U_{\text{vdW}}$ between the
particle and the corrugated surface, we take as basis the analytical
perturbative approach presented by us in Ref. [65], according to which
$U_{\text{vdW}}\approx U^{(0)}_{\text{vdW}}+U^{(1)}_{\text{vdW}}$, where
$U^{(0)}_{\text{vdW}}$ is the vdW potential for the case of a grounded
conducting plane [8], and $U^{(1)}_{\text{vdW}}$, the first-order correction
to $U^{(0)}_{\text{vdW}}$ due to the surface corrugation, is given by

$U^{(1)}_{\text{vdW}}(\mathbf{r}_{0})=-\frac{\hbar
a}{64\pi^{2}\epsilon_{0}z_{0}^{4}}\sum_{i,j}{\cal K}_{ij}({\bf
r}_{0},h){\int_{0}^{\infty}d\xi\,\alpha_{ij}\left(i\xi\right)}$ (1)

where $\alpha_{ij}$ are the components of the polarizability tensor in the
laboratory system, the functions ${\mathcal{K}}_{ij}$ are written as

${\mathcal{K}}_{ij}({\bf r}_{0},h)=\frac{1}{a}\int\frac{d^{2}{\bf
q}}{(2\pi)^{2}}\tilde{h}({\bf q})e^{i{\bf q}\cdot{\bf
r}_{0\parallel}}\mathcal{J}_{ij}(z_{0}{\bf q}),$ (2)

with the functions $\mathcal{J}_{ij}(\mathbf{u})=\mathcal{J}_{ji}(\mathbf{u})$
given by

$\displaystyle\mathcal{J}_{kl}$ $\displaystyle=\delta_{kl}\frac{3}{8}|{{\bf
u}}|^{3}K_{3}(|{{\bf u}}|)-\frac{3}{8}u_{k}u_{l}|{{\bf u}}|^{2}K_{2}(|{{\bf
u}}|)\;\;(k,l=x,y),$ $\displaystyle\mathcal{J}_{zz}$
$\displaystyle=\left(2+\frac{3}{8}|{{\bf u}}|^{2}\right)|{{\bf
u}}|^{2}K_{2}(|{{\bf u}}|)+\frac{1}{4}|{{\bf u}}|^{3}K_{3}(|{{\bf u}}|),$ (3)
$\displaystyle\mathcal{J}_{kz}$ $\displaystyle=i{u}_{k}|{{\bf
u}}|^{2}K_{2}\left(|{{\bf u}}|\right)-\frac{3i}{8}{u}_{k}|{{\bf
u}}|^{3}K_{3}\left(|{{\bf u}}|\right)\;\;(k=x,y),$

where $K_{2}$ and $K_{3}$ are modified Bessel functions of the second kind.
Note that, $a/z_{0}\ll 1$ is our perturbative parameter and ${\cal K}_{ij}$
are dimensionless functions storing information on the corrugation.

Since we are interested in a particle arbitrarily oriented in space, using the
Euler angles we write
$\int_{0}^{\infty}d\xi\,\alpha_{ij}\left(i\xi\right)=R(\phi,\theta,\psi)AR^{-1}(\phi,\theta,\psi),$
where
$A=\int_{0}^{\infty}d\xi\,\text{diag}[\alpha_{1}\left(i\xi\right),\alpha_{2}\left(i\xi\right),\alpha_{3}\left(i\xi\right)]$.
Motivated by the discussion in Ref. [71], we write
$A=\gamma_{\text{iso}}\Pi(\gamma_{s},\gamma_{a})$ where
$\Pi(\gamma_{s},\gamma_{a})=I+\gamma_{s}M_{s}+\gamma_{a}M_{a}$, $I$ is the
$3\times 3$ identity matrix, $M_{s}=\text{diag}(-1,-1,2)$,
$M_{a}=\text{diag}(-3,3,0)$, and we introduced the parameters
$\gamma_{\mathrm{iso}}$, $\gamma_{s}$, and $\gamma_{a}$, which characterize,
in a convenient manner, the particle anisotropy, and are given by

$\gamma_{\mathrm{iso}}=\frac{\text{Tr}(A)}{3},\>\gamma_{s}=\frac{[A_{33}-\frac{(A_{22}+A_{11})}{2}]}{3\gamma_{\mathrm{iso}}},\>\gamma_{a}=\frac{\frac{(A_{22}-A_{11})}{2}}{3\gamma_{\mathrm{iso}}},$
(4)

assuming that the principal axes of the particle have been enumerated in such
a way that $A_{11}\leq A_{22}\leq A_{33}$. The $\gamma$ parameters are such
that $0\leq\gamma_{s}<1$, and
$0\leq\gamma_{a}\leq\min(\gamma_{s},1-\gamma_{s})$. The parameter $\gamma_{s}$
measures the degree of particle anisotropy, in the sense that $\gamma_{s}=0$
means an isotropic particle, whereas the greater the value of $\gamma_{s}$,
the greater the difference between the polarizability along
$\hat{\mathbf{e}}_{3}^{\prime}$ and the others along
$\hat{\mathbf{e}}_{1}^{\prime}$ and $\hat{\mathbf{e}}_{2}^{\prime}$. On the
other hand, $\gamma_{a}$ is an adittional measure of the particle anisotropy,
by means of the difference between the polarizabilities along
$\hat{\mathbf{e}}_{1}^{\prime}$ and $\hat{\mathbf{e}}_{2}^{\prime}$. Taking
all this into account, we write

$\frac{U_{\mathrm{vdW}}^{(1)}(\mathbf{r}_{0})}{\mathcal{U}(z_{0})}=-\text{Tr}[{\cal
K}(\mathbf{r}_{0},h)R(\phi,\theta,\psi)\Pi(\gamma_{s},\gamma_{a})R^{-1}(\phi,\theta,\psi)],$
(5)

where
${\mathcal{U}(z_{0})}={\hbar\gamma_{\mathrm{iso}}a}/{(64\pi^{2}\epsilon_{0}z_{0}^{4})}$.
The dimensionless ratio $U_{\mathrm{vdW}}^{(1)}/{\mathcal{U}(z_{0})}$ in Eq.
(5) is useful to investigate the behavior of the lateral vdW force for an
isotropic particle and a general anisotropic one, arbitrarily oriented in
space, interacting with a perfectly conducting corrugated surface. With this
in mind, hereafter we consider the particle kept constrained to move on the
plane $z=z_{0}$. In addition, a classical counterpart of Eq. (5), involving a
neutral particle with a permanent electric dipole moment, can be obtained in a
similar way (see Appendix A).

##  III A Gaussian protuberance

We first apply our Eq. (5) to investigate the vdW interaction for the
situation of a plane surface with a single slight Gaussian protuberance of
height $a$ and width $d$, given by
$h(\mathbf{r}_{\parallel})=a\exp[{-\left(|\mathbf{r}_{\parallel}|/d\right)^{2}}]$.
For this case, one obtains that

$\mathcal{K}_{ij}\left(\frac{{\bf
r}_{0\parallel}}{z_{0}},\frac{d}{z_{0}}\right)=\pi\frac{d^{2}}{z_{0}^{2}}\int\frac{d^{2}{\bf
u}}{(2\pi)^{2}}e^{-\frac{1}{4}\frac{d^{2}}{z_{0}^{2}}|{\bf u}|^{2}}e^{i{\bf
u}\cdot\frac{{\bf r}_{0\parallel}}{z_{0}}}\mathcal{J}_{ij}({\bf u}),$ (6)

and $U_{\mathrm{vdW}}^{(1)}/\mathcal{U}$ depends on the ratios $x_{0}/z_{0}$,
$y_{0}/z_{0}$ and $d/z_{0}$. The geometric effects of the Gaussian
protuberance are regulated by the ratio $d/z_{0}$, so that we are going to
investigate how the variation of this ratio affects the behavior of
$U_{\mathrm{vdW}}^{(1)}/\mathcal{U}$ in relation to $x_{0}/z_{0}$ and
$y_{0}/z_{0}$.

In the limit of a very smooth Gaussian $(d/z_{0}\to\infty)$, one recovers the
result characteristic of the PFA [56], and Eq. (5) becomes

$\displaystyle\frac{U_{\mathrm{vdW}}^{(1)}}{\mathcal{U}}$
$\displaystyle\approx-3e^{-\left(|\mathbf{r}_{\parallel}|/d\right)^{2}}$
$\displaystyle\times\text{Tr}[\text{diag}(1,1,2)R(\phi,\theta,\psi)\Pi\left(\gamma_{s},\gamma_{a}\right)R^{-1}(\phi,\theta,\psi)],$
(7)

In this context, one can observe that the minimum values of
$U_{\mathrm{vdW}}^{(1)}$ always coincide with the planar coordinates of the
Gaussian peak $(|\mathbf{r}_{\parallel}|=0)$, no matter if the particle is
isotropic or anisotropic (or how this latter is oriented). In other words,
when the PFA is considered, the prediction is that a particle will always be
attracted to the protuberance, under the action of the lateral vdW force.

For a generic value of $d/z_{0}$, when considering an isotropic particle
$(\gamma_{s}=0)$, Eq. (5) becomes simply
$U_{\mathrm{vdW}}^{(1)}/\mathcal{U}=-\text{Tr}({\cal K})$, and we obtain that
$U_{\mathrm{vdW}}^{(1)}$ has a single minimum point at
$|\mathbf{r}_{\parallel}|=0$ for any value of $d/z_{0}$, which means that,
under the action of the lateral vdW force, an isotropic particle is always
attracted to the peak of the Gaussian protuberance. On the other hand, when we
consider an anisotropic particle, our Eq. (5) shows that nontrivial geometric
effects arise when the ratio $d/z_{0}$ decreases. Hereafter, for simplicity,
we focus our analysis on the case of generic particles characterized by
$\gamma_{a}=0$ (cylindrically symmetric polarizable particles) and oriented
with $\phi=0,\psi=0$ (which means that $\hat{\mathbf{e}}_{3}^{\prime}$ is on
the $xz$-plane). In this context, let us consider ${d}/{z_{0}}=0.8$,
$\gamma_{s}=0.6$, and $\theta=\pi/2$
($\hat{\mathbf{e}}_{3}^{\prime}=\hat{\mathbf{x}}$). When the PFA is used, we
obtain that the equipotential lines are circular, and the minimum value of
$U^{(1)}_{\text{vdW}}$ is located at the origin, so that the lateral vdW force
attracts the particle to the protuberance peak [see Fig. 2]. On the other
hand, a better description of the behavior of $U^{(1)}_{\text{vdW}}/{\cal{U}}$
is obtained by using Eq. (5) and shown in Fig. 2, from where one can see that
the minimum point of $U^{(1)}_{\text{vdW}}$ remains at the origin, but the
equipotential lines are, in fact, ellipsoidal. Now, let us decrease the ratio
$d/z_{0}$, considering, for example, $d/z_{0}=0.2$. In Fig. 2, we show the
behavior of $U^{(1)}_{\text{vdW}}/{\cal{U}}$ for this case, according to Eq.
(5). One can see that, now, the energy has two minimum points, and none of
them coincide with the peak of the Gaussian. As a consequence of this change
in the minimum points, one has a considerable change in the shape of the
equipotential lines, and the particle can feel a lateral vdW force which moves
it away from the peak of the protuberance. Thus, when a particle is slightly
dislocated from the point $(0,0,z_{0})$, along the $x$-axis, the lateral force
points to opposite directions when comparing the situations with
${d}/{z_{0}}=0.8$ [Fig. 2] and ${d}/{z_{0}}=0.2$ [Fig. 2]. This sign inversion
in the lateral vdW force is therefore a nontrivial geometric effect regulated
by the ratio $d/z_{0}$. Moreover, this effect is affected by the particle
orientation. From the case shown in Fig. 2, for example, if we change the
particle orientation to $\theta=0$
$(\hat{\mathbf{e}}_{3}^{\prime}=\hat{\mathbf{z}})$, one sees that the energy
has only one minimum point located at the origin and the equipotencial lines
are circular [see Fig. 2], so that the lateral vdW force leads the particle to
the Gaussian peak, independently of the ratio $d/z_{0}$ (a discussion of cases
where $0<\theta<\pi/2$ can be found in Appendix B).

All these nontrivial effects are also influenced by the particle anisotropy.
We consider a generic particle characterized by $\gamma_{a}=0$ and an
arbitrary value for $\gamma_{s}$, oriented with $\phi=\psi=0$ and
$\theta=\pi/2$. In Fig. 3 we show the configurations of $\gamma_{s}$ and
$d/z_{0}$ for which the center of the protuberance is a minimum (dark region)
or a maximum (lighter region) point of $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$. The
sign inversion in the lateral force is possible when there is a transition
from a configuration in the dark region to another in the lighter one. For
instance, when we consider $\gamma_{s}=0.6$, and change the ratio
${d}/{z_{0}}$ from ${d}/{z_{0}}=0.8$ to ${d}/{z_{0}}=0.2$, we have a
transition from the dark to the lighter region in Fig. 3, which corresponds to
the transition from Figs. 2 to 2. On the other hand, when considering
$\gamma_{s}<5/14$, there is no change of the ratio ${d}/{z_{0}}$ that makes
possible a transition from the dark to the lighter region, so that there is no
possibility of a sign inversion in the lateral force. In addition, the change
from the dark to the lighter region in Fig. 3 can also be obtained by
considering a fixed value for $d$, and increasing $z_{0}$, so that as $z_{0}$
increases, the more evident are the effects predicted here. In this way, even
if $z_{0}$ becomes large enough for the retardation effects become relevant
(Casimir-Polder regime of the interaction), we expect that a sign inversion in
the lateral force will still occur.

When, instead of considering a protuberance $z=h(x)\geq 0$ in Eq. (5), we
consider a hole $[h(x)\leq 0]$, the sign of $U_{\mathrm{vdW}}^{(1)}$ is
inverted, which means that the minimum points of $U_{\mathrm{vdW}}^{(1)}$ for
a protuberance become maximum points for a hole, and vice-versa. In this way,
for a Gaussian hole, with characteristic width $d$, when the PFA formula is
applied, the particle is always moved away from the hole, no matter if it is
isotropic or anisotropic [see Fig. 4]. On the other hand, using Eq. (5), while
an isotropic particle is always moved away from the hole, independently of the
ratio $d/z_{0}$, an anisotropic particle can be attracted to the hole when the
ratio $d/z_{0}$ is decreased [see Figs. 4 and 4].

Figure 2:  Behavior of $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$ and ${y_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$. In
each figure, we consider this particle characterized by $\gamma_{a}=0$ and
$\gamma_{s}=0.6$, oriented such that $\phi=0$ and $\psi=0$. The insets in the
bottom of the graphics illustrate the Gaussian profile projected on the plane
$y=0$, a particle located at $(x_{0},0,z_{0})$, its orientation and the
direction of the lateral vdW force acting on it. In (a), the PFA is
considered. In (b) - (d), we consider our Eq. (5), providing predictions
beyond the PFA. From (b) to (c), the Gaussian width decreases (decreasing the
ratio $d/z_{0}$). From (c) to (d), there is a change on the particle
orientation.

Figure 3:  For a particle characterized by $\gamma_{a}=0$ and oriented with
$\phi=0,\theta=\pi/2,\psi=0$, it is shown the configurations of $\gamma_{s}$
and $d/z_{0}$ for which the center of the protuberance is a minimum (dark
region) or a maximum (lighter region) point of
$U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$, as illustrated in the insets. In (a), we
show this for a Gaussian protuberance, whereas in (b), for a rectangular
strip. The dotted lines highlight the values of $\gamma_{s}$ [$5/14$ in (a)
and $4/11$ in (b)], below which there is no value of $d/z_{0}$ that makes
possible a transition from the dark to the lighter region, so that there is no
possibility of a sign inversion in the lateral force.

Figure 4:  Behavior of $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$ and ${y_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$
interacting with a plane with a Gaussian hole of width $d$. In each figure, we
consider this particle characterized by $\gamma_{a}=0$ and $\gamma_{s}=0.6$,
oriented such that $\phi=0$ and $\psi=0$. The insets in the bottom of the
graphics illustrate the Gaussian hole projected on the plane $y=0$, a particle
located at $(x_{0},0,z_{0})$, its orientation and the direction of the lateral
vdW force acting on it. In (a), the PFA is considered, whereas in (b) and (c),
we consider predictions beyond this approximation. From (b) to (c), the width
of the Gaussian hole decreases (decreasing the ratio $d/z_{0}$). Note that,
when a particle is slightly dislocated from the point $(0,0,z_{0})$, along the
$x$-axis, the lateral force points to opposite directions when comparing these
situations.

The detection of such geometric effects on the lateral vdW force could be
done, for example, by trapping a particle with mass $m$, near a plane with a
protuberance, and measuring the deviation (due to the protuberance) in the
original trap frequency (see, for instance, Refs. [22, 55, 65]). In the
present context, let us consider the situations described in Figs. 2 and 2 and
that the particle is constrained to oscillate only along the $x$-axis, trapped
by a harmonic potential $U_{\text{trap}}(x)$ with equilibrium point at
$x_{0}=0$ (see Fig. 5). In the absence of the protuberance, the particle would
oscillate around $x_{0}=0$ with a frequency $\omega_{\text{trap}}$. However,
the presence of the protuberance modifies this oscillation frequency to a new
value
$\omega_{\text{trap}}^{\prime}=\sqrt{\omega_{\text{trap}}^{2}+m^{-1}\left[\partial^{2}U_{\text{vdW}}^{(1)}/\partial
x_{0}^{2}\right]_{x_{0}=0}}$, resulting in a frequency deviation
$\delta\omega_{\text{trap}}\equiv\omega_{\text{trap}}^{\prime}-\omega_{\text{trap}}$.
When the peak of the protuberance coincides with the minimum point of
$U_{\text{vdW}}^{(1)}$, an experimental apparatus would detect
$\delta\omega_{\text{trap}}>0$ [see Fig. 5]. Otherwise, when the peak of the
protuberance coincides with a local maximum point of $U_{\text{vdW}}^{(1)}$,
one has $\delta\omega_{\text{trap}}<0$ [see Fig. 5]. Therefore, the sign
inversion in the lateral force [illustrated in Figs. 2 and 2] manifests, in
this scenario, as a sign inversion in the frequency deviation
$\delta\omega_{\text{trap}}$. In addition, as discussed in Refs. [72, 65, 66],
when the reflectivity of a surface is not perfect, the vdW interaction differs
by a numerical factor from the one calculated considering an ideal surface.
Thus, we expect that the sign inversion in the lateral vdW force, and its
manifestation as a sign inversion in $\delta\omega_{\text{trap}}$, manifests
itself even when considering nonideal materials.

Figure 5:  In (a), where the peak of the protuberance coincides with the
minimum point of $U_{\text{vdW}}^{(1)}$, an experimental apparatus would
detect $\delta\omega_{\text{trap}}>0$. In (b), the peak of the protuberance
coincides with a local maximum point of $U_{\text{vdW}}^{(1)}$, and for this
case one has $\delta\omega_{\text{trap}}<0$. Therefore, the sign inversion in
the lateral force [illustrated in Figs. 2 and 2] manifests, in this scenario,
as a sign inversion in the frequency deviation $\delta\omega_{\text{trap}}$.

##  IV Rectangular protuberances and gratings

Since Eq. (5) can be applied to any surface profile, let us apply it to other
surface geometries to investigate the generality of the effects discussed so
far. When considering a rectangular strip of height $a$ and width $d$,
described by
$h(\mathbf{r}_{||})=a\left[\Theta\left(x+\frac{d}{2}\right)-\Theta\left(x-\frac{d}{2}\right)\right]$,
where $\Theta$ is the Heaviside step function, we obtain that

$\mathcal{K}_{ij}\left(\frac{x_{0}}{z_{0}},\frac{d}{z_{0}}\right)=\frac{3}{16}[f_{ij}\left(\frac{x_{0}}{z_{0}}+\frac{1}{2}\frac{d}{z_{0}}\right)-f_{ij}\left(\frac{x_{0}}{z_{0}}-\frac{1}{2}\frac{d}{z_{0}}\right)],$
(8)

where

$\displaystyle f_{xx}(u)$
$\displaystyle=\frac{u^{3}(8u^{4}+28u^{2}+35)}{(u^{2}+1)^{7/2}},$
$\displaystyle f_{yy}(u)$
$\displaystyle=\frac{u(8u^{4}+20u^{2}+15)}{(u^{2}+1)^{5/2}},$ $\displaystyle
f_{zz}(u)$
$\displaystyle=\frac{u(16u^{6}+56u^{4}+66u^{2}+41)}{(u^{2}+1)^{7/2}},$ (9)
$\displaystyle f_{xz}(u)$ $\displaystyle=\frac{8u^{2}-7}{(u^{2}+1)^{7/2}},$
$\displaystyle f_{xy}(u)$ $\displaystyle=f_{yz}(u)=0,$

and $U_{\mathrm{vdW}}^{(1)}/\mathcal{U}$ depends on the ratios $x_{0}/z_{0}$
and $d/z_{0}$. When the PFA is applied, the prediction is that a particle
above the strip feels no lateral vdW force. On the other hand, according to
our Eq. (5), while an isotropic particle is, in fact, always attracted to the
center of the strip (in agreement with Ref. [55]), when an anisotropic one is
considered, a sign inversion in the lateral vdW force can occur as $d/z_{0}$
decreases (see, for instance, Fig. 6). It is remarkable that when considering
$\gamma_{s}<4/11$ there is no change of the ratio ${d}/{z_{0}}$ that makes
possible a sign inversion in the lateral vdW force [see Fig. 3].

Figure 6:  Behavior of $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$, and oriented with
$\phi=0,\theta=\pi/2,\psi=0$ (in this case, the vector
$\hat{\mathbf{e}}_{3}^{\prime}$ coincides with $\hat{\mathbf{x}}$). From top
to bottom figure, we change the ratio ${d}/{z_{0}}$ from ${d}/{z_{0}}=1$
(dashed line) to ${d}/{z_{0}}=0.1$ (dot-dashed line). In these figures, the
surface profiles are represented by the solid lines. Note that, from top to
bottom figure, we have a change in the minimum points, so that a particle
slightly dislocated from the origin feels a sign inversion in the lateral
force.

Sign inversions in the lateral force also occur when we consider more than one
protuberance in the plane, but a relevant difference can be observed when we
compare this case involving a collective of protuberances with that of a
single protuberance. To investigate this, let us consider a particle
characterized by $\gamma_{s}=0.2$ and oriented with $\theta=\pi/2$,
interacting with two rectangular strips of height $a$, width $d$, and distant
by $L$ from each other, which are described by
$h\left(\mathbf{r}_{||}\right)=a\left[\Theta\left(x+L+\frac{d}{2}\right)-\Theta\left(x+\frac{L}{2}\right)\right]+a\left[\Theta\left(x-\frac{L}{2}\right)-\Theta\left(x-L-\frac{d}{2}\right)\right]$.
According to Eq. (5), when we have, for instance, $L/z_{0}=0.5$, we obtain
that for $d/z_{0}=0.8$ the minimum points of the energy are over the strips
[see Fig. 7(i)], whereas when $d/z_{0}=0.2$ the energy has only one minimum
point located at the middle point between the strips [Fig. 7(ii)]. As a
consequence of this change in the minimum points, for a particle slightly
dislocated from the origin, along the $x$-axis, the lateral force points to
opposite directions when comparing both situations [Figs. 7(i) and 7(ii)].
Although we have a sign inversion in this case of two strips, if we had
considered a single strip, one would see that the change from $d/z_{0}=0.8$ to
$d/z_{0}=0.2$ does not change the minimum point of the energy, which remains
at the center of the protuberance [see Figs. 7(iii) and 7(iv)]. This occurs
because we are considering $\gamma_{s}=0.2$, a value for which, in the
presence of a single protuberance, there is no possibility of a sign inversion
in the lateral force, since it is less than $4/11$. Thus, from all this, one
can conclude that the consideration of more than one protuberance is not a
mere extension of an individual effect (originated from a single
protuberance), but, more than that, there are sign inversions in the lateral
force that are induced only by a collective of protuberances. As the number of
rectangular strips increases, so that they tend to form a periodic structure,
these collective effects manifest themselves as the peak and valley regimes
(see, for instance, Appendix C), which were recently described in the
literature [65, 66].

Figure 7:  Behavior of the ratio $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$, with $\gamma_{a}=0$,
$\gamma_{s}=0.2$ and oriented with $\phi=0,\theta=\pi/2,\psi=0$. In (i) and
(ii), we consider two strips of width $d$, distant $L$ from each other, with
$L/z_{0}=0.5$. In (iii) and (iv), we consider a single strip of width $d$. In
these figures, the surface profiles are represented by the solid lines. From
top to bottom figures, we change the ratio ${d}/{z_{0}}$ from
${d}/{z_{0}}=0.8$ (dashed line) to ${d}/{z_{0}}=0.2$ (dot-dashed line). Note
that, from (i) to (ii), we have a change in the minimum points, so that a
particle slightly dislocated from the origin feels a sign inversion in the
lateral force. On the other hand, due to the considered value for
$\gamma_{s}$, from (iii) to (iv), we do not have a change in the minimum point
of the energy.

##  V Final Remarks

The interest in knowing how to control the sign of dispersive forces has grown
[29, 30, 6, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,
47, 48, 49]. In this context, we predicted the possibility of sign inversions
in the lateral vdW force acting on an anisotropic particle interacting with a
perfectly conducting plane containing a single slight protuberance, and showed
that these sign inversions can be controlled by suitable manipulations of the
ratio between the characteristic widths of the protuberance and the particle-
plane distance, opening a new path for investigations of nontrivial aspects of
dispersive forces. Even for situations where the sign inversion does not occur
in the presence of a single protuberance, we showed that it can arise when two
or more protuberances are put together. Thus, we observed a distinction
between sign inversions in the lateral vdW force originated by a purely
individual effect, from those originated by a collective effect (such as the
peak and valley regimes, recently described in the literature in the context
of periodic gratings [65, 66]).

We showed that a sign inversion in the lateral vdW force manifests itself as a
sign inversion in the frequency deviation of a particle trapped near a plane
with a protuberance. Thus, the comprehension of all these nontrivial geometric
effects on the lateral vdW force is relevant to achieve a higher degree of
control of the interaction between a neutral anisotropic polarizable particle
and a corrugated surface.

###### Acknowledgements.

The authors thank Alexandre Costa, Carlos Farina, Stanley Coelho, and Van
Sérgio Alves for valuable discussions. L.Q. and E.C.M.N. were supported by the
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES),
Finance Code 001.

##  Appendix A Classical counterpart of Eq. (5)

To investigate the existence of sign inversions in the lateral force in a
classical context, involving a neutral particle with a permanent electric
dipole moment $\bf{p}$, we again take as basis the perturbative approach shown
in Ref. [65], according to which the interaction energy $U_{\text{cla}}$,
between a dipolar particle and a corrugated surface, is given by
$U_{\text{cla}}\approx U^{(0)}_{\text{cla}}+U^{(1)}_{\text{cla}}$, where
$U^{(0)}_{\text{cla}}$ is the interaction energy for the case of a grounded
conducting plane [73], and $U^{(1)}_{\text{cla}}$ is given by
$U^{(1)}_{\text{cla}}(\mathbf{r}_{0})=-\frac{a}{z_{0}}\sum_{i,j}{\cal
K}_{ij}({\bf r}_{0},h)p_{i}p_{j}/{(64\pi\epsilon_{0}z_{0}^{3})}$. After
manipulations of this formula, we obtain

$\frac{U_{\mathrm{cla}}^{(1)}(\mathbf{r}_{0})}{\mathcal{U}_{\text{cla}}(z_{0})}=-\text{Tr}[{\cal
K}(\mathbf{r}_{0},h)R(\phi,\theta,\psi)\Pi(1,0)R^{-1}(\phi,\theta,\psi)],$
(10)

where
${\mathcal{U}_{\text{cla}}(z_{0})}=a|{\bf{p}}|^{2}/({192\pi\epsilon_{0}z_{0}^{4}})$.
Note that the behavior of the classical ratio
$U_{\mathrm{cla}}^{(1)}/\mathcal{U}_{\text{cla}}$ is the same of the quantum
ratio $U_{\mathrm{vdW}}^{(1)}/\mathcal{U}$ for $\gamma_{s}=1$ and
$\gamma_{a}=0$. Therefore, similar sign inversions in the lateral force also
arise in the classical context.

##  Appendix B Behavior of $U^{(1)}_{\text{vdW}}/{\cal{U}}$ for
$0<\theta<\pi/2$

The sign inversion in the lateral vdW force is affected by the particle
orientation. Let us consider, for instance, a particle characterized by
$\gamma_{a}=0$ and $\gamma_{s}=0.6$, oriented with $\phi=0,\psi=0$, and the
ratio ${d}/{z_{0}}=0.2$. When $\theta=\pi/2$
($\hat{\mathbf{e}}_{3}^{\prime}=\hat{\mathbf{x}}$), we have the case shown in
Fig. 2, whereas, when $\theta=0$
$(\hat{\mathbf{e}}_{3}^{\prime}=\hat{\mathbf{z}})$, we have the case shown in
Fig. 2. In these two cases, $U^{(1)}_{\text{vdW}}/{\cal{U}}$ has a symmetric
behavior. On the other hand, when considering $0<\theta<\pi/2$ one can see
that such symmetry does not occur anymore. In comparison to the case shown in
Fig. 2, if we make a small change in the particle orientation, for example,
from $\theta=\pi/2$ to $\theta=0.47\pi$, one can see that the energy still has
two minimum points, but one of them is, now, only a local minimum point [see
Fig. 8]. However, if $\theta$ decreases further, for example, from
$\theta=0.47\pi$ to $\theta=\pi/3$, we have only a global minimum point, which
does not coincide with the peak of the Gaussian [see Fig. 8].

Figure 8:  Behavior of $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$ and ${y_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$. In
each figure, we consider this particle characterized by $\gamma_{a}=0$ and
$\gamma_{s}=0.6$, oriented such that $\phi=0$ and $\psi=0$, and the ratio
${d}/{z_{0}}=0.2$. The insets in the bottom of the graphics illustrate the
Gaussian profile projected on the plane $y=0$, a particle located at
$(x_{0},0,z_{0})$, its orientation and the direction of the lateral vdW force
acting on it. From (a) to (b), there is a change on the particle orientation
from $\theta=0.47\pi$ to $\theta=\pi/3$.

##  Appendix C Peak and valley regimes

The result in Eq. (8) can be readily generalized for the case of $N$ strips of
width $d$, distant by $L$ from each other. In this case, the profile function
is given by

$\displaystyle h(\mathbf{r}_{||})$
$\displaystyle=a\sum_{k=1}^{N}\left\\{\Theta\left[x+\left(\frac{N+1}{2}-k\right)(L+d)+\frac{d}{2}\right]\right.$
$\displaystyle\left.-\Theta\left[x+\left(\frac{N+1}{2}-k\right)(L+d)-\frac{d}{2}\right]\right\\},$
(11)

so that, one can write

$\displaystyle\mathcal{K}_{ij}^{(N)}$
$\displaystyle\left(\frac{x_{0}}{z_{0}},\frac{d}{z_{0}},\frac{L}{z_{0}}\right)$
$\displaystyle=\sum_{k=1}^{N}\mathcal{K}_{ij}\left[\frac{x_{0}}{z_{0}}+\left(\frac{N+1}{2}-k\right)\left(\frac{L}{z_{0}}+\frac{d}{z_{0}}\right),\frac{d}{z_{0}}\right],$
(12)

with $\mathcal{K}_{ij}$ given by Eq. (8). As $N$ increases, so that the strips
tend to form a periodic structure, one can see these collective effects
manifesting themselves as the peak and valley regimes (see Fig. 9), which were
recently described in the literature [65, 66].

Figure 9:  Behavior of the ratio $U_{\mathrm{vdW}}^{(1)}/{\cal{U}}$ versus
${x_{0}}/{z_{0}}$, for a particle fixed at $z=z_{0}$, with $\gamma_{a}=0$,
$\gamma_{s}=0.2$ and oriented with $\phi=0,\theta=\pi/2,\psi=0$. We consider a
periodic structure formed by several rectangular strips of width $d$ and
distant $L$ from each other, so that $L/z_{0}=0.5$ (the surface profile is
represented by the solid lines). From top to bottom figure, we change the
ratio ${d}/{z_{0}}$ from ${d}/{z_{0}}=0.8$ (dashed line) to ${d}/{z_{0}}=0.2$
(dot-dashed line). In the top figure, note that the minimum points of the
energy are over the centers of the protuberances, with such behavior called in
Ref. [65] as peak regime. On the other hand, in the bottom figure the minimum
points are over the middle points between a pair of strips, with such behavior
called in Ref. [65] as valley regime.

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# Algorithms and Hardware for Efficient Processing of Logic-based Neural
Networks††thanks:  This research is supported in part by a grant from the
Software and Hardware Foundations program of the National Science Foundation.

Jingkai Hong*, Arash Fayyazi*, Amirhossein Esmaili, Mahdi Nazemi, and Massoud
Pedram *Jingkai Hong and Arash Fayyazi contributed equally to this work.
Department of Electrical & Computer Engineering, University of Southern
California, Los Angeles, CA, USA
<EMAIL_ADDRESS>
###### Abstract

Recent efforts to improve the performance of neural network (NN) accelerators
that meet today’s application requirements have given rise to a new trend of
logic-based NN inference relying on fixed-function combinational logic (FFCL).
This paper presents an innovative optimization methodology for compiling and
mapping NNs utilizing FFCL into a logic processor. The presented method maps
FFCL blocks to a set of Boolean functions where Boolean operations in each
function are mapped to high-performance, low-latency, parallelized processing
elements. Graph partitioning and scheduling algorithms are presented to handle
FFCL blocks that cannot straightforwardly fit the logic processor. Our
experimental evaluations across several datasets and NNs demonstrate the
superior performance of our framework in terms of the inference throughput
compared to prior art NN accelerators. We achieve 25x higher throughput
compared with the XNOR-based accelerator for VGG16 model that can be amplified
5x deploying the graph partitioning and merging algorithms.

##  I Introduction

Deep neural networks (DNNs) provide state-of-the-art (SoA) performance in
various artificial intelligence applications and have surpassed the accuracy
of conventional machine learning models in many challenging domains, including
computer vision [21, 7] and natural language processing [6, 4]. The emergence
of more complex DNN models such as transformers [18] and MLPMixers [15] is a
key reason for the remarkable performance of DNNs in many application domains
but these models impose huge compute and memory resource requirements.

To improve the efficiency of DNNs, some prior work formulates the problem of
efficient processing of neural networks as a Boolean logic minimization
problem where ultimately, logic expressions compute the output of various
filters/neurons. NullaNet [10] optimizes a target DNN for a given dataset and
maps essential parts of the computation in DNNs to logic blocks, such as look-
up tables (LUTs) on FPGAs. In most cases, including those used in this study,
the average accuracy drop for binary implementation is less than 4%.

The issue is once the target fixed-function combinational logic (FFCL) for a
specific NN model is synthesized, the synthesized fabric can only be used for
the inference task of that given NN model, which makes ASIC realization of
FFCL impractical. In addition, since neurons designed for SoA NNs include tens
to hundreds of inputs, the obtained Boolean logic expression can be huge. Our
experiments show that it is impossible to map some generated Boolean logic
functions onto a single FPGA because LUTs are used up and cannot accommodate
such huge Boolean functions.

A logic processor comprising a Boolean logic unit, in which the Boolean logic
unit is responsible for performing Boolean operations of each Boolean function
associated with an FFCL block extracted from a binary neural network (BNN), as
introduced in [11], is critical to doing inference with different BNNs.
Therefore, designing configurable efficient logic processors as logic-based
inference engines, which can be used in a variety of applications with
different DNN models, is highly desirable.

The compilation and scheduling of an arbitrary logic graph associated with a
Boolean function to be mapped onto a logic processor is a demanding task from
the viewpoint of the compiler design. The compiler needs to detect and group
the operations of all gates that can be executed simultaneously, considering
hardware resource limitations (i.e., the number of Boolean logic units per
logic processor). To address these challenges, we design a many-core logic
processor and introduce novel techniques for compiling and mapping BNNs that
utilize FFCL into this logic processor. Furthermore, we present an original
graph partitioning algorithm for handling very large logic graphs. The
contributions of the paper are as follows:

  * •

We present the design of a logic processor which can process large Boolean
functions.

  * •

We present an innovative optimization methodology for compiling and mapping
BNNs utilizing FFCL into this logic processor. The proposed compiler generates
customized instructions for static scheduling of all operations of the logic
graph during inference.

  * •

We present a method to map FFCL blocks to a set of Boolean functions where
Boolean operations in each function are mapped to high-performance, low-
latency, and parallelized processing elements.

  * •

We present a graph partitioning algorithm to efficiently deal with very large
Boolean logic graphs.

  * •

Our experimental evaluations across several datasets and NNs demonstrate the
superior performance of our framework in terms of the inference throughput
compared to prior art NN accelerators. We achieve 25x higher throughput
compared with the XNOR-based accelerator for VGG16 model [13] that can be
amplified 5x deploying the graph partitioning and merging algorithms.

While the scope of this work is focused on the algorithms for enabling the
execution of arbitrary-size FFCL blocks on a logic processing fabric, we also
present the results of using our algorithms and hardware design on an FPGA to
determine their efficacy. The algorithms and hardware can be used for an ASIC
design as well.

##  II Terminology and Notation

This section provides the terminology and notation used throughout this paper:

  * •

Fixed-function combinational logic (FFCL) block: A netlist of a combinational
logic circuit written in a hardware description language, such as Verilog.

  * •

Logic processing element (LPE): A programmable hardware block which performs
(two-input) logic operations such as AND, OR, XOR, etc.

  * •

Logic processing vector (LPV): A hardware block that contains a fixed number
of LPEs. LPVs are linearly ordered relative to each other.

  * •

Logic processing unit (LPU): A hardware block that contains a fixed number of
LPVs, also called a logic processor in this paper.

  * •

Maximal feasible subgraph (MFG): A directed acyclic graph (where nodes are
Boolean operations and edges are data dependencies) greedily extracted from an
FFCL without exceeding the LPU’s capacity when mapping to an LPU.

  * •

Full path balancing (FPB): Equalizing the logic depth of all propagation paths
from circuit inputs (i.e., primary inputs) to circuit outputs (i.e., primary
outputs). It guarantees all input-output paths have the same number of gates
on them.

##  III Proposed Design Flow

The overall flow of the proposed framework is as depicted in Fig. 1. The input
to the flow is a description of an FFCL block in the Verilog language. Please
note that the framework can be structured to accept any specification of an
FFCL block as the input. Yosys [19] and ABC [3] can be used to generate
synthesizable Verilog code from any behavioral specification. NullaNet [10]
generates the FFCL block in Verilog format and will be used as the upper
stream engine. We first parse the Verilog netlist, synthesize the circuit
using standard logic optimization techniques, primarily aimed at reducing the
total gate count and depth of the circuit, and map the circuit to a customized
cell library. Notice that the Boolean operations supported by the logic gates
in the cell library, such as two input AND, OR, and XOR operations, must be
supported by the LPEs. Next, the mapped circuit is levelized according to the
definition in Section II. The logic synthesis and levelization are the same as
the one presented in [12].

Because a gate that is at a specific logic level in a target circuit has no
connections to any other gates at the same logic level, operations of all
gates at the same logic level can be executed simultaneously. However, these
operations may have to be assigned to different compute cycles due to hardware
resource limitations, i.e., the fixed number of LPVs per LPU (the depth issue)
or the fixed number of LPEs per LPV (the width issue). Multiple LPUs can be
assembled in parallel or series configuration for large graphs to complete the
required computations for a given logic graph at the extra area/power cost.
Our compiler has the ability to map any logic graph to an arbitrary-size LPU.
To handle the width issue, the compiler decomposes the filter/neuron functions
into MFGs, each of which is then mapped onto the LPU one after the other (more
details in Section V).

Figure 1:  An overview of the proposed framework.

##  IV logic Processor Architecture

Figure 2:  The LPU architecture.

The architecture of the logic processor is shown in Fig. 2. The logic
processor is a data-driven architecture in the sense that the streaming data
is received and processed by multiple stages of LPVs without having to store
any intermediate results in some scratchpad memories. More precisely, a logic
processor comprises a set of LPVs that are linearly ordered. Each LPV contains
$m$ LPEs, each of which receives two inputs and produces one output,
resembling a logic gate. Therefore, each LPV receives up to $2m$ input
operands and produces a vector of up to $m$ output results. To support logic
operation packing and increase hardware efficiency, each operand has a width
of $2m$ bits, which translates into $2m$ Boolean variables or $m$ 4-valued
logic variables, etc. In the case of processing an FFCL block extracted from a
convolutional neural network (CNN) model, the $2m$ bits of data come from
different patches of an input feature volume in a CNN or from different images
for batch-based inference tasks. To pass data from the $i$th LPV to the
$(i+1)$th LPV, we use a non-blocking multicasting multi-stage switch network.

The number of LPEs per LPV and the number of LPVs per LPU determine the size
of the logic graph that can be processed by an LPU. With the parameter values
described previously, an LPU can process a logic graph with a maximum width of
$m$ and a maximum depth of $n$, where the width refers to the number of logic
operations at any logic depth in the graph and the depth refers to the logic
depth from any graph inputs to any graph outputs.

Because of the data dependency between two adjacent logic levels within a
logic graph, the intuitive way of computing a graph is level by level.
However, given the hardware budget is tight and high throughput is desired, it
is not an attractive option to use scratchpad memories to store temporary
results (i.e., results produced but not yet consumed) between two logic
levels. Therefore, we propose distributed snapshot registers to store
temporary results as shown in Fig. 2. Moreover, we propose a MFG-by-MFG
computing paradigm and the scheduling algorithm, which are detailed in Section
V. This paradigm further exploits the locality brought about by the snapshot
registers that are placed in each of the LPEs.

Each LPE contains a logic unit where an elementary Boolean operation can be
performed, and two snapshot registers where each of the LPE inputs can be
temporarily stored for a certain data lifecycle determined by the compiler.
Additionally, the operations assigned to each LPE are configured with the aid
of a instruction set. Notice two types of logic operation can be performed,
namely, a multiple-input single-output (MISO) operation including AND, OR,
XOR/XNOR and a single-input single-output (SISO) operation including
NOT/BUFFER. BUFFER denotes a node that is added to a directed acyclic graph
(DAG) to make all paths between any two connected nodes have the same
topological length (i.e., an equal number of gates exist on all paths between
two connected nodes). Buffer insertions are done as a part of the full path
balancing step. Full path balancing guarantees no data dependencies exist
between two non-adjacent logic levels of gates, simplifying the mapping of the
logic graph onto our pipelined architecture.

##  V Compiler

A compiler tailored to the logic processor is presented. The compiler parses a
gate-level Verilog netlist to extract the set of operations that are carried
out at each logic level of the circuit netlist, creates a DAG to represent
these gate operations and their directional data dependencies, then partitions
this DAG into MFGs such that each MFG can fit in the given LPU. Then it
schedules the generated MFGs and maps them to different LPVs in different
compute cycles. As a result, the LPU processes level by level within each MFG
and executes the large logic graph in an MFG-by-MFG manner.

###  V-A Boolean network partitioning

Consider a subgraph $H=(V^{\prime},E^{\prime})$ of a fully path balanced
Boolean DAG $G=(V,E)$. Logic levels of nodes in subgraph $H$ are from
$L_{bottom}(H)$ to $L_{top}(H)$. Now, given a partitioning solution $P$ of
graph $G$ such that $P$ consists of $|P|$ subgraphs, we have:

$\forall H\in P,~{}~{}~{}0\leq L_{bottom}(H)\leq L_{top}(H)\leq L_{max}$

where $0$ and $L_{max}$ denote the levels of primary inputs and primary
outputs of $G$, respectively. We denote the set of nodes in a logic level $l$
by $node\\_set(l)$. Moreover, given a set of nodes $S$, let $input(S)$ denote
the set of distinct nodes that feed into the set of nodes $S$.

The MFGs must satisfy the following conditions. First, the corresponding
subgraphs $H$ must satisfy:

$\displaystyle\forall l\in[L_{bottom}(H)+1,L_{top}(H)]\implies$ (1)
$\displaystyle input(node\\_set(l))\in H$

which implies that inputs of all levels of a subgraph except the bottom-most
level must also be contained in the same subgraph. Differently stated, inbound
connections from nodes outside the subgraph to a node inside the subgraph are
allowed only at the bottom-most level of the subgraph. Second, a subgraph must
contain at most $m$ nodes in each level of the subgraph (recall that each LPV
in the proposed logic processor has $m$ LPEs):

$\forall l\in[L_{bottom}(H),L_{top}(H)],|node\\_set(l)|\leq m$ (2)

Note that nodes need not belong exclusively to a subgraph, i.e., MFGs can have
overlapping node sets. More precisely,

$\exists l\in H,\exists l^{\prime}\in H^{\prime},node\\_set(l)\cap
node\\_set(l^{\prime})\neq\emptyset$ (3)

And, finally, nodes in the bottom-most level of an MFG must have input node
count greater than $m$ with the exception of the subgraphs whose inputs are
the PIs of $G$:

$\displaystyle\forall H\in P\setminus\\{H_{0}|L_{bottom}(H_{0})=0\\},$ (4)
$\displaystyle|input(node\\_set(L_{bottom}(H)))|>m$

where $\setminus$ denotes the set subtraction operation. Notice that the
inputs of the bottom-most level of a subgraph $H$ are not included in $H$.
This equation is the break condition of while loop in Algorithm 2.

The Boolean network partitioning pseudo-code is shown in Algorithm 1. The
algorithm uses a BFS traversal starting from the primary outputs (POs) on the
given graph to find all MFGs. The MFG rooted at the POs is obtained by using
the $findMFG()$ procedure as explained in Algorithm 2. Algorithm 1 then
continues by finding MFGs rooted at input nodes of the just extracted MFG. The
traversal continues until we reach the PIs of the Boolean network. The
procedure to construct an MFG rooted at some node $V$ keeps adding nodes to
the MFG (again in a BFS traversal manner) until it reaches a logic level in
its transitive fanin cone that has more than $m$ nodes, which is called the
stop level. Note that, as seen in Algorithm 2 and also shown in Fig. 3, the
MFG rooted at $V$ does not include the stop level nodes. The MFG cannot
include any subset of nodes at its stop level because condition 1 is violated
in that case.

Algorithm 1 returns a set of MFGs called allTempMFGs which contains MFGs that
have one node at their top level, as shown in Fig. 3. The runtime of a BNN
inference task is primarily affected by the total number of MFGs. Therefore, a
greedy merging algorithm (see Algorithm 3) is proposed to merge within a set
of single-output MFGs that feeds into the same MFG and has the same bottom
level, generates one multiple-output MFG (refer to Fig. 3). The checkLevel
function checks whether the nodes of two MFGs in each logic level meet the
constraint of $|$nodes(MFG1, $l_{i}$) $\cup$ nodes(MFG2, $l_{i}$)$|$ $\leq$ m.
Note that one cannot merge two MFGs that have different bottom levels because
of violating the property described in condition 1. Next, we discuss the main
challenge we faced in compiler design.

Figure 3:  An example of the merging procedure. Algorithm 1 Single-output
Boolean network partitioning

Input: The PO of a Boolean network, $m$ number of LPEs per LPV

Output: A set of MFGs that covers the Boolean network

1: allTempMFGs = $[]$ // a set of all MFGs

2: MFG=findMFG(PO,$m$) // call Alg. 2

3: queue = $[]$

4: queue.append(MFG)

5: while queue is not empty do

6: curMFG = queue.pop(0) // pop the first element

7: allTempMFGs.append(curMFG)

8: for inputNode in input(curMFG) do

9: childMFG=findMFG(inputNode,$m$) // call Alg. 2

10: queue.append(childMFG)

11: return allTempMFGs

Algorithm 2 Function findMFG()

Input: Node $V$, $m$ number of LPEs per LPV

Output: A Graph object maintaining a MFG rooted at $V$

1: MFG = Graph(root=V) // initialize a Graph with root=V

2: queue = $[]$

3: queue.append($V$)

4: visited = emptyset()

5: visited.add($V$)

6: while queue is not empty do

7: curNode = queue.pop(0)

8: MFG.nodeCount[curNode.level]+=1

9: visited.add(curNode)

10: if $|$MFG.nodeCount[curNode.level$|$ $\geq$ $m$ then

11: stopLevel = curNode.level

12: break

13: for child in curNode.children do

14: if child not in visited then

15: visited.add(child)

16: queue.append(child)

17: MFG.bottomLevel = stopLevel + 1

18: return MFG

###  V-B Addressing the width issue

For most of the Boolean networks generated by NullaNet [10], the mapped
netlists have sizes exceeding $n$ logic levels and contain a lot more than $m$
nodes per logic level. We refer to the former problem as the depth issue and
the latter problem as the width issue, which is addressed by the MFG-by-MFG
computing paradigm as follows.

MFGs can be scheduled and processed sequentially with the aid of the snapshot
registers to store the intermediate results generated by $node\\_set(L_{top})$
of each MFG. In a pipelined manner, each MFG requires $L_{top}-L_{bottom}+1$
number of LPVs for its computation. Precisely, the computational resources
allocated to MFG $H$ are $LPV\in[L_{bottom},L_{top}]$. The compute cycle count
is $(L_{top}-L_{bottom}+1)\times t_{c}$ clock cycles where $t_{c}$ is the
summation of one cycle for computation within an LPE and $t_{sw}$ cycles for
data routing (steering) in the deployed switch network. Note that $t_{c}$ is
fixed for different BNN inference tasks. In this paper, $t_{c}=6$ because
$t_{sw}=5$ where a 5-stage non-blocking multicast switch network [20] is used.
The snapshot registers of LPV associated with the $L_{top}+1$ of the MFG
(e.g., $H_{i}$) to be routed, store the intermediate results generated by the
given MFG. The parent MFG (i.e., $H_{j}$, the MFG that has inputs from the
$H_{i}$) starts its computation at $L_{top}+1$ using the data stored in the
snapshot registers.

Algorithm 3 MFG merging algorithm

Input: A set of MFGs

Output: Reduced set of MFGs

1: allMergedMFGs = $[]$

2: rootMFG = the MFG contained PO(s)

3: queue = $[]$

4: queue.append(topMFG)

5: while queue is not empty do

6: curMFG = queue.pop(0) // pop the first element

7: allMergedMFGs.append(curMFG)

8: for all MFG1 and MFG2 in curMFG.children do

9: merge = False

10: if MFG1.bottomLevel == MFG2.bottomLevel then

11: merge = checkLevel(MFG1, MFG2)

12: if merge then

13: mergedChildMFG $=$ MFG1 $\cup$ MFG2

14: queue.append(mergedChildMFG)

15: for all grandchild in MFG1.children and MFG2.children do

16: update grandchild.parent to mergedChildMFG

17: else

18: queue.append(MFG1, MFG2)

19: return allMergedMFGs

An illustrative graph partitioning solution is shown in Fig. 4. In this
example, a Boolean network is partitioned into 10 MFGs, which are shown with
different colors, each is scheduled and processed as shown in the time-space
diagram of Fig. 5. The computation periods of different logic levels are shown
by ${l_{i}}$ after the MFG’s name. For instance, $A1$ represents the
computation of all nodes in logic level 1 of MFG $A$ and it takes 1 cycle.
They are also associated with other two variables, computing cycles (i.e., C
$j$) and LPVs (LPV $k$) to represent the computation of ${l_{i}}$th logic
level of an MFG is performed in LPV $k$ at clock cycle $j$.

Figure 4:  An example of partitioning where $L_{max}=10$. Figure 5:  An
example of scheduling. (Note: $C0$ denotes clock cycle 0)

In the LPU, a LPV stage and the 5 stages of the subsequent switch network form
a block configured by a 6 instruction queues block, in which each memory takes
the read address from its predecessor every cycle. The instruction queues are
accessible through a read address shift register. The instructions
corresponding to a MFG are written into the same address in all instruction
queues associated with all LPVs that are involved in the computations of the
MFG. For instance, instructions for computing MFG $J$, highlighted in pink in
Fig. 5, are written to memLoc5 of the instruction queues associated with LPVs
#8, 9, 10 as shown in Fig. 6.

In Fig. 6, memory locations of instruction queues, which program all the LPVs,
are shown. The color of a memory location corresponds to the color of the MFG
(cf. Fig. 4). All MFGs with $L_{bottom}=0$ receive the PI values needed by
$node\\_set(L_{bottom})$ from the input data buffer. Using a counter, the
compiler ensures that the required PI values are properly stored in different
locations of the input data buffers such that the desired data is accessed
correctly every cycle. This scheme simplifies the address generation compared
to a random-access addressing system. Inputs of other MFGs that have
$L_{bottom}\neq 0$, are provided by at least two child MFGs that have been
computed earlier. Therefore, scheduling the MFGs is equivalent to arranging
the instructions and placing them into proper memory locations.

Figure 6:  Instruction queue configuration. Algorithm 4 MFG scheduling
algorithm

Input: A set of routed MFGs

Output: Memory location to which instructions write

1: memLoc = $INT_{MAX}$

2: topMFG.memLocation() = MemLoc

3: stack = $[]$

4: stack.append(topMFG)

5: while stack not empty do

6: curMFG = stack.pop()

7: curMFG.memLocation() = memLoc

8: if curMFG.parents $\neq$ None then

9: for childMFG in curMFG.children() do

10: stack.append(childMFG)

11: else

12: memLoc = memLoc - 1

13: for all MFG do

14: MFG.memLocation() = MFG.memLocation() - memLoc

The scheduling algorithm shown in algorithm 4 determines the memory locations
for writing the instructions for each MFG. As shown in Fig. 5, each of the
MFGs that satisfies $L_{bottom}\neq 0$ has at least two child MFGs supporting
all the nodes in its $node\\_set(L_{bottom})$. For MFG $H$, we refer to the
child MFGs as $H_{c}=\\{H_{c1},H_{c2},...,H_{cn}\\}$. Each of the MFGs in
$H_{c}$ will generate a subset of $input(node\\_set(L_{bottom}(H)))$;
therefore, we have
$\bigcup_{i=1}^{n}node\\_set(L_{top}(H_{ci}))=input(node\\_set(L_{bottom}(H)))$.
We refer to the last-scheduled child MFG that generates a subset of the
parent’s input nodes (without having to store them in the snapshot registers)
as the most recent child. For instance, MFG $J$’s most recent child is MFG $I$
(see Fig. 5). Note that two MFGs may use the same memLoc value as long as one
of them is the most recent child of the other (e.g., MFG $I$, $J$) because
they are performed on different LPVs. So, the required size of the instruction
queues is reduced.

###  V-C Addressing the depth issue

The depth issue is left to the LPU hardware. If an MFG has $L_{top}$ that is
greater than the total amount of LPVs of a fixed size LPU, the output data
buffer will perform as the snapshot registers of LPV $L_{top}+1$, which is the
LPV that does not physically exist. Instead, LPV 0 resorts to the circulation
mechanism to perform the functionality of LPV $L_{top}+1$. The compiler is
responsible for detecting potential depth issue and relocating the
instructions accordingly. The compiler notifies the hardware when to feed the
intermediate data stored in the output data buffer back to the LPV 0. Such
data goes through the pipeline for multiple rounds of computation to complete
the computation of all logic levels of the given FFCL.

##  VI Experimental Results

For evaluation purposes, we targeted a high-end Virtex® UltraScale+ FPGA
(Xilinx VU9P FPGA , which is available in the cloud as the AWS EC2 F1
instance). We include the FPGA prototyping results since the SoA
implementations use the same FPGA. The hardware metrics are reported in table
I for LPV count = 16.

Our benchmarked models can be categorized into two groups, i) models for high-
accuracy requirement (i.e., large models), and ii) models for high-throughput
requirement (i.e., tiny models). In the first group, we study VGG-16, VGG-like
model used in ChewBaccaNN[2], LENET5 on the MNIST dataset, and MLPMixers [15]
on the CIFAR-10 dataset. We also evaluate our logic processor against extreme-
throughput tasks in physics and cybersecurity such as jet substructure
classification (JSC) [5] and network intrusion detection (NID) [9]. We used
UNSWNB15 dataset to compare our logic processor with other implementations. We
employed the same preprocessed training and testing data as that of Murovic et
al. [9] which has 593 binary features corresponding to 49 original features
and two output classes.

For MLPMixers, the resolution of the input image is 32*32, and the patch size
that the experiments are based on is 4*4. So, we have 64 non-overlapping image
patches that are mapped to a hidden dimension $C$ which is 128 and 192 for
small design (S) and Base design (B), respectively. $D_{S}$ and $D_{C}$ are
tunable hidden widths in the token-mixing and channel-mixing MLPs,
respectively. $D_{S}$ and $D_{C}$ are 64 (96) and 512 (768) for S (B) design.
There are 8 and 12 mixing layers in S and B designs, respectively.

TABLE I:  Resource utilization of design of LPV count = 16. FF(%) | LUT(%) | BRAM(%) | FREQ
---|---|---|---
478K(20.2%) | 433K(36.7%) | 12240K (15.8%) | 333MHz

###  VI-A Effect of the MFG merging procedure

To show the efficacy of the proposed merging procedure described in Section V,
we compare the performance of our logic processor with and without
incorporating the merging procedure. Results are shown in Fig. 7 and 8. Fig.
7(a) shows the clock cycle count for computing layers [2:13] of VGG16 with and
without the merging procedure. Fig. 7(b) shows the total number of MFGs
obtained from the proposed algorithm with and without the merging procedure.
The results confirm the superior performance after applying the merging
procedure and also demonstrate the high correlation between computation time
and the MFG count. To further assess the effectiveness of the proposed merging
algorithm, we apply it to all models used in this study and summarize the
results in Fig. 8. As can be seen, the throughput is improved by 5.2x on
average while the MFG count can be reduced up to 9.4x.

(a) Computation time

(b) MFG count

Figure 7: a) Computation time and b) MFG count of VGG16 layers before and
after applying merging algorithm.

###  VI-B Comparison Between MAC-based, XNOR-based and NullaNet-based FPGA
Implementation of NNs

The VGG16 is a huge network and it has about 138 million parameters. We
implement intermediate convolutional layers 2-13 in VGG16 using the proposed
framework and fixed-function combinational logic functions. As a baseline for
the SoA generic MAC array-based accelerator for the layers realized using
conventional MAC calculations, we used the open-source implementation of [14]
with some improvements proposed in [12]. We use FINN [16] for our XNOR-based
baseline. We improve this implementation by packing operations. We also use
the NullaDSP model [12] as another baseline for mapping FFCL generated by
NullaNet to the programmable DSP blocks where it can fit any FFCL with any
size. We use the best results of each implementation reported in [12] and
compare them to our proposed architecture in tables II and III. In the case of
JSC and NID, we use the implementation and the associated performance reported
in LogicNets [17], Google and CERN’s optimized implementation [8], and the
implementation presented in [1].

As illustrated in the tables II, our implementation shows superior performance
compared to other implementations. The LPU and XNOR implementation achieves
significant saving, especially in large DNN model like VGG16, since we keep
all intermediate data on on-chip memories and there is no cost associated with
off-chip memories while this is not the case for MAC-based and NullaDSP
implementation. We achieved 14.01x(33.43x), 4.86x(3.93x), and 1.95x(4.89x) in
performance improvement on VGG16 (LENET-5) inference compared to MAC-based,
NullaDSP, XNOR-based implementations, respectively.

LogicNets [17] have higher frames per second (FPS) than our design. However,
they cannot use the same hardware for the other models since they realized
each model as a customized hard network of logic gates (as in random logic
blocks). Whereas, our design offers programmable logic processors that can
perform the required logic gate operations of any logic (computation) graphs.
The former realization is ideal for building a highly efficient, yet
unchangeable, inference engine whereas the latter one is desirable for
accelerating the training process and for building inference engines that can
be updated after they are deployed in the field. Note that NullaNet Tiny [11]
is our upstream for generating FFCL blocks and presents a similar
implementation as LogicNets [17] and outperforms the LogicNets in similar
settings on the same benchmarks.

(a) Throughput

(b) MFG count

Figure 8: a) Throughput and b) MFG count before and after applying merging algorithm. TABLE II:  FPS Comparison between the different implementation of models with high accuracy requirements. LPV count in LPU is 16. | MAC | NullaDSP | XNOR | LPU
---|---|---|---|---
VGG16 | 0.12K | 0.33K | 0.83K | 103.99K
LENET5 | 0.48K | 4.12K | 3.31K | 1035.60K
MLPMixer-S/4 | 4.17K | - | 50.00K | 179.23K
MLPMixer-B/4 | 0.88K | - | 16.67K | 102.01K
TABLE III:  FPS Comparison between the different implementation of models with high throughput requirements. LPV count in LPU is 16. |  LogicNets [17] |  Google+CERN[8] | [1] | LPU
---|---|---|---|---
NID | 95.24M | - | 49.58M | 8.39M
JSC-M | 2995.00M | - | - | 0.69M
JSC-L | 76.92M | 76.92M | - | 0.21M
Figure 9:  Inference time of VGG16 and LENET5.

###  VI-C Ablation study with LPV count

To determine the influence of the LPV count on the performance of the
presented logic processor, we conducted experiments with different LPV counts.
As shown in Fig. 9, the inference time decreases as we increase the number of
LPVs. The influence of the LPV count is saturated after a while. To conduct a
comparative analysis on NullaDSP [12] against the LPU, we benchmark the
effective LPV threshold, which is defined as the minimum number of LPVs that
an LPU needs to achieve performance equivalent to NullaDSP. As shown in Fig.
9, we need at least 2 LPVs to achieve such performance for the case of VGG16.

##  VII Conclusion

The proposed logic processor offers a novel hardware design approach afforded
by the presented compiler resulting in efficient partitioning and mapping of a
given neural network model in the format of fixed-function combinational
logic. In future work, we plan to intend to explore the heterogeneous
architecture where the number of LPEs per LPVs and their following switch
networks will not be the same for all LPVs. Also, it is worth trying multiple
LPUs that can be assembled in parallel or series configurations.

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