LLVM IR for the GenX backend¶
- Introduction
- LLVM IR representation of EU code
- Vector regions
- Predicates and predication
- Non-GenX intrinsics
- GenX intrinsics
- Region/element access intrinsics
- ALU type conversion intrinsics
- Modifier intrinsics
- Boolean reduction intrinsics
- SIMD control flow intrinsics
- ALU intrinsics
- add
llvm.genx.*add.sat
: add instruction with saturation- addc
- asr
llvm.genx.*avg
: integer averaging, no saturationllvm.genx.*avg.sat
: integer averaging with saturationllvm.genx.*bfe
: bitfield extractllvm.genx.bfi
: bitfield insertllvm.genx.bfrev
: reverse bitsllvm.genx.cbit
: count set bits- cmp
llvm.genx.cos
: cos instruction- div
llvm.genx.ieee.div
: Divide, IEEE variantllvm.genx.dp2
: dp2 instruction (dot product on groups of 4 elements)llvm.genx.dp3
: dp3 instruction (dot product on groups of 3 elements)llvm.genx.dp4
: dp4 instruction (dot product on groups of 4 elements)llvm.genx.dph
: dph instruction (dot product homogenous)llvm.genx.exp
: base 2 exponentllvm.genx.*fbh
: find bit highllvm.genx.fbl
: find bit lowllvm.genx.frc
: fractional partllvm.genx.inv
: reciprocalllvm.genx.line
: linear equationllvm.genx.log
: base 2 logarithmllvm.genx.lrp
: linear interpolationllvm.genx.lzd
: leading zero detectionllvm.genx.*mad
: mad instruction, no saturationllvm.genx.*mad.sat
: mad instruction with saturationllvm.genx.*max
: max instructionllvm.genx.*min
: min instruction- mod
- mul
llvm.genx.*mul
: mul instruction, no saturationllvm.genx.*mul.sat
: mul instruction with saturationllvm.genx.*mulh
: mulh instruction, no saturation- not
- or
llvm.genx.pln
: plane equationllvm.genx.pow
: powerllvm.genx.rndd
: round downllvm.genx.rnde
: round to evenllvm.genx.rndu
: round upllvm.genx.rndz
: round to zerollvm.genx.rsqrt
: reciprocal square rootllvm.genx.*sad2
: two-wide sum of absolute differencesllvm.genx.*sad2add
: two-wide sum of absolute differences and addllvm.genx.*sad2add.sat
: two-wide sum of absolute differences and add, saturatedllvm.genx.*shl
: shl instruction, no saturationllvm.genx.*shl.sat
: shl instruction with saturation- shr
llvm.genx.sin
: reciprocal square rootllvm.genx.sqrt
: reciprocal square rootllvm.genx.ieee.sqrt
: reciprocal square root, IEEE variantllvm.genx.dp4a
: dp4a instruction (Dot Product 4 Accumulate)- add3
llvm.genx.*add3
: add3 instruction without saturationllvm.genx.*add3.sat
: add3 instruction with saturation- bfn
llvm.genx.bfn
: bfn instruction- subb
- xor
- vISA reserved register intrinsics
llvm.genx.thread.*
: read thread ID registerllvm.genx.group.id.*
: read group ID registerllvm.genx.timestamp
: read vISA v11 (%timestamp)llvm.genx.r0
: read vISA v12 (%r0)llvm.genx.sr0
: read vISA v13 (%sr0)llvm.genx.set.sr0.2
: write vISA v13(0, 2) (%sr0.2)llvm.genx.get.color
: read color value of the thread originllvm.genx.get.hwid
: read hw_id valuellvm.genx.set.pause
: set the pause register (v11.4)llvm.genx.dummy.mov
: insert a dummy mov to v0
- Shared function intrinsics
llvm.genx.dword.atomic.*
: dword atomic with binary operatorllvm.genx.dword.atomic.*
: dword atomic with fmin/fmax operationllvm.genx.dword.atomic.*
: dword atomic with inc/dec operationllvm.genx.dword.atomic.cmpxchg
: vISA DWORD_ATOMIC CMPXCHG instructionllvm.genx.dword.atomic.fcmpwr
: vISA DWORD_ATOMIC FCMPWR instructionllvm.genx.typed.atomic.*
: atomic typed with binary operatorllvm.genx.typed.atomic.*
: atomic typed with fmin/fmax operationllvm.genx.typed.atomic.*
: atomic typed with inc/dec operationllvm.genx.typed.atomic.cmpxchg
: vISA TYPED_ATOMIC CMPXCHG instructionllvm.genx.typed.atomic.fcmpwr
: vISA TYPED_ATOMIC FCMPWR instructionllvm.genx.gather.orig
: vISA GATHER instructionllvm.genx.gather.private
: CMC internal, no VISAllvm.genx.gather.scaled
: vISA GATHER_SCALED instructionllvm.genx.gather4.orig
: vISA GATHER4 instructionllvm.genx.gather4.scaled
: vISA GATHER4_SCALED instructionllvm.genx.gather4.typed
: vISA GATHER4_TYPED instructionllvm.genx.media.ld
: vISA MEDIA_LD instructionllvm.genx.media.st
: vISA MEDIA_ST instructionllvm.genx.oword.ld*
: oword load instructionllvm.genx.oword.st
: vISA OWORD_ST instructionllvm.genx.scatter.orig
: vISA SCATTER instructionllvm.genx.scatter.private
: CM internal, no VISAllvm.genx.scatter.scaled
: vISA SCATTER_SCALED instructionllvm.genx.scatter4.orig
: vISA SCATTER4 instructionllvm.genx.scatter4.scaled
: vISA SCATTER4_SCALED instructionllvm.genx.scatter4.typed
: vISA SCATTER4_TYPED instructionllvm.genx.transpose.ld
: vISA TRANSPOSE_LD instructionllvm.genx.untyped.atomic.*
: vISA UNTYPED_ATOMIC with binary operatorllvm.genx.untyped.atomic.*
: vISA UNTYPED_ATOMIC with inc/decllvm.genx.untyped.atomic.cmpxchg
: vISA UNTYPED_ATOMIC CMPXCHG instructionllvm.genx.svm.block.ld*
: vISA SVM BLOCK_LD instructionllvm.genx.svm.block.st
: vISA SVM BLOCK_ST instructionllvm.genx.svm.gather
: vISA SVM GATHER instructionllvm.genx.svm.gather4.scaled
: vISA SVM GATHER4_SCALED instructionllvm.genx.svm.scatter
: vISA SVM SCATTER instructionllvm.genx.svm.scatter4.scaled
: vISA SVM SCATTER4_SCALED instructionllvm.genx.svm.atomic.*
: vISA SVM_ATOMIC with binary operatorllvm.genx.svm.atomic.*
: vISA SVM_ATOMIC with inc/decllvm.genx.svm.atomic.cmpxchg
: vISA SVM_ATOMIC CMPXCHG instructionllvm.genx.svm.atomic.*
: vISA SVM_ATOMIC with binary operatorllvm.genx.svm.atomic.fcmpwr
: vISA SVM_ATOMIC FCMPWR instructionllvm.genx.load
: vISA LOAD (sampler load) instructionllvm.genx.sample
: vISA SAMPLE instructionllvm.genx.sample.unorm
: vISA SAMPLE_UNORM instructionllvm.genx.3d.sample
: vISA 3D_SAMPLE instructionllvm.genx.3d.load
: vISA 3D_LOAD instructionllvm.genx.avs
: vISA AVS instructionllvm.genx.barrier
: vISA BARRIER instructionllvm.genx.sbarrier
: vISA SBARRIER instructionllvm.genx.cache.flush
: vISA CACHE_FLUSH instructionllvm.genx.fence
: vISA FENCE instructionllvm.genx.wait
: vISA WAIT instructionllvm.genx.yield
: vISA YIELD instructionllvm.genx.raw.send
: vISA RAW_SEND instructionllvm.genx.raw.send.noresult
: vISA RAW_SEND instruction with no resultllvm.genx.raw.sends
: vISA RAW_SENDS instructionllvm.genx.raw.sends.noresult
: vISA RAW_SENDS instruction with no resultllvm.genx.va.convolve2d
vISA VA 2d Convolve instructionllvm.genx.va.hdc.convolve2d
vISA VA HDC 2d Convolve instructionllvm.genx.va.erode
vISA VA Erode instructionllvm.genx.va.hdc.erode
vISA VA HDC Erode instructionllvm.genx.va.dilate
vISA VA Dilate instructionllvm.genx.va.hdc.dilate
vISA VA HDC Dilate instructionllvm.genx.va.minmax
vISA MinMax instructionllvm.genx.va.minmax.filter
vISA MinMax Filter instructionllvm.genx.va.hdc.minmax.filter
vISA HDC MinMax Filter instructionllvm.genx.va.bool.centroid
vISA Boolean Centroid instructionllvm.genx.va.centroid
vISA Centroid instructionllvm.genx.va.1d.convolve.horizontal
vISA 1d convolve horizontal instructionllvm.genx.va.hdc.1d.convolve.horizontal
vISA HDC 1d convolve horizontal instructionllvm.genx.va.1d.convolve.vertical
vISA 1d convolve vertical instructionllvm.genx.va.hdc.1d.convolve.vertical
vISA HDC 1d convolve vertical instructionllvm.genx.va.1pixel.convolve
vISA 1 Pixel Convolve instructionllvm.genx.va.hdc.1pixel.convolve
vISA HDC 1 Pixel Convolve instructionllvm.genx.va.1pixel.convolve.1x1mode
vISA 1 Pixel Convolve (1x1 mode) instructionllvm.genx.va.lbp.creation
vISA LBP Creation instructionllvm.genx.va.hdc.lbp.creation
vISA HDC LBP Creation instructionllvm.genx.va.lbp.correlation
vISA LBP Correlation instructionllvm.genx.va.hdc.lbp.correlation
vISA HDC LBP Correlation instructionllvm.genx.va.correlation.search
vISA Correlation Search instructionllvm.genx.va.flood.fill
vISA Flood Fill instruction
Introduction¶
The GenX backend accepts LLVM intermediate representation with certain restrictions, and with additional GenX-specific intrinsics.
LLVM IR representation of EU code¶
Whole thread representation¶
When using LLVM with the GenX backend, the LLVM IR represents execution on a whole EU thread. This is distinct from IGC and Beignet (the OpenCL compiler for the Intel open source driver), in which the LLVM IR represents just a single work item, and a later stage of the compiler after LLVM IR parallelizes that into simd4,8,16 or 32.
The GenX backend thus gives more flexibility for a client that needs full control over what is executed in the EU thread for one of these reasons:
- the compiler needs to expose that control in the language (like CM);
- the compiler wants to do some parallelization, but in a more flexible way (e.g. different SIMD width for different parts of the code). This could be done as an LLVM pass before reaching the GenX backend, or it could be done even before reaching LLVM;
- the compiler wants to expose “cross lane” functionality, where an algorithm can be executed in parallel within a single EU thread, but the separate lanes need to access each other’s data at some points.
Linkage¶
A kernel is represented by a function with dllexport
linkage.
A non-kernel function is represented by a function with public
linkage.
A subroutine is represented by a function with internal
linkage. A subroutine
is allowed to be accessed from multiple kernels and non-kernel functions; the
GenX backend clones such a subroutine so it appears with each kernel and function
that uses it in the vISA.
No other linkage is supported.
Global variables are not supported. (The CM compiler has its own CMABI pass that works around this by passing such variable into and out of any subroutine that uses it.)
Kernel information¶
The genx.kernels named metadata node contains a metadata node for each kernel, containing:
- 0: reference to Function
- 1: kernel name
- 2: asm name
- 3: kernel argument kinds (i32 for each kernel argument)
- 4: slm size in bytes
- 5: kernel argument offsets (i32 for each kernel argument)
Types¶
Only fundamental types that correspond to Gen types are allowed:
- i1 for predicate
- i8 for b/ub
- i16 for w/uw
- half for hf
- i32 for d/ud
- float for f
- i64 for q/uq
- double for df
Arbitrary size vectors of these types are allowed.
Arithmetic/logic operator¶
There is no vector width restriction on operands and result of an arithmetic/logic operator.
Where the operands and result have the same type, and no saturation is
required, the corresponding LLVM IR instruction can be used, for example
add
.
A floating point operation where saturation is required is represented by
the LLVM IR instruction followed by the llvm.genx.sat
intrinsic.
For an integer operation, vISA allows the operands to have one type and the result to have a different type. This is represented by an intrinsic, typically with signed/unsigned variants and variants with saturation. Saturation cannot be represented by a separate intrinsic as for floating point, because the intermediate result in the EU’s ALU has one more bit than the execution size.
An intrinsic is also required where the operator does not have an LLVM IR
instruction equivalent, such as min
.
Load and store¶
Load and store instructions are allowed only to load/store from/to a static alloca, i.e. ones that are removed by a mem2reg pass.
Vector regions¶
Introduction to region-based addressing¶
The Gen hardware, and thus vISA, provide the ability for a vector operand of an instruction to be a region within a register.
1D region¶
A 1D region has the following parameters:
- The execution size is the number of elements in the region. This is determined by the instruction in which the operand appears.
- The horizontal stride (sometimes called just the stride) is the number of elements to step between each element of the region. This is 1 for a contiguous region, but can take other values, including 0 (in a source operand only) to splat the same scalar value across the whole operand.
- The start index indicates which element within the register is the start of the region.
The stride must be a constant. The start index can be a variable (giving an indirect operand).
Here is a simple contiguous 1D region (yellow), with execution size 4, stride 1 and start index 3, in a register with 8 elements:
Here is a non-contiguous 1D region, with execution size 4, stride 2 and start index 3, in a register with 16 elements:
2D region¶
A 2D region has multiple rows where each row is a 1D region. It has the following parameters:
- The execution size is the number of elements in the region. This is determined by the instruction in which the operand appears.
- The vertical stride (or vstride) is the number of elements to step between the start of one row and the start of the next row. It can be 0 (in a source operand only) to repeat the same row multiple times.
- The width is the number of elements per row.
- The horizontal stride (or stride) is the number of elements to step between each element of the region within a row. This is 1 for a contiguous row, but can take other values, including 0 (in a source operand only) to splat the same scalar value across the whole row.
- The start index indicates which element within the register is the start of the region.
The vstride, width and stride must be a constant. The start index can be a scalar variable (giving an indirect operand) or a vector variable with an element per row of the region (giving a multi-indirect operand).
Here is a 2D region with contiguous rows, with:
- execution size 8 (the number of elements in the region)
- vstride 8 (the step between the start of one row (3) and the start of the next (11)
- width 4 (the number of elements in a row)
- stride 1 (the step between each element in a row)
- start index 3
Here is a 2D region with:
- execution size 9 (the number of elements in the region)
- vstride 7 (the step between the start of one row (8) and the start of the next (15)
- width 3 (the number of elements in a row)
- stride 3 (the step between each element in a row)
- start index 8
Notes¶
Some points that arise from these examples:
- The execution size must be a multiple of the width. Execution size divided by width is the number of rows in a 2D region. If the number of rows is 1, then it is a 1D region.
- Gen and vISA only support powers of two within certain limits for the region parameters other than start index. Also 2D regions are allowed only in a source operand. But source languages like CM using regions do not have these restrictions, and the compiler needs to allow for the more general case.
- The matrix representation shown in the last two examples is not a property of the register from/into which the region is read/written. Rather, it is a property of the region parameters. We show a matrix whose width is the vstride of the region. In the last example, the register is not even a multiple of vstride number of elements, so we have some left-over elements at the bottom.
Region access in LLVM IR¶
Region access is represented in LLVM IR by intrinsics with the same region parameters as above. The representation is close to the hardware capabilities, but:
- The vISA/hardware restrictions on the region parameters being powers of 2 within certain ranges are not initially imposed. The GenX backend includes a legalization pass that imposes these restrictions, and other gen-specific ones such as not being allowed to cross 2 GRF boundaries and not being allowed a 2D region as a destination, by splitting up region accesses.
- There is an extra parent width region parameter used for optimizations when the GenX backend collapses and legalizes region accesses.
- To make the parent width parameter effective when a variable start index is involved, a compiler frontend should compile a 2D region access as two separate accesses, one for the rows and one for the columns within the rows.
The restriction still needs to be imposed that the region is entirely contained within the vector it is being read from or written to, otherwise undefined behavior ensues at runtime.
Reading a region¶
Reading a region, that is extracting certain elements from a vector to make a
new smaller vector, is represented by the llvm.genx.rdregioni
or
llvm.genx.rdregionf
intrinsic. (There are integer and fp variants simply
because the tablegen language for declaring an overloaded intrinsic does not
allow an “any scalar or vector type”.
The operands to this intrinsic are:
- the vector being read from;
- vstride (ignored for a 1D region, that is width == execution size);
- width;
- stride;
- start index;
- parent width (see below).
The execution size is implied by the vector width of the return value of the intrinsic call.
The vstride, width and stride are expressed in elements. But the start index is expressed in bytes, as this is what the hardware does in the variable index case.
A read from the first example region from above:
is represented by the following LLVM IR (assuming the start index is constant, and the element type is i32):
%v1 = <8 x i32> something
%region1 = call <4 x i32> @llvm.genx.rdregioni.v4i32.v8i32(<8 x i32> %v1, i32 0, i32 4, i32 1, i16 12, i32 undef)
The vstride is set to 0, but is ignored because it is a 1D region.
The width is 4 (elements) and the stride is 1.
The start index is 12, but remember this is in bytes, so it means 3 elements. (The elements have type i32.)
A read from the fourth example region from above:
is represented by this LLVM IR (assuming constant start index and i32 element type):
%v2 = <30 x i32> something
%region2 = call <9 x i32> @llvm.genx.rdregioni.v9i32.v30i32(<30 x i32> %v2, i32 7, i32 3, i32 2, i16 32)
With:
- execution size 9 (the number of elements in the region)
- vstride 7 (the step between the start of one row (8) and the start of the next (15)
- width 3 (the number of elements in a row)
- stride 3 (the step between each element in a row)
- start index 32 bytes, which is 8 elements.
The diagram above shows the input vector %v2 as a matrix of width 7 with two elements left over in a partial row. This 7 is not a property of the input vector value, which is just a vector (LLVM IR does not represent matrices). Instead it is the vstride of the region we are reading.
Writing a region¶
Writing a region, that is inserting the elements of a vector into certain
positions of another vector, yielding a new value for the latter vector,
is represented by the llvm.genx.wrregioni
or
llvm.genx.wrregionf
intrinsic. (There are integer and fp variants simply
because the tablegen language for declaring an overloaded intrinsic does not
allow an “any scalar or vector type”.
In SSA, each value is defined exactly once. Since we are representing a vector value as an LLVM IR value, the only way of representing a write to a region, which is a partial write, is for the operation to take the old value of the vector as an input, and to return the updated value of the vector. It is then up to the GenX backend to ensure that the two values are allocated to the same register.
The operands to this intrinsic are:
- the “old value” of the vector being written into;
- the “new value”, that is, the vector or scalar value to write into the region;
- vstride;
- width;
- stride;
- start index;
- parent width (see below);
- mask.
The execution size is the vector width of the “new value” input. For a 1D region (width == execution size), vstride is ignored.
As above in llvm.genx.rdregion, the vstride, width and stride are expressed in elements, but the start index is expressed in bytes.
Using the same two example regions as above in llvm.genx.rdregion:
Writing the elements of %region3 into the region in %v3, generating a new value %v3.new is represented by:
%v3 = <8 x i32> something
%region3 = <4 x i32> something
%v3.new = call <8 x i32> @llvm.genx.wrregion.v8i32.v4i32.i1(<8 x i32> %v3, <4 x i32> %region3, i32 0, i32 4, i32 1, i16 12, i32 undef, i1 1)
The .v8i32.v4i32.i1 decoration on the intrinsic name arises from LLVM’s intrinsic overloading mechanism. The v8i32 is the type of the return value, and the v4i32 is the type of the value being written in to the region. The i1 is the type of the mask operand; see below.
The vstride is set to 0, but is ignored because it is a 1D region.
The width is 4 (elements) and the stride is 1.
The start index is 12, but remember this is in bytes, so it means 3 elements. (The elements have type i32.)
Writing the elements of %region4 into the region in %v4, generating a new value %v4.new is represented by:
%v4 = <30 x i32> something
%region4 = <9 x i32> something
%v4.new = call <30 x i32> @llvm.genx.wrregion.v30i32.v9i32.i1(<30 x i32> %v4, <9 x i32> %region4, i32 7, i32 3, i32 2, i16 32, i32 undef, i1 1)
With:
- execution size 9 (the number of elements in the region)
- vstride 7 (the step between the start of one row (8) and the start of the next (15)
- width 3 (the number of elements in a row)
- stride 3 (the step between each element in a row)
- start index 32 bytes, which is 8 elements.
The mask operand¶
The wrregion* intrinsics have an extra mask operand. This is used to control which elements in the region are actually written, for use in predication and SIMD control flow.
Most generally, the mask operand is a vector of i1 with the same vector width as the value being written in to the region, and it is variable. If any element of the mask is 0, the corresponding element of the value is not written in to the region, leaving that element unchanged.
The most common case, used when there is no predication, is that the mask is all ones. As a shorthand, this is represented by a single constant i1 value of 1, rather than the whole vector.
Single element region¶
A single element could be a scalar value or a 1-vector. It is convenient to allow both in LLVM IR, because CM allows both as distinct types.
The rdregion and wrregion intrinsics are defined such that a single element region can be represented as either a scalar or a 1-vector. However, for the scalar case, it is recommended to use the LLVM IR instructions extractelement and insertelement instead, as core LLVM optimizations understand them.
The parent width operand¶
For a 2D region, certain parts of the GenX backend can optimize better if it is known that a row of the region cannot cross certain boundaries:
- Collapsing two 2D regions is possible only if it is known that a row of the inner 2D region cannot cross a row boundary of the outer 2D region.
- Knowing that a row of a 2D region cannot cross a GRF boundary can help to avoid splitting it up so much in legalization.
For a region with a constant start index, this can all be calculated from the start index and region parameters. For a region with a variable start index, the parent width operand is set to value N to make a statement that the semantics of the language being compiled say that a row of the region cannot cross a multiple of N boundary.
Predicates and predication¶
Certain vector operations can be predicated, that is, a vector of i1 predicate controls whether the corresponding element of the operation is written into its result element.
LLVM IR already has select
with a vector condition.
As outlined above, the wrregion intrinsics have a mask operand. If a bit is not set in the mask, then the corresponding element of the “new value” input is not written into the result.
The intrinsics corresponding to predicated send messages (e.g. gather), and the raw send intrinsics, have a predicate operand.
Non-GenX intrinsics¶
In general the GenX backend does not implement non-GenX intrinsics, with the following exceptions:
llvm.uadd.with.overflow
– the GenX backend does not implement the other arithmetic-with-overflow intrinsics, but I found a case where LLVM was transforming a CM program to use this one, so I had to implement it.llvm.fma
– this intrinsic is generated in the GenXPatternMatch pass, but I think the GenX backend would be able to cope with it being in the IR already.
GenX intrinsics¶
Region/element access intrinsics¶
llvm.genx.rdregion*
: read a region, direct or single-indirect¶
llvm.genx.rdregioni
: integer element type (not i1)llvm.genx.rdregionf
: fp element type- arg0: vector to read region out of
- arg1: i32 vstride in elements, constant
- arg2: i32 width in elements, constant
- arg3: i32 stride in elements, constant
- arg4: i16 or vXi16 offset in bytes
- arg5: i32 parent width, constant, ignored if offset is constant
- Return value: the region extracted
The return type must be a vector with the same element type as the input vector, and number of elements giving the total size of the region. A scalar can be used instead of a 1-vector.
There are two variants, an integer one and an fp one, because the intrinsic declaration language does not let us declare the return type as any scalar or vector int or fp type.
The element type must be an integral power of two number of bytes up to and including 8 bytes in size, thus one of i8, i16, i32, i64, half, float, double. In particular i1 is not allowed. The width must be non-zero and must divide the total size evenly.
There is no requirement on vstride, width, stride or total size being a power of two or having any maximum.
The offset in bytes arg can be i16 or vector of i16. If a vector, then its vector width must be the height of the region, i.e. the total size of the region divided by the width.
The parent width arg is ignored if the offset arg is constant. If the offset arg is variable, then a non-undef parent width is a statement that the value of offset is such that a row of the region does not cross a multiple of parent width boundary. This is used by the backend to determine whether the region can be collapsed into another region.
llvm.genx.wrregion*
: write a region, direct or single-indirect¶
llvm.genx.wrregioni
: integer element type (not i1)llvm.genx.wrregionf
: fp element type- arg0: vector to write region in to
- arg1: subvector or scalar to write into the region
- arg2: i32 vstride in elements, constant
- arg3: i32 width in elements, constant
- arg4: i32 stride in elements, constant
- arg5: i16 or vXi16 offset in bytes
- arg6: i32 parent width, constant, ignored if offset is constant
- arg7: vector of i1 mask, or scalar i1
- Return value: the updated vector with the region modified
The return type must be a vector with the same type as the arg0 vector. The arg1 subvector must have the same element type as the arg0 vector and be no larger. Arg1 can be a scalar if the number of elements in the subregion is 1.
There are two variants, an integer one and an fp one, because the intrinsic declaration language does not let us declare the arg1 type as any scalar or vector int or fp type.
The element type must be an integral power of two number of bytes up to and including 8 bytes in size, thus one of i8, i16, i32, i64, half, float, double. In particular i1 is not allowed. The width must be non-zero and must divide the total size evenly.
The arg7 mask is a vector of booleans, exactly as wide as the arg1 subvector, such that an element of the subvector is written into its place in the vector only if the corresponding element of the mask is true. Alternatively, arg7 can be a single i1 constant with value 1, meaning that the wrregion is unconditional.
There is no requirement on vstride, width, stride or total size being a power of two or having any maximum.
The offset in bytes arg can be i16 or vector of i16. If a vector, then its vector width must be the height of the region, i.e. the total size of the region divided by the width.
After lowering, the arg1 subvector to write can be a scalar of the same type as an element of arg0, indicating that the region has one element. (Lowering lowers an insertelement to this type of wrregion.)
The parent width arg is ignored if the offset arg is constant. If the offset arg is variable, then a non-undef parent width is a statement that the value of offset is such that a row of the region does not cross a multiple of parent width boundary. This is used by the backend to determine whether the region can be collapsed into another region.
llvm.genx.vstore
: store a vector value into memory¶
This intrinsic has the exact semantics of an llvm store instruction. It is designed for reading and writing a pass-by-reference argument and it stops llvm optimizations from optimizing away accesses to the pass-by-reference arguments.
- arg0: the memory to be accessed
llvm.genx.vload
: load a vector value from memory¶
This intrinsic has the exact semantics of an llvm load instruction. It is designed for reading and writing a pass-by-reference argument and it stops llvm optimizations from optimizing away accesses to the pass-by-reference arguments.
- arg0: the memory to be accessed
- Return value: the vector value read
ALU type conversion intrinsics¶
llvm.genx.fptosi.sat
: convert floating point to signed integer with saturate¶
- arg0: value to saturate, any scalar or vector floating point type
- Return value: converted value, any scalar or vector integer type
- (treated as signed) with same vector width as arg0
llvm.genx.fptoui.sat
: convert floating point to unsigned integer with saturate¶
- arg0: value to saturate, any scalar or vector floating point type
- Return value: converted value, any scalar or vector integer type
- (treated as unsigned) with same vector width as arg0
llvm.genx.sat
: floating point saturate¶
- arg0: value to saturate, any scalar or vector floating point type
- Return value: saturated value, same type as arg0
We represent floating point saturation by simply calling this intrinsic on the result of a floating point operation. This works because the value before saturation fits in the same type.
We do not have an equivalent for integer saturation, because the before-saturation value needs a bigger integer type than the result. Instead, any integer operation that supports saturation needs an intrinsic for the saturating variant.
llvm.genx.*trunc.sat
: integer truncation with saturation¶
llvm.genx.sstrunc.sat
: signed result, signed operandllvm.genx.sutrunc.sat
: signed result, unsigned operandllvm.genx.ustrunc.sat
: unsigned result, signed operandllvm.genx.uutrunc.sat
: unsigned result, unsigned operand- arg0: value to truncate, any scalar or vector integer type
- Return value: truncated value, any scalar or vector integer type
- with same vector width as arg0
Modifier intrinsics¶
Abs is the only source modifier that is represented by an intrinsic; neg(x) uses 0-x, and not(x) uses x^-1.
llvm.genx.abs*
: take absolute value¶
llvm.genx.absf
: abs modifier for fpllvm.genx.absi
: abs modifier for integer- arg0: input value, scalar/vector
- Return value: result, same type
Boolean reduction intrinsics¶
llvm.genx.all
: true if all input elements are true¶
- arg0: input value: v*i1
- Return value: i1 result
llvm.genx.any
: true if any input element is true¶
- arg0: input value: v*i1
- Return value: i1 result
SIMD control flow intrinsics¶
goto
and join
instructions are represented by llvm.genx.simdcf.goto
and llvm.genx.simdcf.join
intrinsics.
The BSpec model¶
The BSpec defines SIMD control flow in terms of each of the 32 channels having a PcIP (per-channel instruction pointer), which determines where a disabled channel will be re-enabled:
A goto has two targets, UIP (update IP) and JIP (join IP).
A (forward) goto evaluates its vector condition, and, for each channel that is enabled and the condition is true, it sets the channel’s PcIP to UIP, to mark that the channel is disabled until execution reaches the join instruction at UIP. If, after disabling channels in this way, no channels are left enabled, then execution jumps to JIP.
UIP and JIP may be different, as there may be channels already disabled from an earlier goto with their PcIPs set to an earlier point than the present goto’s UIP. So JIP needs to be set to the earliest point that a channel could have its PcIP pointing at.
There is also a backward goto variant for use in a conditional loop back edge (end of a do..while loop). It works the same as a forward goto over an unconditional jump back to the top of the loop.
A join has one target, JIP. It reenables all channels that have PcIP set to this join. If there are still no channels enabled, it jumps to JIP.
Each instruction’s register write-back is gated by which channels are enabled, unless the instruction has a nomask bit set. This is in addition to optionally being gated by a predicate.
The action of the channel enable mask (and predicate) in a send depends on the shared function. Some (e.g. gather and scatter) have the expected semantics where disabled channels do not participate in the memory read/write, and (in the case of a read) do not update that channel’s result.
This scheme allows arbitrarily unstructured SIMD control flow. For it to work and guarantee convergence, it is sufficient (not sure if it is necessary) for there to be a linear chain of join points, and each goto/join’s UIP and JIP are forward in the chain, and JIPs are set correctly so it is not possible for execution to “miss out” a join point where a channel should have been enabled. (As above, a backward goto is handled in this model by being considered a forward goto over a backward unconditional jump.)
In Gen code, this linear chain of join points does not actually have to be in program order, as long as the join point order with forward UIP and JIP is derivable.
In vISA, the linear chain of join points does have to be in program order. vISA does not encode the JIP of a goto/join; instead it derives it itself. Also, vISA uses whether a goto’s target is before or after to encode whether it is a conditional loop backedge branch.
The LLVM IR model¶
The model we use in LLVM IR is very similar to the above.
The PcIP (per-channel instruction pointer) is replaced by:
- a global (in the function) EM (execution mask), with each channel having a bit that is 1 when the channel is enabled;
- each join point has a RM (resume mask), with each channel having a bit that is 1 if the channel is disabled and due to be re-enabled when execution reaches that join point.
A goto is represented by the llvm.genx.simdcf.goto
intrinsic. Its
inputs are the current EM value, the current RM value for its UIP, and the
vector condition. Its results are the updated EM value, the updated RM
value for its UIP, and a scalar bool that says whether all channels are now
disabled and execution should branch to the JIP. This last result is then
(usually) used in a standard LLVM conditional br
instruction.
A goto is implicitly attached to its UIP join by the input and output RM values being part of a web of RM values connected by goto and phi nodes and used in that join.
A join is represented by the llvm.genx.simdcf.join
intrinsic. Its
inputs are the current EM value and the current RM value for this join.
Its results are the updated EM value (this join’s RM value is now effectively
all zeros so it not returned as a result), and a scalar bool that says whether
all channels are still disabled and execution should branch to the JIP.
This last result is then (optionally) used in a standard LLVM conditional
br
instruction.
An instruction’s register write-back being gated by which channels are enabled is modeled by the current EM value (or the appropriate size left slice of it) being used as the predicate in a select or wrregion or shared function intrinsic.
Note that EM is always 32 bit, but a join’s RM may be smaller as it has the same vector width as the condition on all gotos that update it.
This model is equivalent to the BSpec model, as long as:
- there is only ever one EM value live at a time with an initial value in a function of either all ones or the passed in call mask;
- for each join point, there is only ever one RM value live at a time with an initial value in a function of all zeros, and a value after the join point of all zeros;
- it is possible to re-order the code such that the “false” target of a conditional branch that a goto or join is attached to is fall-through, and all JIPs and UIPs are forward.
Like any other variable with multiple values transformed to SSA, different EM values may be joined with a phi node. Similarly, for a particular join point’s RM, different RM values may be joined with a phi node.
The llvm.genx.simdcf.goto
and llvm.genx.simdcf.join
intrinsics can
only be generated to goto
and join
instructions if the GenX backend
deems them to be used in a way that is equivalent to the BSpec model. Otherwise,
they are lowered to equivalent but slower code that implements the semantics
of the spec of the intrinsics below.
There are more detailed requirements on the use of these intrinsics to be able
to generate them to goto
and join
instructions documented in the
GenXSimdCFConformance pass.
llvm.genx.simdcf.goto
: goto instruction¶
- arg0: OldEM (old execution mask): v32i1
- arg1: OldRM (old resume mask): vector of i1
- arg2: SimdCond (the SIMD control flow condition): same type as arg1
Return value: struct with the following elements:
- ret0: NewEM (updated execution mask): v32i1
- ret1: NewRM (updated resume mask): same type as arg1
- ret2: BranchCond: i1
The elements of the returned struct are calculated as follows:
- NewEM = OldEM & (SimdCond one extended to v16i1)
- NewRM = OldRM | (OldEM & ~(SimdCond & (OldEM truncated to size of SimdCond)))
- BranchCond = !any(NewEM truncated to size of SimdCond)
llvm.genx.simdcf.goto
represents a Gen goto instruction, taking a
vector condition, modifying the global EM and the UIP’s RM, and
resulting in a scalar condition to be used in a conditional branch whose
“true” successor is the goto’s JIP.
If the BranchCond result is not used, then the goto’s JIP is set to the join immediately after.
If the BranchCond result is used in a conditional branch, and JIP is later than the earliest join point where a channel would be re-enabled, then it is undefined whether the resulting goto instruction’s JIP is as specified here, or an earlier join point. (This rule is to allow for the vISA finalizer re-deriving the JIPs.)
If the goto intrinsic’s conditional branch simply branches over an empty block
with an unconditional branch, then the GenX backend takes the intrinsic and
the two branches to be a do..while back edge, giving a Gen goto
instruction with BranchCtrl=1, UIP set to the successor of the unconditional
branch (the top of the do..while loop), and JIP set to the following join
instruction.
Channels already disabled in EM remain disabled. For enabled channels, any channel whose element in SimdCond is true becomes disabled in EM, and the corresponding bit in RM is set such that the channel becomes re-enabled upon reaching the RM’s join point. If all channels in EM are then disabled, then BranchCond is true and the conditional branch in which it is used branches to the next join point in sequence.
Note that SimdCond has the same sense as in the Gen goto instruction, but the opposite sense to that in a vISA forward goto instruction.
llvm.genx.simdcf.join
: join instruction¶
- arg0: OldEM (old execution mask): v32i1
- arg1: RM (resume mask): vector of i1
Return value: struct with the following elements:
- ret0: NewEM (updated execution mask): v32i1
- ret1: BranchCond: i1
The elements of the returned struct are calculated as follows:
- NewEM = OldEM | (RM zero extended to v32i1)
- BranchCond = !any(NewEM truncated to size of RM)
This is marked as having side effects to stop LLVM removing an otherwise unused join at an outer endif.
llvm.genx.simdcf.join
represents a Gen join instruction, using the join
point’s RM, modifying the global EM, and resulting in a scalar condition to
be used (optionally) in a conditional branch whose “true” successor is
the join’s JIP.
If the BranchCond result is not used, then the join’s JIP is undefined; this case is used when it is known that at least one channel is enabled after the join so JIP will never be used.
If the BranchCond result is used in a conditional branch, and JIP is later than the earliest join point where a channel would be re-enabled, then it is undefined whether the resulting goto instruction’s JIP is as specified here, or an earlier join point. (This rule is to allow for the vISA finalizer re-deriving the JIPs.)
Note that vISA does not have a join instruction; the vISA finalizer recovers the join points from the goto instructions assuming a linear order.
Channels with a set bit in RM become enabled in EM. If all channels in EM are still disabled, then BranchCond is true and the conditional branch in which it is used branches to the next join point in sequence.
ALU intrinsics¶
add¶
Non-saturating add intrinsic is not needed. A vISA non-saturating add where the result type is different to the operand type is represented by trunc/zext/sext of each operand and then an LLVM IR Add instruction.
llvm.genx.*add.sat
: add instruction with saturation¶
llvm.genx.ssadd.sat
: result signed, operands signedllvm.genx.suadd.sat
: result signed, operands unsignedllvm.genx.usadd.sat
: result unsigned, operands signedllvm.genx.uuadd.sat
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type, even i64
- arg1: second input, same type as arg0
- Return value: result, any scalar or vector integer type with same
- vector width
For an fp add, use the LLVM IR FAdd instruction, followed by llvm.genx.sat if saturation is required.
asr¶
asr intrinsic is not needed. Because asr cannot overflow, an asr that saturates with a smaller result type than the execution type can be represented by an LLVM IR Asr instruction then an llvm.genx.sstrunc.sat.
llvm.genx.*avg
: integer averaging, no saturation¶
llvm.genx.ssavg
: result signed, operands signedllvm.genx.suavg
: result signed, operands unsignedllvm.genx.usavg
: result unsigned, operands signedllvm.genx.uuavg
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
- Return value: result, any scalar/vector integer type (not i64)
- with same vector width
llvm.genx.*avg.sat
: integer averaging with saturation¶
llvm.genx.ssavg.sat
: result signed, operands signedllvm.genx.suavg.sat
: result signed, operands unsignedllvm.genx.usavg.sat
: result unsigned, operands signedllvm.genx.uuavg.sat
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
- Return value: result, any scalar/vector integer type (not i64)
- with same vector width
llvm.genx.*bfe
: bitfield extract¶
llvm.genx.sbfe
: bitfield extract, signed resultllvm.genx.ubfe
: bitfield extract, unsigned result- arg0: first input, any scalar/vector i32 type
- arg1: second input, same type as arg0
- arg2: third input, same type as arg0
- Return value: result, same type as arg0
llvm.genx.bfi
: bitfield insert¶
- arg0: first input, any scalar/vector i32 type
- arg1: second input, same type as arg0
- arg2: third input, same type as arg0
- arg3: fourth input, same type as arg0
- Return value: result, same type as arg0
llvm.genx.bfrev
: reverse bits¶
- arg0: first input, any scalar/vector i32 type
- Return value: result, same type as arg0
llvm.genx.cbit
: count set bits¶
- arg0: first input, any scalar/vector integer type
- Return value: result, int32 of same width as arg0
llvm.genx.cos
: cos instruction¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.ieee.div
: Divide, IEEE variant¶
- arg0: first input, any scalar/vector float/double type
- arg1: second input, same type
- Return value: result, same type
llvm.genx.dp2
: dp2 instruction (dot product on groups of 4 elements)¶
- arg0: first input value, any vector float with a multiple of 4 elements
- arg1: second input value, same type as arg0
- Return value: result, same type
llvm.genx.dp3
: dp3 instruction (dot product on groups of 3 elements)¶
- arg0: first input value, any vector float with a multiple of 4 elements
- arg1: second input value, same type as arg0
- Return value: result, same type
llvm.genx.dp4
: dp4 instruction (dot product on groups of 4 elements)¶
- arg0: first input value, any vector float with a multiple of 4 elements
- arg1: second input value, same type as arg0
- Return value: result, same type
llvm.genx.dph
: dph instruction (dot product homogenous)¶
- arg0: first input value, any vector float with a multiple of 4 elements
- arg1: second input value, same type as arg0
- Return value: result, same type
llvm.genx.exp
: base 2 exponent¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.*fbh
: find bit high¶
llvm.genx.sfbh
: find bit high, signed operandllvm.genx.ufbh
: find bit high, unsigned operand- arg0: input value, any scalar/vector i32 type
- Return value: result, same type
llvm.genx.fbl
: find bit low¶
- arg0: input value, any scalar/vector i32 type
- Return value: result, same type
llvm.genx.frc
: fractional part¶
- arg0: input value, any scalar/vector float type
- Return value: result, same type
llvm.genx.inv
: reciprocal¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.line
: linear equation¶
- arg0: first input value, vector float with exactly 4 elements
- arg1: second input value, vector float with a multiple of 4 elements
- Return value: result, same type as arg1
llvm.genx.log
: base 2 logarithm¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.lrp
: linear interpolation¶
- arg0: first input value, any vector float with a multiple of 4 elements
- arg1: second input value, same type as arg0
- arg2: third input value, same type as arg0
- Return value: result, same type
llvm.genx.lzd
: leading zero detection¶
- arg0: input value, any scalar/vector i32 type
- Return value: result, same type
llvm.genx.*mad
: mad instruction, no saturation¶
llvm.genx.ssmad
: result signed, operands signedllvm.genx.sumad
: result signed, operands unsignedllvm.genx.usmad
: result unsigned, operands signedllvm.genx.uumad
: result unsigned, operands unsigned
result := arg0 * arg1 + arg2
- Return value: result, any scalar or vector integer type with same
- vector width
- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
- arg2: third input, same type as result
llvm.genx.*mad.sat
: mad instruction with saturation¶
llvm.genx.ssmad.sat
: result signed, operands signedllvm.genx.sumad.sat
: result signed, operands unsignedllvm.genx.usmad.sat
: result unsigned, operands signedllvm.genx.uumad.sat
: result unsigned, operands unsigned
result := sat(arg0 * arg1 + arg2)
- Return value: result, any scalar or vector integer type with same
- vector width
- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
- arg2: third input, same type as result
llvm.genx.*max
: max instruction¶
llvm.genx.smax
: result and operands signedllvm.genx.umax
: result and operands unsignedllvm.genx.fmax
: result and operands float- arg0: first input, any scalar/vector integer/float type, even i64
- arg1: second input, same type as arg0
- Return value: result, any scalar, vector integer/float type with same
- vector width
There is no need for a saturating variant of this intrinsic. Because max cannot overflow, a saturating max can be represented by this non-saturating max followed by the applicable one of the saturating trunc intrinsics.
llvm.genx.*min
: min instruction¶
llvm.genx.smin
: result and operands signedllvm.genx.umin
: result and operands unsignedllvm.genx.fmin
: result and operands float- arg0: first input, any scalar/vector integer/float type, even i64
- arg1: second input, same type as arg0
- Return value: result, any scalar or vector integer/float type with same
- vector width
There is no need for a saturating variant of this intrinsic. Because min cannot overflow, a saturating min can be represented by this non-saturating min followed by the applicable one of the saturating trunc intrinsics.
mul¶
Still need non-saaturating mul intrinsic as def-hoist/copy-prop in jitter cannot fully remove the trunc/zext/sext on each operand.
llvm.genx.*mul
: mul instruction, no saturation¶
llvm.genx.ssmul
: result signed, operands signed, signedllvm.genx.sumul
: result signed, operands signed, unsignedllvm.genx.usmul
: result signed, operands unsigned, signedllvm.genx.uumul
: result signed, operands unsigned, unsigned
result := arg0 * arg1
- Return value: result, any scalar or vector integer type with same
- vector width
- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
llvm.genx.*mul.sat
: mul instruction with saturation¶
llvm.genx.ssmul.sat
: result signed, operands signedllvm.genx.sumul.sat
: result signed, operands unsignedllvm.genx.usmul.sat
: result unsigned, operands signedllvm.genx.uumul.sat
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type (not i64)
- arg1: second input, same type as arg0
- Return value: result, any scalar/vector integer type with same
- vector width, even i64
For an fp mul, use the LLVM IR FMul instruction, followed by llvm.genx.sat if saturation is required.
llvm.genx.*mulh
: mulh instruction, no saturation¶
llvm.genx.smulh
: signedllvm.genx.umulh
: unsigned- arg0: first input, any scalar/vector i32 type
- arg1: second input, same type as arg0
- Return value: result, same type as arg0
llvm.genx.pln
: plane equation¶
- arg0: first input value, vector float with exactly 4 elements
- arg1: second input value, vector float with a multiple of 16 elements
- Return value: result, vector float with half as many elements as arg1
llvm.genx.pow
: power¶
- arg0: first input, any scalar/vector half/float type
- arg1: second input, same type
- Return value: result, same type
llvm.genx.rndd
: round down¶
- arg0: input value, any scalar/vector float type
- Return value: result, same type
llvm.genx.rnde
: round to even¶
- arg0: input value, any scalar/vector float type
- Return value: result, same type
llvm.genx.rndu
: round up¶
- arg0: input value, any scalar/vector float type
- Return value: result, same type
llvm.genx.rndz
: round to zero¶
- arg0: input value, any scalar/vector float type
- Return value: result, same type
llvm.genx.rsqrt
: reciprocal square root¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.*sad2
: two-wide sum of absolute differences¶
llvm.genx.ssad2
: signed argument and resultllvm.genx.usad2
: unsigned argument and result- arg0: first input, vector of i8, multiple of 2 wide
- arg1: second input, same type
- Return value: result, vector of i16 of same vector width
llvm.genx.*sad2add
: two-wide sum of absolute differences and add¶
llvm.genx.sssad2add
: signed result and argsllvm.genx.uusad2add
: unsigned result and argsllvm.genx.ussad2add
: unsigned result and signed argsllvm.genx.susad2add
: signed result and unsigned args- arg0: first input, vector of i8, multiple of 2 wide
- arg1: second input, same type
- arg2: third input, vector of i16 of same vector width
- Return value: result, same type as arg2
llvm.genx.*sad2add.sat
: two-wide sum of absolute differences and add, saturated¶
llvm.genx.sssad2add.sat
: signed result and argsllvm.genx.uusad2add.sat
: unsigned result and argsllvm.genx.ussad2add.sat
: unsigned result and signed argsllvm.genx.susad2add.sat
: signed result and unsigned args- arg0: first input, vector of i8, multiple of 2 wide
- arg1: second input, same type
- arg2: third input, vector of i16 of same vector width
- Return value: result, same type as arg2
llvm.genx.*shl
: shl instruction, no saturation¶
llvm.genx.ssshl
: result signed, operands signedllvm.genx.sushl
: result signed, operands unsignedllvm.genx.usshl
: result unsigned, operands signedllvm.genx.uushl
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type, even i64
- arg1: second input, same type as arg0
- Return value: result, any scalar or vector integer type with same
- vector width, even i64
llvm.genx.*shl.sat
: shl instruction with saturation¶
llvm.genx.ssshl.sat
: result signed, operands signedllvm.genx.sushl.sat
: result signed, operands unsignedllvm.genx.usshl.sat
: result unsigned, operands signedllvm.genx.uushl.sat
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type, even i64
- arg1: second input, same type as arg0
- Return value: result, any scalar/vector integer type with same
- vector width, even i64
shr¶
Intrinsic is not needed. Because shr cannot overflow, an shr that saturates with a smaller result type than the execution type can be represented by an LLVM IR Shr instruction then an llvm.genx.sstrunc.sat.
llvm.genx.sin
: reciprocal square root¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.sqrt
: reciprocal square root¶
- arg0: input value, any scalar/vector half/float type
- Return value: result, same type
llvm.genx.ieee.sqrt
: reciprocal square root, IEEE variant¶
- arg0: input value, any scalar/vector float/double type
- Return value: result, same type
llvm.genx.dp4a
: dp4a instruction (Dot Product 4 Accumulate)¶
- arg0: first input value, vector integer type
- arg1: second input value, vector integer type
- arg2: third input value, vector integer type
- Return value: result, vector integer type
llvm.genx.*add3
: add3 instruction without saturation¶
llvm.genx.add3
:- arg0: first input, any scalar/vector integer type, i16/i32
- arg1: second input, same type as arg0
- arg2: third input, same type as arg0
llvm.genx.*add3.sat
: add3 instruction with saturation¶
llvm.genx.ssadd3.sat
: result signed, operands signedllvm.genx.suadd3.sat
: result signed, operands unsignedllvm.genx.usadd3.sat
: result unsigned, operands signedllvm.genx.uuadd3.sat
: result unsigned, operands unsigned- arg0: first input, any scalar/vector integer type, i16/i32
- arg1: second input, same type as arg0
- arg2: third input, same type as arg0
- Return value: result, any scalar or vector integer type with same
- vector width
llvm.genx.bfn
: bfn instruction¶
llvm.genx.bfn
:- arg0: first input, any scalar/vector integer type, i16/i32
- arg1: second input, same type as arg0
- arg2: third input, same type as arg0
- arg3: fourth input, byte, constant
vISA reserved register intrinsics¶
llvm.genx.thread.*
: read thread ID register¶
llvm.genx.thread.x
: read vISA v1 (%thread_x)llvm.genx.thread.y
: read vISA v2 (%thread_y)- Return value: i16 the value read
llvm.genx.group.id.*
: read group ID register¶
llvm.genx.group.id.x
: read vISA v7 (%group_id_x)
llvm.genx.group.id.y
: read vISA v8 (%group_id_y)
llvm.genx.group.id.z
: read vISA v23 (%group_id_z)
- Return value: i32 the value read
llvm.genx.timestamp
: read vISA v11 (%timestamp)¶
- Return value: vxi32 the value read
The vector width must be power of 2 and no larger than 4.
llvm.genx.r0
: read vISA v12 (%r0)¶
- Return value: vxi32 or i32 the value read
The vector width must be power of 2 and no larger than 8.
llvm.genx.set.sr0.2
: write vISA v13(0, 2) (%sr0.2)¶
arg0: data to write (1 dword)
- Return value: void
llvm.genx.get.color
: read color value of the thread origin¶
Return Value: i16 the value read
This may not be the most appropriate way to access this value, but is a stop-gap solution.
llvm.genx.get.hwid
: read hw_id value¶
Return Value: i32 the value read
llvm.genx.set.pause
: set the pause register (v11.4)¶
arg0: length of pause 10 bits (0-4 must be 0)
Return Value: none
Set the pause value - this pauses instruction issue until the value has been decremented to 0 (decrements every 32 clocks)
We set this intrinsic to have side-effects (last field empty) to stop it being removed as it otherwise looks dead
llvm.genx.dummy.mov
: insert a dummy mov to v0¶
arg0: a value that we want to mov to v0 (usually to trigger a scoreboard dependency)
Return Value: none
This is primarily used to set up scoreboard dependencies. If a value is mov’ed to v0 then it will trigger a scoreboard dependency check. As a word (16 bits) is usually the basic type of value that is worked with, you only need to dummy mov one of these from any payload to correctly trigger the dependency
We set this intrinsic to have side-effects (last field empty) to stop it being removed as it otherwise looks dead and also to prevent any kind of code motion optimisation


bool is true
bool is not true
name is empty
name is not empty
surname is not empty
surname is empty
There is not activities
There are activities


Liverpool urged to keep Premier League focus as fixture pile-up looms
In Summary
- The Reds hold an eight-point edge over second-placed Leicester and are heavy favourites to end a painful 30-year wait for a league title
London. Liverpool start a daunting run of 13 games in 41 days at Crystal Palace on Saturday that will define their season and, quite possibly, how the Jurgen Klopp era will be remembered at Anfield.
The spectacular, and controversial, 3-1 victory over defending champions Manchester City before the international break has left Liverpool nine points clear of Pep Guardiola's side.
They hold an eight-point edge over second-placed Leicester and are heavy favourites to end a painful 30-year wait for a league title.
The visit to Selhurst Park also starts a sequence of five league games against opponents who appear, on paper at least, not to offer too stern a test for a team that have dropped just two league points all season -- in a 1-1 draw at Manchester United.
But it is Liverpool's schedule away from the league that has caused the greatest degree of interest and speculation in recent weeks.
Their involvement in the FIFA Club World Cup in Qatar, plus their success in the League Cup, means Klopp has been forced to play two games within 24 hours of each other, over 4,000 miles (6,400 kilometres) apart.
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Liverpool visit Aston Villa on December 17 in the cup quarter-final before they play in the Middle East on the 18th, with Klopp fielding two different squads to cope with the congestion.
The Liverpool boss concedes that the exact nature and logistics of putting out two teams on different continents within a matter of hours are yet to be addressed.
But a number of pundits, led by former Anfieldfavourite Jamie Carragher, have argued that Klopp should effectively ignore the four cup competitions in which his team are involved this season -- the two domestic cups, Champions League and Club World Cup.
- Premier League fever -
The obsession among the red half of Merseyside with winning the title increased with the near-miss under Brendan Rodgers in 2014.
And it reached near-fever pitch in May, when they lost the title to City by one point.
Not even the considerable consolation of winning the Champions League in June could dull the desire from Liverpool supporters to see their team lift a trophy they last won under Kenny Dalglish in 1990.
"I know a lot of Liverpool supporters wouldn't say this, and certainly the club couldn't, but nothing can get in the way of Liverpool winning the league. Nothing," said Carragher.
"The Aston Villa game in the Carabao (League) Cup? If Liverpool get through they will have two semi-finals to play then and that cannot get in the way of Liverpool winning the league."
The difficulties facing Liverpool are summed up by a run of at least two games per week for the remainder of 2019 including Champions League group matches against Napoli and Salzburg before the double header at Villa and in Qatar.
But a run of league fixtures against Palace, Brighton, struggling Everton at home, Bournemouth and Watford suggests Klopp's side could maintain their dominant grip on the title race prior to visiting former manager Rodgers and current second-placed side Leicester on December 26.
Mohamed Salah and Andy Robertson are considered doubts for the trip to Palace, with injuries they collected earlier this month.
But Joe Gomez and Jordan Henderson, who both pulled out of England's game in Kosovo last weekend, are expected to be fit to return.


Hamukwaya targets more spots at Tokyo 2020 20 Nov 2019, 09:27 by Staff Reporter Home \ Sports \ Hamukwaya targets more spots at Tokyo 2020 - New Era Live


Pro-Brexit UK candidate harassed anti-Brexit opponent: court
by AFPLONDON: A pro-Brexit candidate was on Wednesday found guilty of harassing a prominent “remain” figure after a court in London heard she followed her to parliament and called her a traitor.
Westminster Magistrates Court was told Amy Dalla Mura, 56, targeted Anna Soubry between January and March, on one occasion forcing her to abandon a public speaking engagement.
Mura is standing for the far-right English Democrats against Soubry, a former Conservative MP who is seeking re-election as an independent in the Broxtowe constituency in central England.
Chief magistrate Emma Arbuthnot described the defendant’s behaviour as “oppressive and unacceptable”, assessing that she was “driven by anger at Ms Soubry’s political views on Brexit”.
She said she was satisfied with Mura’s verbal abuse, including one occasion when she called Soubry a traitor as she was giving a television interview inside parliament, was harassment.
The judge granted Mura bail pending the completion of psychiatric reports and ordered her to reappear for sentencing on December 16 – four days after the general election.
As a condition of her bail, the judge banned her from campaigning in person in Broxtowe and ordered her not to mention Soubry by name as she canvassed for votes.
Last week, a man who sent a death threat to Soubry was jailed for one year after warning Soubry she would suffer the same fate as Jo Cox, an opposition Labour party lawmaker who was murdered by a neo-Nazi days before the 2016 EU referendum.

A police unit set up after Cox’s murder said it was probing increasing levels of abuse, threats and intimidation against MPs, their staff or families.
Safety warnings for the campaign have been issued to candidates.
Adrian Usher, of the Metropolitan Police’s Parliamentary Liaison and Investigation Team, arrested and charged Mura, who pleaded not guilty.
He said: “Strong political opinions are no excuse for abuse, harassment or intimidation of members of the public or parliamentarians.
“Police will treat such allegations seriously and seek to bring offenders to justice – as today’s conviction demonstrates.”


--- layout: post title: "A simpler Arbitrary for the Diamond kata" description: "There's a simple way to make FsCheck generate letters in a particular range." date: 2015-02-23 19:50 UTC tags: [Unit Testing, F#, FsCheck] --- {% include JB/setup %}
{{ page.description }}
In my post about the Diamond kata with FsCheck, I changed the way FsCheck generates char values, using this custom Arbitrary (essentially a random value generator):
type Letters = static member Char() = Arb.Default.Char() |> Arb.filter (fun c -> 'A' <= c && c <= 'Z')
This uses the default, built-in Arbitrary for char values, but filters its values so that most of them are thrown away, and only the letters 'A'-'Z' are left. This works, but isn't particularly efficient. Why generate a lot of values only to throw them away?
It's also possible to instruct FsCheck to generate values from a particular set of valid values, which seems like an appropriate action to take here:
type Letters = static member Char() = Gen.elements ['A' .. 'Z'] |> Arb.fromGen
Instead of using Arb.Default.Char()
and filtering the values generated by it, this implementation uses Gen.elements
to create a Generator of the values 'A'-'Z', and then an Arbitrary from that Generator.
Much simpler, but now it's also clear that this custom Arbitrary will be used to generate 100 test cases (for each property) from a set of 26 values; that doesn't seem right...


The GenFileSelector provides the user interface and functionality to allow a user to traverse directories and volumes (disks) and view the files contained therein. It can be customized to limit the displayed file names or to expand the listings to include special files.
This object is used by the GenDocumentControl object to provide most file dialog boxes. If your application uses the Document Control objects, you will probably not need to add a GenFileSelector.
1 File Selector Overview
2 File Selector Basics
2.1 Setting Up the File Selector
2.2 Supporting the File Selector
2.3 Messages to Handle
2.4 Some Common Customizations
3 File Selector Instance Data
3.1 The GFSI_attrs Field
3.2 The GFSI_fileCriteria Field
3.3 Matching a File's Token
3.4 Matching a File's Creator App
3.5 Matching a File's Geode Attributes
3.6 Masking File Names
3.7 Matching a File's File Attributes
3.8 Searching Via Callback Routine
3.9 Resetting a Filter
4 File Selector Use
4.1 When a User Selects a File
4.2 The Current Selection
4.3 Rescanning Directories
4.4 Setting Scalable UI Data


For Windows 32-bit \----folder +---configuration.xml +---setup.cmd +---setup.exe +---office +---data +---v32.cab +---v32_build.cab +---build +---i320.cab +---i32LCID.cab +---s320.cab +---s321LCID.cab +---stream.x86.lang.dat +---stream.x86.x-none.dat
For Windows 64-bit \----folder +---configuration.xml +---setup.cmd +---setup.exe +---office +---data +---v64.cab +---v64_build.cab +---build +---i640.cab +---i64LCID.cab +---s640.cab +---s64LCID.cab +---stream.x64.lang.dat +---stream.x64.x-none.dat
:: Made by BaoTrongIT @echo off title Install Office Click To Run color 0f pushd "%~dp0" echo Step 1. Extract office deployment tool if not exist "%~dp0setup.exe" ( md temp for /f %%A in ('dir /b officedeploymenttool*.exe') do ( echo.&echo Extracting %%A...&echo. %%A /extract:temp /quiet ) move "%~dp0\temp\setup.exe" "%~dp0" >nul 2>&1 rd "%~dp0\temp" /s /q ) else ( echo.&echo Office deployment tool has extracted ) echo ======================================================= echo Step 2. Download file from "configuration.xml" if not exist "%~dp0configuration.xml" goto:exit echo.&echo Downloading file, keep your connection... setup.exe /download configuration.xml echo.&echo Download completed echo ======================================================= echo Step 3. Install office from "configuration.xml" echo.&echo Installing office, do not turn off your computer... setup.exe /configure configuration.xml echo.&echo Install completed if not exist "%~dp0Setup_Offline.cmd" ( echo @echo off > Setup_Offline.cmd echo setup.exe /configure configuration.xml >> Setup_Offline.cmd echo exit >> Setup_Offline.cmd ) echo.&echo Press any key to exit ! pause >nul del %0 /q /f exit :exit echo.&echo configuration.xml not exist, please generator it and save to this folder echo.&echo Press any key to exit ! pause >nul3. Put configuration.xml same folder with Office deploymet tool
Monthly Channel might be the right choice for your organization in the following situations:
You want to provide your users with the newest features of Office as soon as those features are available
You don't have many line-of-business applications, add-ins, or macros that you need to test to determine if they work with an updated version of Office.
A Monthly Channel with new features is expected to be released each month, although there is no set schedule for when a feature release occurs. In addition to new or updated features, the release might also contain non-security updates, such as updates that provide stability or performance improvements for Office. Security updates for Monthly Channel are usually released on the second Tuesday of the month. At any other time, if there is a critical non-security issue that needs to be fixed, we will provide a separate Monthly Channel release that fixes the issue.
Monthly Channel releases are cumulative. The most current Monthly Channel release contains all the features, security updates, and non-security updates from the previous Monthly Channel releases.
A Monthly Channel release is supported only until the next Monthly Channel release is available. No new security updates are provided for previous Monthly Channel releases.
This update channel provides an early look at the upcoming Monthly Channel release. It is a supported update channel, and usually is available at least one week ahead of time when it's a Monthly Channel release that contains new features.
If your organization doesn't want to deploy the latest features of Office right away or you have a significant number of line-of-business applications, add-ins, or macros that you need to test with Office, then Semi-Annual Channel might be the better choice for your organization. That's because new features are added to Semi-Annual Channel only twice a year, instead of every month. Semi-Annual Channel is the default update channel for Office 365 ProPlus.
A Semi-Annual Channel with new features is expected to be released twice a year, in January and July. New features aren't added to Semi-Annual Channel at any other time. The features that are included in Semi-Annual Channel are features that have been released previously in Monthly Channel.
In the four months prior to a new Semi-Annual Channel feature release, Microsoft provides builds of the upcoming release so that pilot users and application compatibility testers in your organization can work with the upcoming release. These builds are provided through the Semi-Annual Channel (Targeted) update channel.
After the January and July releases of Semi-Annual Channel, additional security updates, if needed, can also be added to Semi-Annual Channel. A release of Semi-Annual Channel with these updates usually occurs on the second Tuesday of the month. If there is a critical non-security issue that needs to be fixed in Semi-Annual Channel, that non-security update will also be included in a Semi-Annual Channel release.
To help your organization prepare for a Semi-Annual Channel release, Microsoft provides Semi-Annual Channel (Targeted). The primary purpose of this update channel is to give pilot users and application compatibility testers in your organization a chance to work with the upcoming Semi-Annual Channel release. During this time, which is about four months, you might identify possible issues that you need to fix with your line-of-business applications, add-ins, or macros or that you want Microsoft to fix.
A Semi-Annual Channel (Targeted) with new features is expected to be released twice a year, in March and September. New features aren't added to Semi-Annual Channel (Targeted) at any other time. The features that are included in Semi-Annual Channel (Targeted) are features that have been released previously in Monthly Channel.
The March and September feature releases for Semi-Annual Channel (Targeted) also include security and non-security updates that have been released previously in Monthly Channel. After the March and September releases, additional security and non-security updates, if needed, can also be added to Semi-Annual Channel (Targeted). A release of Semi-Annual Channel (Targeted) with these updates usually occurs on the second Tuesday of the month.
Even though this update channel is primarily designed for your testing, it's a fully supported version of Office 365 ProPlus.


SUNDAY
MONDAY
TUESDAY
WEDNESSDAY
THURSDAY
FRIDAY
SATURDAY
week 1
{{time}}
{{lect}}
{{lnm}}
week 2
week 3
week 4


Kitchen v Restaurant
While it's easy to see the technical gains that a student can make at DBC, the cultural knowledge is just as important.
Students were asked to watch one of Shereef's "Fireside Chats", and answer a few questions regarding our expectations of the program, and ourselves...
What's your take on the DBC experience?
Buckle in and hold on! I expect DBC to be one of the most unique experiences of my life. My comfort zone will be smashed by technical and cultural hammers. The only question is, what will I be when the pieces are put back together?...
What is your impression of DBC?
My impression of DBC is...wrong. It will change - multiple times. To me, DBC is one of those journeys that's so unique our minds can't predict it accurately. For now, I believe DBC to be a alternative form of learning. People from all across the country congregate in one place, and proceed to eat, breathe, and $hit code. DBC stretches your mind, slaps it in the face, and beats it against a keyboard until you can't take it. "Hells yeah."
How do you see yourself engaging with this type of culture?
As with any new environment, adapting to DBC will be a huge adjustment. Luckily, my professional career has taught me much about thinking outloud, communicating my thoughts, and considering others' point of view. With that said, most of my academic career has followed the tyipcal model: sit, listen, test. I'm open-minded though, and I applied to DBC for a reason.
Have your expectations of DBC changed, and how?
Admittedly, my initial interest in DBC came from more of a "restaurant/consumer" mentality. My current job was going nowhere, and I wanted a fix. After applying the first time I was rejected (luckily), and my approach is much more inline with the "kitchen" mentality. This program will be what WE MAKE IT. Not only must I make commitments each day when walk into DBC, but all of my peers must as well. This isn't every man for himself. Sit. Listen. Test? Psh.... How about: GET UP! TALK THROUGH IT! CREATE!
Are you excited to participate in this kind of learning environment?
Excited? No. F***ing ecstatic? YES. I've been looking forward to this program for over a year, and my excitement has only strengthened. The challenges, students, and instructors are already making this a wild ride.
Does it make you nervous?
Hmmmm...Spending my life savings, quitting my job, and moving across the country to live/work with complete strangers. If you're not at least a little nervous, you must have ice water running through your veins. I'm certainly nervous, but in a good way. Much of DBC is unpredictable, and that's what I signed up for. Keep the adrenaline coming!


{% extends "layout_task-list.html" %} {% block page_title %} Money Claims Prototype {% endblock %} {% block home_link %} ../task-list {% endblock %} {% block proposition_header %} {% set my_account="1" %} {% include "includes/propositional_navigation.html" %} {% endblock %} {% block content %} {% include "includes/phase_banner_beta.html" %} Back {{formData | safe}} You didn't get the claim Completing your claim You don't owe the money You can apply to cancel the judgment if you didn't get or respond to the claim. This is called getting the judgment 'set aside'. You may have to pay a court fee of £255. You'll need to explain in your application and at a private hearing why you weren't able to respond. If approved the CCJ will be removed from the register and you'll have 14 days to respond to the claim. You owe the money You’ll need to pay Jan Clark £1,500. Don’t pay the court. You can ask to change the way you pay. Make sure you'll be able to prove you’ve paid. Send a cheque or postal order by post or make a bank transfer. Don’t send cash through the post. {% endblock %}
Completing your claim
You can apply to cancel the judgment if you didn't get or respond to the claim. This is called getting the judgment 'set aside'. You may have to pay a court fee of £255.
If approved the CCJ will be removed from the register and you'll have 14 days to respond to the claim.
You’ll need to pay Jan Clark £1,500. Don’t pay the court.
You can ask to change the way you pay.
Make sure you'll be able to prove you’ve paid. Send a cheque or postal order by post or make a bank transfer. Don’t send cash through the post.


throw
statements
which throw inappropriate exceptions. One use of this inspection would be to warn of
throw
statements which throw overly generic exceptions
(e.g. java.lang.Exception
or java.io.IOException
).
Example:
void setup(Mode mode) { if (mode == null) throw new RuntimeException("Problem during setup"); // warning: Prohibited exception 'RuntimeException' thrown ... }
Use the list below to specify which exceptions should be flagged by this inspection.


Circumflex is in active development stage. For now, it is primarily maintained by whiteants.net (Russia).
If you wish to join the team, please contact one of the team members below.
The Circumflex team thanks all people interested in our projects. We hope you'll have a lot of fun developing with Circumflex!
We also owe special thanks to some people for their contribution to the development of Circumflex:
We highly appreciate your help, guys!


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ORDER NOW! Try Papa John’s mobile web ordering!
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|
New_CETA_AR
|
UI infomation panel control whenever player walks into a special place More...
Inherits MonoBehaviour.
Public Types | |
| enum | actionType { actionType.video, actionType.panel, actionType.scene, actionType.none } |
| What the action does. More... | |
Public Member Functions | |
| void | ButtonActiveEvent () |
| Use menu to trigger info panel instead of walking into it More... | |
Public Attributes | |
| CETAUIManager | managerCall |
| Used to call to the CETA UI Manager. More... | |
| string | TriggerTitle |
| What the button that triggers the info UI should display. More... | |
| string | displayTitle |
| The title of the UI. More... | |
| string | ImageLocation |
| What image should be shown. (The URL link to the image.) More... | |
| Sprite | sprite |
| store image texture in scope More... | |
| string | webButtonTitle |
| Website button text. More... | |
| string | webLink |
| Website Link. More... | |
| string | actionTitle |
| Action button title. More... | |
| actionType | setType |
| GameObject | panel |
| The panel to show. More... | |
| string | videoURL |
| The video URL to play;. More... | |
| string | triggerScene |
| The scene the trigger should load. More... | |
Private Member Functions | |
| void | Start () |
| initial database connection More... | |
| void | Update () |
| Update is called every frame More... | |
| void | OnTriggerStay (Collider hit) |
| Whenever Player walks into a info Trigger, show button for opening info panel More... | |
| void | OnTriggerExit (Collider hit) |
| Whenever Player exits the Trigger, hide button for opening info panel More... | |
| void | prepareAction () |
| Setup info panel base one what action Type the Trigger is More... | |
| async void | getInfo (bool isEvent) |
| Thread get image from database More... | |
| IEnumerator | SetInfo (Uri URL, bool isEvent) |
| Thread set all the infomations to info panel More... | |
| void | ManagerCalls (string text, bool isEvent) |
| Display the info panel for user by calling manager script More... | |
Private Attributes | |
| FirebaseStorage | storage |
| StorageReference | storage_ref |
| GameObject | loadingGif |
| loading.gif More... | |
| Vector3 | panelHide |
| Where the panel should hide. More... | |
| bool | inTrigger = false |
| Denotes if the player is in a trigger. More... | |
| PlayerController | controller |
UI infomation panel control whenever player walks into a special place
|
strong |
| void InfoTrigger.ButtonActiveEvent | ( | ) |
Use menu to trigger info panel instead of walking into it
|
private |
Thread get image from database
|
private |
Display the info panel for user by calling manager script
|
private |
Whenever Player exits the Trigger, hide button for opening info panel
|
private |
Whenever Player walks into a info Trigger, show button for opening info panel
|
private |
Setup info panel base one what action Type the Trigger is
|
private |
Thread set all the infomations to info panel
|
private |
initial database connection
|
private |
Update is called every frame
Show/Hide panel for video display
| string InfoTrigger.actionTitle |
Action button title.
|
private |
| string InfoTrigger.displayTitle |
The title of the UI.
| string InfoTrigger.ImageLocation |
What image should be shown. (The URL link to the image.)
|
private |
Denotes if the player is in a trigger.
|
private |
loading.gif
| CETAUIManager InfoTrigger.managerCall |
Used to call to the CETA UI Manager.
| GameObject InfoTrigger.panel |
The panel to show.
|
private |
Where the panel should hide.
| actionType InfoTrigger.setType |
| Sprite InfoTrigger.sprite |
store image texture in scope
|
private |
|
private |
| string InfoTrigger.triggerScene |
The scene the trigger should load.
| string InfoTrigger.TriggerTitle |
What the button that triggers the info UI should display.
| string InfoTrigger.videoURL |
The video URL to play;.
| string InfoTrigger.webButtonTitle |
Website button text.
| string InfoTrigger.webLink |
Website Link.


What's your take on the DBC / EDA experience?
I think it is very well put together. I like the focus on things other than coding and the staff I have met seem very genuine and committed.
What are your impressions?
The two thoughts that come to mind, is caring and intense.
How do you see yourself engaging with this type of culture?
I can seem myself really enjoying it but also at the same time I like my own time so being around a lot of outgoing people could be a challenge.
Have your expectations of EDA changed? If so, how?
To be honest my expectations haven't changed that much. I am pretty cautious and really research a lot, before I have to commit to something requiring the investment of EDA. That being said it's the first week! I'm prepared to be surprised.
Are you excited to participate in this kind of learning environment? Does it make you nervous?
I'm very excited! I see it as a chance push myself and learn a whole new skill that will serve me well.


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©The ALC Team 2019


M. A. Buen-Abad, J. Buch, J. Fan, and J. S. C. Leung, Galactic Origin of Relativistic Bosons and XENON1T Excess, (2020), arXiv: 2006.12488.
J. Buch, J. Fan, and J. S. C. Leung, Implications of the Gaia Sausage for Dark Matter Nuclear Interactions, Phys. Rev. D 101, no. 6, 063026 (2020), arXiv: 1910.06356.
J. Buch, J. S. C. Leung, and J. Fan, Using Gaia DR2 to Constrain Local Dark Matter Density and Thin Dark Disk, JCAP 1904, 026 (2019), arXiv: 1808.05603.
J. Fan, P. Jaiswal, and J. S. C. Leung, Jet Observables and Stops at 100 TeV Collider, Phys. Rev. D 96, no. 3, 036017 (2017), arXiv: 1704.03014.
Ph.D. thesis, Dark Matter Searches in the Crescendo of the 21st Century Experiments, advisor: Jiji Fan.
M.Phil. thesis, Topics in Cosmic Ray Measurement and Particle Detectors Development, advisor: Ming Chung Chu.
Senior thesis, Rabi Oscillation and State Construction in Quantum Bouncing Ball System, advisor: Chi Kwong Law.
(Junior) CERN thesis, Cathode Strip Chambers Production for CMS Endcaps, advisor: Armando Lanaro.


title = "Altarservers_lengfeld" url = "/altarservers_lengfeld" layout = "base_administration" is_hidden = 0 ==


--- layout: post title: Storyboards line date: '2017-08-15T11:30:11+02:00' categories: - Storyboards - Sketches picture_url: https://film-Storyboards.tumblr.com/post/164218827168/Storyboards-line ---


Commentary: What’s next for e-scooters after the footpath ban?
by Julienne ChenThe new law may keep pedestrians safe from e-scooters, but does not negate the need for investment in critical transport infrastructure going forward, says Julienne Chen.
SINGAPORE: The ban on e-scooters from footpaths was announced suddenly. But let us be honest, it was a long time coming.
The warning signs were there: Fights and accidents playing out in full view for all to see and judge, and efforts at mediation were insufficient to calm the tension hanging in the air, too thick to be tenable over the long term.
The co-habitation arrangement between pedestrians and e-scooters wasn’t going to stand the test of time.
AN OVERDUE BREAK–UP
Now that the break-up has happened, e-scooters have been ordered to pack their bags and move out.
As with most break-ups, there is also a lot of finger-pointing going on – towards everyone from the reckless riders down to the sellers of non-compliant e-scooters. Even the graciousness and kindness of Singaporeans, as a whole, is on trial.
READ: What happened to cautiousness and graciousness on the roads? A commentary
READ: E-scooter ban on footpaths – here’s a list of those who got off scot-free, a commentary
Interestingly, there is one factor that seems to be flying under the radar despite the central role it has played in the drama: The lack of sufficient infrastructure.
THE GOOD NEWS? NOT A COMPLETE BAN
In their announcement, the Singapore Government did not impose a full ban on e-scooters. They are still able to use dedicated cycling paths and the Park Connector Network.
The Government also stated that they would construct approximately an additional 310km of such pathways, primarily in intra-town networks (i.e., to connect to local destinations within neighbourhoods), by 2025 – creating a total of approximately 750km of pathways that e-scooters can avail themselves of.
This is approximately 13 per cent of the existing network of 5,500km of footpaths, and less than 8 per cent of the 9,405km of vehicular road lanes.
A GOOD COMPROMISE?
On the face, this sounds like a good compromise. Indeed, e-scooters never belonged on a footpath to begin with.
Transportation modes that travel at vastly different speeds have almost always been separated from each other for reasons of efficiency, speed and, most of all, safety.
It is why separated bicycle paths are still the gold standard for transportation-forward cities around the world.
A goal of 310km of additional pathways in six years will be a good contribution, and well ahead of many other cities.
But Singapore is not just any other city. It is a city that prides itself on being fast, efficient, effective and inventive. The home of the Jewel, Marina Bay Sands and a wide array of other impressive high budget engineering feats that have literally moved earth.
IMAGINE THE WORLD’S MOST IMPRESSIVE TRANSPORT INFRASTRUCTURE
What could happen if we were to apply that ingenuity to creating the world’s most impressive infrastructure – not only for bicycles, but for e-scooters, hover boards, unicycles, skateboards and other modes of transport that are too fast for a footpath and too slow for a roadway?
Indeed, infrastructure for these emerging forms of transportation is so new that there is not even consensus on what to call it.
I have seen terms including “clean paths,” “green paths,” “third paths,” and an array of other path-isms.
This is because it seems counter-intuitive to call something a bicycle path when bicycles may not even be its dominant user. But it is better than the tongue twister: “Bicycles, e-bikes, e-scooters, PMDs and other emerging forms of low-impact transport.”
For the sake of simplicity, I’ll call them “car-lite modes”.
REDESIGNING SINGAPORE’S CAR-LITE PATHS
We are in new territory, and this presents a critical moment to consider how to successfully integrate these car-lite modes into the city.
The demand is now proven, and it is waiting for the infrastructure to catch up to allow it to thrive. This is where I hope we can transfer our energy to next, and with speed.
This time would be well spent rethinking how to create great, intuitive infrastructure for car-lite modes. A well-considered design has the ability to help reconfigure the relationships we have with one another on the road.
To create a truly multi-modal transportation network, it will not be enough to simply widen existing footpaths in neighbourhoods.
We need to consider everything from how different car-lite modes interact with one another within the path, to how the paths interface with pedestrians, cars, buses, intersections, bus stops, footpaths and more.
Further, we need to look at how to create linkages not only within towns, but across the city to allow people to get to where they want to go safely, comfortably and easily.
READ: Can we co-exist with PMDs? Yes, but we need to take a different path, a commentary
READ: Walking the NParks 36km Coast-to-Coast trail: Worth the effort?
Even on the existing Park Connector Network, there are a number of potential design improvements that could enhance its appeal.
It is great to have a dedicated recreation pathway, but many sections of it still require significant effort to use including navigating overhead bridges, busy traffic intersections with long signal wait times, steps, narrow shared footpaths that snake around busy bus stops, unsigned detours around construction sites and unclear entrance and connection points.
Applying intuitive and user-friendly design to these types of infrastructure will elevate Singapore to the next level of transport, opening a whole new range of mobility options that can change the way that we see, move within and interact with the city.
DISRUPTIVE INNOVATION NEEDED
To create a diversified and future-proof transportation network, it is unlikely that incremental improvements will be sufficient. We need disruptive innovation.
Industry will continue to introduce new innovations with different modes of transport.
If the Government can look towards innovation on the side of the design and infrastructure, building upon all that we have experienced in the past two years, I am optimistic that we can reintroduce car-lite modes to the city, with the right conditions to set it up for success.
Julienne Chen is a research fellow at the Lee Kuan Yew Centre for Innovative Cities at the Singapore University of Technology and Design, where she focuses on urban processes and systems.


Software
skarnet.org
s6
What is it ?
s6 is a small suite of programs for UNIX, designed to allow process supervision
(a.k.a service supervision),
in the line of daemontools
and runit, as well as various
operations on processes and daemons. It is meant to be a toolbox for
low-level process and service administration, providing different sets of
independent tools that can be used within or without the framework, and
that can be assembled together to achieve powerful functionality with
a very small amount of code.
Examples of things you can do by assembling together several programs
provided by s6 - besides process supervision:
- syslogd functionality,
using much less resources than the traditional syslogd.
- Reliable service readiness notification, which is the basis for
service dependency management.
- Controlled privileged gain as with
sudo, without using
any suid programs.
- The useful parts of
socket
activation[1]
without having to change application code or link servers
against any specific library, and without having to switch to any
specific init system.
The s6 documentation tries to be complete and self-contained; however,
if you have never heard of process supervision before, you might be
confused at first. See the related resources section
below for pointers to more resources, and earlier approaches to process
supervision that might help you understand the basics.
Installation
Requirements
- A POSIX-compliant system with a standard C development environment
- GNU make, version 3.81 or later
- skalibs version
<IP_ADDRESS> or later. It's a build-time requirement. It's also a run-time
requirement if you link against the shared version of the skalibs
library.
- (Optional, but really recommended for full functionality):
execline version
<IP_ADDRESS> or later. When s6 is built with execline support (which is the default),
execline is a build-time requirement, and also a run-time requirement for
certain binaries that spawn scripts interpreted with
execlineb.
The following optional dependencies are also supported:
- If you're using musl and
want nsswitch-like functionality:
nsss version
<IP_ADDRESS> or later (build-time and boot-time)
Licensing
s6 is free software. It is available under the
ISC license.
Download
Compilation
- See the enclosed INSTALL file for installation details.
Upgrade notes
- This page lists the differences to be aware of between
the previous versions of s6 and the current one.
Reference
If you prefer to read this documentation as man pages, it is now possible!
There is a project that
ports the s6 documentation to a set of man pages.
Commands
All these commands exit 111 if they encounter a temporary error, and
100 if they encounter a permanent error - such as a misuse. They exit
127 if they're trying to execute into a program and cannot find it, and
126 if they fail to execute into a program for another reason.
Short-lived commands exit 0 on success.
Supervision system
s6-svscan and s6-supervise
are the long-lived processes maintaining the supervision tree. Other programs are
a user interface to control those processes and monitor service states.
Daemontools-like utilities
These programs are a rewrite of the corresponding utilities from
daemontools, with
a few extras.
Fifodir management, notification and subscription
These programs are a clean rewrite of the obsolete "pipe-tools" package; they
are now based on a properly designed notification library.
They provide a command-line interface to
inter-process notification and
synchronization.
Local service management and access control
suidless privilege gain
Logging
Management of user supervision trees
Management of dynamic instances
Timed lock acquisition
fd-holding, a.k.a. the sensible part of socket activation
Libraries
Definitions
Related resources
s6 manual pages
Other components for s6-based init systems
- s6-linux-init
is a package to help you create a /sbin/init binary booting a
Linux system with s6-svscan as process 1.
- s6-overlay
is a project that automates integration of s6 into Docker images.
- s6-rc is a
dependency-based service manager for s6.
- anopa is another dependency-based
service manager for s6.
s6 discussion
- s6 is discussed on the
supervision mailing-list.
- There is a #s6 IRC channel on OFTC. Sometimes people are there
and answer questions.
Similar work
- daemontools, the pioneering
process supervision software suite.
- daemontools-encore,
a derived work from daemontools with enhancements. (Note that although s6 follows
the same naming scheme, the same general design, and many of the same architecture
choices as daemontools, it is still original work, sharing no code at all with
daemontools.)
- runit, a slightly different
approach to process supervision, with the same goals.
- perp, yet another slightly different
approach to process supervision, also with the same goals.
- nosh
is another suite of system-level utilities with similarities in the design
and approach. It is written in C++, though, and is coded in quite a
different way than the previous items on this list.
Other init systems
(This list hasn't been updated in a long while. I'm keeping it for reference.)
- Felix von Leitner's minit is an
init system for Linux, with process supervision capabilities.
- suckless init is
considered by many as the smallest possible init. I disagree: suckless
init is incorrect, because it
has no supervision capabilities, and thus, killing all processes but init
can brick the machine. Nevertheless, suckless init, like many other
suckless projects, is a neat exercise in minimalism.
- sysvinit is the
traditional init system for Linux.
- Upstart is a well-known init system
for Linux, with complete service management, that came with earlier versions of the Ubuntu
distribution. It is now deprecated.
- systemd is a problem in its own category.
- The various BSD flavors have their own style of
init.
- MacOS X has its own init spaghetti monster called
launchd.
All-in-one init systems generally feel complex and convoluted, and when most
people find out about the process supervision approach to init systems, they
usually find it much simpler.
There is a good reason for this.
Miscellaneous
Why "s6" ?
skarnet.org's small and secure
supervision software suite.
Also, s6 is a nice command name prefix to have: it identifies the origin of the
software, and it's short. Expect more use of s6- in future skarnet.org software
releases. And please avoid using that prefix for your own projects.
Footnotes
[1]
Take everything you read on that link with two or three salt shakers.
(This is true for anything written by the author of that document.)


Create New Op Mode
Rename Selected Op Mode
Copy Selected Op Mode
Delete Selected Op Modes
Download Selected Op Modes
Help
My Op Modes
Op Mode Name
Date Modified
Op Mode name:
Cancel
OK
Delete Selected Op Modes
Are you sure you want to delete these Op Modes?
No
Yes


You can reach this dialog via the menu entry Analysis \ Analyze Randomness \ FIPS PUB-140-1 Test Battery. The prerequisition is, that you have loaded a document of at least 2500 bytes length.
A default dialog for the FIPS-PUB-140-1 test battery looks like this:
In this dialog there are no parameters to choose from. The individual FIPS-PUB-140-1 tests are automatically performed.
Within "Entropy state" you additionaly get the entropy of the file examined. For every individual test the user is informed whether the test has been passed or not.
The test battery is only passed if all four individual tests are passed.
If one or more tests are failed, then the dialog looks like this: