-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS> Sun Jan 4 07:39:14 2015 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: AutoShift Device,speed: LCMXO2-7000HE,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 1.200 V ================================================================================ Preference: FREQUENCY NET "osc_clk_c_c" 2.080000 MHz ; 55 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i0 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_0 to SLICE_0 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 CTOF_DEL --- 0.116 R4C9A.A1 to R4C9A.F1 SLICE_0 ROUTE 1 0.000 R4C9A.F1 to R4C9A.DI1 n56 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_1 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 CTOF_DEL --- 0.116 R4C9C.A0 to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_1 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 CTOF_DEL --- 0.116 R4C9C.A1 to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i1 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_3 to SLICE_3 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 CTOF_DEL --- 0.116 R4C9B.A0 to R4C9B.F0 SLICE_3 ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 n55 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_3 to SLICE_3 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 CTOF_DEL --- 0.116 R4C9B.A1 to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.435ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.420ns (64.3% logic, 35.7% route), 2 logic levels. Constraint Details: 0.420ns physical path delay SLICE_5 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.435ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.150 R4C9D.Q0 to R4C9D.A0 n5 CTOF_DEL --- 0.116 R4C9D.A0 to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.420 (64.3% logic, 35.7% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i9 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.423ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.423ns physical path delay SLICE_2 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.438ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10B.CLK to R4C10B.Q0 SLICE_2 (from osc_clk_c_c) ROUTE 13 0.153 R4C10B.Q0 to R4C10B.A0 cnt_9 CTOF_DEL --- 0.116 R4C10B.A0 to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.423 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i8 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.423ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.423ns physical path delay SLICE_4 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.438ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10A.CLK to R4C10A.Q1 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.153 R4C10A.Q1 to R4C10A.A1 cnt_8 CTOF_DEL --- 0.116 R4C10A.A1 to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.423 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.423ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.423ns physical path delay SLICE_4 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.438ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.153 R4C10A.Q0 to R4C10A.A0 cnt_7 CTOF_DEL --- 0.116 R4C10A.A0 to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.423 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.438ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.423ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.423ns physical path delay SLICE_5 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.438ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.153 R4C9D.Q1 to R4C9D.A1 cnt_6 CTOF_DEL --- 0.116 R4C9D.A1 to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.423 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 0.564ns (73.4% logic, 26.6% route), 2 logic levels. Constraint Details: 0.564ns physical path delay SLICE_1 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.579ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 CTOF1_DEL --- 0.260 R4C9C.A0 to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 0.564 (73.4% logic, 26.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 0.564ns (73.4% logic, 26.6% route), 2 logic levels. Constraint Details: 0.564ns physical path delay SLICE_3 to SLICE_3 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.579ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 CTOF1_DEL --- 0.260 R4C9B.A0 to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 0.564 (73.4% logic, 26.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.564ns (73.4% logic, 26.6% route), 2 logic levels. Constraint Details: 0.564ns physical path delay SLICE_5 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.579ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.150 R4C9D.Q0 to R4C9D.A0 n5 CTOF1_DEL --- 0.260 R4C9D.A0 to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.564 (73.4% logic, 26.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.582ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.567ns (73.0% logic, 27.0% route), 2 logic levels. Constraint Details: 0.567ns physical path delay SLICE_4 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.582ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.153 R4C10A.Q0 to R4C10A.A0 cnt_7 CTOF1_DEL --- 0.260 R4C10A.A0 to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.567 (73.0% logic, 27.0% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.751ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i1 (to osc_clk_c_c +) Delay: 0.736ns (79.6% logic, 20.4% route), 3 logic levels. Constraint Details: 0.736ns physical path delay SLICE_0 to SLICE_3 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.751ns Physical Path Details: Data path SLICE_0 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOF0_DE --- 0.172 R4C9B.FCI to R4C9B.F0 SLICE_3 ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 n55 (to osc_clk_c_c) -------- 0.736 (79.6% logic, 20.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.751ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.736ns (79.6% logic, 20.4% route), 3 logic levels. Constraint Details: 0.736ns physical path delay SLICE_1 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.751ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.260 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.172 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.736 (79.6% logic, 20.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.751ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 0.736ns (79.6% logic, 20.4% route), 3 logic levels. Constraint Details: 0.736ns physical path delay SLICE_3 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.751ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.172 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 0.736 (79.6% logic, 20.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.754ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i8 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.739ns (79.3% logic, 20.7% route), 3 logic levels. Constraint Details: 0.739ns physical path delay SLICE_4 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.754ns Physical Path Details: Data path SLICE_4 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10A.CLK to R4C10A.Q1 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.153 R4C10A.Q1 to R4C10A.A1 cnt_8 C1TOFCO_DE --- 0.260 R4C10A.A1 to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.739 (79.3% logic, 20.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.754ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.739ns (79.3% logic, 20.7% route), 3 logic levels. Constraint Details: 0.739ns physical path delay SLICE_5 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.754ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.153 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.260 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.739 (79.3% logic, 20.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.767ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 0.752ns (80.1% logic, 19.9% route), 3 logic levels. Constraint Details: 0.752ns physical path delay SLICE_0 to SLICE_3 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.767ns Physical Path Details: Data path SLICE_0 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOF1_DE --- 0.188 R4C9B.FCI to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 0.752 (80.1% logic, 19.9% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.767ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.752ns (80.1% logic, 19.9% route), 3 logic levels. Constraint Details: 0.752ns physical path delay SLICE_1 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.767ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.260 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.188 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.752 (80.1% logic, 19.9% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.767ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 0.752ns (80.1% logic, 19.9% route), 3 logic levels. Constraint Details: 0.752ns physical path delay SLICE_3 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.767ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.188 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 0.752 (80.1% logic, 19.9% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.770ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.755ns (79.7% logic, 20.3% route), 3 logic levels. Constraint Details: 0.755ns physical path delay SLICE_5 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.770ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.153 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.260 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.755 (79.7% logic, 20.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.778ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 0.763ns (80.3% logic, 19.7% route), 4 logic levels. Constraint Details: 0.763ns physical path delay SLICE_0 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.778ns Physical Path Details: Data path SLICE_0 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.172 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 0.763 (80.3% logic, 19.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.778ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.763ns (80.3% logic, 19.7% route), 4 logic levels. Constraint Details: 0.763ns physical path delay SLICE_1 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.778ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.260 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.763 (80.3% logic, 19.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.778ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.763ns (80.3% logic, 19.7% route), 4 logic levels. Constraint Details: 0.763ns physical path delay SLICE_3 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.778ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.172 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.763 (80.3% logic, 19.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.781ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.766ns (80.0% logic, 20.0% route), 4 logic levels. Constraint Details: 0.766ns physical path delay SLICE_5 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.781ns Physical Path Details: Data path SLICE_5 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.153 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.260 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.766 (80.0% logic, 20.0% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.790ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.775ns (80.6% logic, 19.4% route), 3 logic levels. Constraint Details: 0.775ns physical path delay SLICE_1 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.790ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.299 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.172 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.775 (80.6% logic, 19.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.790ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 0.775ns (80.6% logic, 19.4% route), 3 logic levels. Constraint Details: 0.775ns physical path delay SLICE_3 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.790ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.172 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 0.775 (80.6% logic, 19.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.790ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.775ns (80.6% logic, 19.4% route), 3 logic levels. Constraint Details: 0.775ns physical path delay SLICE_5 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.790ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.150 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.299 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.775 (80.6% logic, 19.4% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.793ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.778ns (80.3% logic, 19.7% route), 3 logic levels. Constraint Details: 0.778ns physical path delay SLICE_4 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.793ns Physical Path Details: Data path SLICE_4 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.153 R4C10A.Q0 to R4C10A.A0 cnt_7 C0TOFCO_DE --- 0.299 R4C10A.A0 to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.778 (80.3% logic, 19.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.794ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 0.779ns (80.7% logic, 19.3% route), 4 logic levels. Constraint Details: 0.779ns physical path delay SLICE_0 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.794ns Physical Path Details: Data path SLICE_0 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.188 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 0.779 (80.7% logic, 19.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.794ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.779ns (80.7% logic, 19.3% route), 4 logic levels. Constraint Details: 0.779ns physical path delay SLICE_1 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.794ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.260 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.779 (80.7% logic, 19.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.794ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.779ns (80.7% logic, 19.3% route), 4 logic levels. Constraint Details: 0.779ns physical path delay SLICE_3 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.794ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.188 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.779 (80.7% logic, 19.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.805ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.790ns (81.0% logic, 19.0% route), 5 logic levels. Constraint Details: 0.790ns physical path delay SLICE_0 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.805ns Physical Path Details: Data path SLICE_0 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.172 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.790 (81.0% logic, 19.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.805ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.790ns (81.0% logic, 19.0% route), 5 logic levels. Constraint Details: 0.790ns physical path delay SLICE_1 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.805ns Physical Path Details: Data path SLICE_1 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.260 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.790 (81.0% logic, 19.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.805ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.790ns (81.0% logic, 19.0% route), 5 logic levels. Constraint Details: 0.790ns physical path delay SLICE_3 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.805ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.790 (81.0% logic, 19.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.806ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.791ns (81.0% logic, 19.0% route), 3 logic levels. Constraint Details: 0.791ns physical path delay SLICE_1 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.806ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.299 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.188 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.791 (81.0% logic, 19.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.806ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 0.791ns (81.0% logic, 19.0% route), 3 logic levels. Constraint Details: 0.791ns physical path delay SLICE_3 to SLICE_1 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.806ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.188 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 0.791 (81.0% logic, 19.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.806ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.791ns (81.0% logic, 19.0% route), 3 logic levels. Constraint Details: 0.791ns physical path delay SLICE_5 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.806ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.150 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.299 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.791 (81.0% logic, 19.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.817ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.802ns (81.3% logic, 18.7% route), 4 logic levels. Constraint Details: 0.802ns physical path delay SLICE_1 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.817ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.299 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.802 (81.3% logic, 18.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.817ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 0.802ns (81.3% logic, 18.7% route), 4 logic levels. Constraint Details: 0.802ns physical path delay SLICE_3 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.817ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.172 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 0.802 (81.3% logic, 18.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.817ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.802ns (81.3% logic, 18.7% route), 4 logic levels. Constraint Details: 0.802ns physical path delay SLICE_5 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.817ns Physical Path Details: Data path SLICE_5 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.150 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.299 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.802 (81.3% logic, 18.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.821ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.806ns (81.4% logic, 18.6% route), 5 logic levels. Constraint Details: 0.806ns physical path delay SLICE_0 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.821ns Physical Path Details: Data path SLICE_0 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.188 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.806 (81.4% logic, 18.6% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.821ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.806ns (81.4% logic, 18.6% route), 5 logic levels. Constraint Details: 0.806ns physical path delay SLICE_3 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.821ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.806 (81.4% logic, 18.6% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.832ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.817ns (81.6% logic, 18.4% route), 6 logic levels. Constraint Details: 0.817ns physical path delay SLICE_0 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.832ns Physical Path Details: Data path SLICE_0 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.817 (81.6% logic, 18.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.832ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.817ns (81.6% logic, 18.4% route), 6 logic levels. Constraint Details: 0.817ns physical path delay SLICE_3 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.832ns Physical Path Details: Data path SLICE_3 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.260 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.817 (81.6% logic, 18.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.833ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.818ns (81.7% logic, 18.3% route), 4 logic levels. Constraint Details: 0.818ns physical path delay SLICE_1 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.833ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.299 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.818 (81.7% logic, 18.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.833ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 0.818ns (81.7% logic, 18.3% route), 4 logic levels. Constraint Details: 0.818ns physical path delay SLICE_3 to SLICE_5 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.833ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.188 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 0.818 (81.7% logic, 18.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.844ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.829ns (81.9% logic, 18.1% route), 5 logic levels. Constraint Details: 0.829ns physical path delay SLICE_1 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.844ns Physical Path Details: Data path SLICE_1 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.150 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.299 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.829 (81.9% logic, 18.1% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.844ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 0.829ns (81.9% logic, 18.1% route), 5 logic levels. Constraint Details: 0.829ns physical path delay SLICE_3 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.844ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.172 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 0.829 (81.9% logic, 18.1% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.848ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.833ns (82.0% logic, 18.0% route), 6 logic levels. Constraint Details: 0.833ns physical path delay SLICE_0 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.848ns Physical Path Details: Data path SLICE_0 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.833 (82.0% logic, 18.0% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.859ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.844ns (82.2% logic, 17.8% route), 7 logic levels. Constraint Details: 0.844ns physical path delay SLICE_0 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.859ns Physical Path Details: Data path SLICE_0 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.150 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.260 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.027 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.844 (82.2% logic, 17.8% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.860ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 0.845ns (82.2% logic, 17.8% route), 5 logic levels. Constraint Details: 0.845ns physical path delay SLICE_3 to SLICE_4 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.860ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.188 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 0.845 (82.2% logic, 17.8% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.871ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 0.856ns (82.5% logic, 17.5% route), 6 logic levels. Constraint Details: 0.856ns physical path delay SLICE_3 to SLICE_2 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.871ns Physical Path Details: Data path SLICE_3 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.154 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.150 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.299 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.027 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.027 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.027 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.172 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 0.856 (82.5% logic, 17.5% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 1.445 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 1.445 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "osc_clk_c_c" 2.080000 | | | MHz ; | 0.000 ns| 0.435 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: n1378 Source: SLICE_25.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: osc_clk_c_c Source: OSCH_inst.OSC Loads: 6 Covered under: FREQUENCY NET "osc_clk_c_c" 2.080000 MHz ; Clock Domain: latch_c Source: latch.PAD Loads: 11 No transfer within this clock domain is found Clock Domain: n1377 Source: SLICE_26.F1 Loads: 15 No transfer within this clock domain is found Clock Domain: clk_c Source: clk.PAD Loads: 12 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 55 paths, 1 nets, and 191 connections (65.19% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0)


Philippine police say will arrest anyone flouting vaping ban
by AFPMANILA: Philippine police were ordered Wednesday to arrest anyone caught vaping in public, just hours after Philippine President Rodrigo Duterte announced he would ban e-cigarettes.
The abrupt prohibition, revealed by Duterte late Tuesday adds to a growing global backlash against a product once promoted as less harmful than tobacco smoking.
Duterte, a former smoker, called the devices “toxic” and said vaping introduced “chemicals” into the user’s body.
He ordered the arrest of anyone vaping publicly in a country that already has some of Asia’s toughest anti-smoking rules.
No formal, written order has been made public that spells out the scope of the ban or penalties for violations.
Duterte is notorious internationally for his deadly anti-narcotics crackdown, but he has also targeted tobacco with a wide-ranging ban on smoking in public.
Citing “the order of the president”, on Wednesday a statement from the head of the Philippine police ordered “effective today, all police units nationwide to enforce the ban on the use of vapes; ensure that all violators will be arrested”.
The ban came days after Philippine health authorities reported the nation’s first vaping-related lung injury, which resulted in a 16-year-old girl being hospitalised.
Vaping has taken off in the Philippines, with speciality shops and vapers puffing away in public a common sight.
E-cigarette users were caught off guard by the ban and questioned the utility of arresting people who, at worst, were hurting themselves.
“It’s inappropriate. In any case, we don’t hurt people, the environment or animals,” said 22-year-old student Alexis Martin.
“Why are vapers being targeted?”
E-cigarettes warm flavoured liquid to produce vapour that is free of the estimated 7,000 chemicals in tobacco smoke, but does contain a number of substances that could potentially be harmful.
Critics say that apart from being harmful in themselves, the multiple exotic flavours of e-cigarette liquids appeal particularly to youngsters and risk getting them addicted to nicotine.
The devices have become hugely popular in the past decade but a rash of vaping-linked deaths and illnesses in the United States is feeding caution about the product, already banned in some places.
In September 2019 India became the latest country to ban the import, sale, production and advertising of e-cigarettes, citing in particular concerns for its youth.
The devices are already banned in several places such as Brazil, Singapore, Thailand and the US state of Massachusetts.


The Best Samsung and Acer Amazon Black Friday 2019 Deals on Monitors
by Nhx TingsonBlack Friday sale is fast approaching, and consumers are most likely preparing their wallets for the biggest deals of the year, including the best deals on computer accessories and monitors.
While it's common for people to flock retailers on the day of the sale itself, online shopping has also become a huge trend in the past few years, and even eCommerce giants such as Amazon have their own big deals for both Black Friday and Cyber Monday.
For those who are looking for tech deals this Black Friday, Amazon is also offering some of the best deals on different techs—from smartphones to computer monitors.
Samsung Amazon Monitor Deals
Here are some of the gaming and professional computer monitors we have seen on Amazon so far:
Samsung is offering some great deals on some of their monitors, where you can save up to 37%, including the following deals:
Samsung LC27F398FWNXZA Samsung C27F398 27-Inch Curved LED Monitor for $149.99 (originally priced at $219.99) - get 32% off
(Photo : Amazon)
Samsung monitors are on sale for Black Friday 2019 on Amazon.
This monitor features a 1800R curvature, a slim design, and a super speedy 4ms response time.
Under this deal, you can also get the Samsung Electronics LC27F398FWNXZA Samsung C27F398 27-Inch Curved Monitor & Logitech MK345 Wireless Keyboard and Mouse Combo for $180.98 which includes a full-sized keyboard and a right-handed mouse.
Samsung 49-Inch CRG90 Curved Gaming Monitor LC49RG90SSNXZA for $1,049.99 (originally at $1,499.99) - get 30% off
If you're looking for a wide-screen experience, this 49-inch curved Samsung monitor is on sale this Black Friday season, and you can now save $450. It has 4ms response speed, 5120x1440p resolution, and FreeSync 2 with HDR, and HDMI.
Samsung LS27F354FHNXZA 27-Inch FHD Flat Monitor for $119.99 (formerly at $189.99) - get 37% off
(Photo : Amazon)
Samsung monitors are on sale for Black Friday.
So far, this Samsung 27-inch flat monitor has the highest discount on Amazon Black Friday deals. This screen is perfect for gaming, especially with its slim bezels for a wider screen and full-immersion. It also comes with AMD Free Sync.
The Space by Samsung LS27R750UENXZA 27-Inch WQHD Bezel-less Monitor with Height Adjustable Arm Stand for $369.99 (initially at $499.99)
(Photo : Amazon)
This monitor comes with adjustable stand.
This monitor comes with an adjustable arm stand that can help you save some desk space, or adjust its height for more comfort. Its bezel-less design also guarantees full-immersion when you're gaming or watching.
ALSO READ: Amazon Black Friday Deals 2019: Here are the Best Offers You can Get Now!
Acer Amazon Deals
Acer gaming monitors are also on sale on Amazon, including the following:
Acer GN246HL Bbid 24-Inch Full HD Widescreen 3D Gaming Monitor for $153.99 (originally at $199.99) - get 23% off
(Photo : Amazon)
Acer gaming monitors are also on sale this Black Friday on Amazon.
This gaming monitor can support full-HD gaming and multimedia experience, so it's great if you want to see the details on the games you're playing or videos you're watching. Additionally, this has a rapid 1ms response time, plus DVI, VGA, and HDMI inputs.
Acer KG221Q 21.5-Inch Gaming Monitor for $94.99 (originally priced at $109.99)
(Photo : Amazon)
Acer has some gaming monitors on huge discounts for Amazon Black Friday.
If you don't have much budget for a gaming monitor, this is the perfect deal as you can already get a good gaming monitor for under $100. It boasts a rapid 1ms response time and AMD FreeSync Technology.


Class: Example.Animal.Lion
| Defined in: | node_modules/codo/spec/_templates/example/src/lion.coffee |
| Inherits: | Example.Animal |
| Extends: | MissingMixin |
| Includes: | Example.AngryAnimal |
Overview
A dangerous lion. Take care.
Variables Summary
- MAX_SPEED =
-
50
Maximum speed in MPH
Variable inherited from Example.Animal
Instance Method Summary
- # (void) move(direction, speed) Move the lion fast
- # (void) escape(direction) Escape at maximum speed.
Inherited Method Summary
Methods inherited from
Example.Animal
Included Method Summary
Methods included from Example.AngryAnimal
Instance Method Details
#
(void)
move(direction, speed)
Move the lion fast
#
(void)
escape(direction)
Escape at maximum speed.
@param (see #move)


This page describes briefly the command line options to timberc, the Timber compiler. Installation is not described.
timberc expects a number of options and a number of files to compile. The most common uses are the following:
The given files are compiled (first to C by the timber compiler, then to object files by the C compiler). No linking takes place. This usage requires that all files on which the given modules depend have already been compiled. This is the typical way to compile new modules during the development of a Timber system. Can be modified to option -C to avoid C compilation.
The compiler expects Mod.t to be the root module of a system for the default environment (i.e. POSIX). All modules in the system are compiled by timberc and gcc as needed and in dependency order, followed by linking. The executable is called Mod. This option obviates the need of a makefile to rebuild the system after changes in any modules. Can be combined with --root=name when the name of the root definition is name (rather than the default root).
Displays the API of module Mod, i.e. all exported kinds, types, defaults and top-level values with their types, typically in a browser window (installation-dependent).


MASTER COMPUTER VISION'S BOOTCAMP
Welcome to enjoyfull adventure to become a computer vision engineer, we are excited to have you in our online bootcamp.
2021.10.15(THU) ~ 16(FRI)
@ ComputerVZ Companie - León, GTO.
Welcome to enjoyfull adventure to become a computer vision engineer, we are excited to have you in our online bootcamp.
@ ComputerVZ Companie - León, GTO.
You just need one computer and programming fundamentals to start our course from scratch to hero in computer vision area.
Study from anywhere according to your current location, everything is going to be online with flexible times to complete it.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.
He studied in Oxford California at Data Scientis Carreer, but now he is teacher at most common libraries in Python for Data Scientist.