|
NANO100_BSP V3.04.001
The Board Support Package for Nano100BN Series
|
Macros | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
Variables | |
| __I uint32_t | ADC_T::RESULT [18] |
| __IO uint32_t | ADC_T::CR |
| __IO uint32_t | ADC_T::CHEN |
| __IO uint32_t | ADC_T::CMPR0 |
| __IO uint32_t | ADC_T::CMPR1 |
| __IO uint32_t | ADC_T::SR |
| uint32_t | ADC_T::RESERVE0 [1] |
| __I uint32_t | ADC_T::PDMA |
| __IO uint32_t | ADC_T::PWRCTL |
| __IO uint32_t | ADC_T::CALCTL |
| __IO uint32_t | ADC_T::CALWORD |
| __IO uint32_t | ADC_T::SMPLCNT0 |
| __IO uint32_t | ADC_T::SMPLCNT1 |
| __IO uint32_t | CLK_T::PWRCTL |
| __IO uint32_t | CLK_T::AHBCLK |
| __IO uint32_t | CLK_T::APBCLK |
| __I uint32_t | CLK_T::CLKSTATUS |
| __IO uint32_t | CLK_T::CLKSEL0 |
| __IO uint32_t | CLK_T::CLKSEL1 |
| __IO uint32_t | CLK_T::CLKSEL2 |
| __IO uint32_t | CLK_T::CLKDIV0 |
| __IO uint32_t | CLK_T::CLKDIV1 |
| __IO uint32_t | CLK_T::PLLCTL |
| __IO uint32_t | CLK_T::FRQDIV |
| __IO uint32_t | CLK_T::MCLKO |
| __IO uint32_t | CLK_T::WK_INTSTS |
| __IO uint32_t | DAC_T::CTL0 |
| __IO uint32_t | DAC_T::DATA0 |
| __IO uint32_t | DAC_T::STS0 |
| uint32_t | DAC_T::RESERVE0 [1] |
| __IO uint32_t | DAC_T::CTL1 |
| __IO uint32_t | DAC_T::DATA1 |
| __IO uint32_t | DAC_T::STS1 |
| uint32_t | DAC_T::RESERVE1 [1] |
| __IO uint32_t | DAC_T::COMCTL |
| __IO uint32_t | EBI_T::EBICON |
| __IO uint32_t | EBI_T::EXTIME |
| __IO uint32_t | FMC_T::ISPCON |
| __IO uint32_t | FMC_T::ISPADR |
| __IO uint32_t | FMC_T::ISPDAT |
| __IO uint32_t | FMC_T::ISPCMD |
| __IO uint32_t | FMC_T::ISPTRG |
| __I uint32_t | FMC_T::DFBADR |
| uint32_t | FMC_T::RESERVE0 [10] |
| __IO uint32_t | FMC_T::ISPSTA |
| __I uint32_t | SYS_T::PDID |
| __IO uint32_t | SYS_T::RST_SRC |
| __IO uint32_t | SYS_T::IPRST_CTL1 |
| __IO uint32_t | SYS_T::IPRST_CTL2 |
| uint32_t | SYS_T::RESERVE0 [4] |
| __IO uint32_t | SYS_T::TEMPCTL |
| uint32_t | SYS_T::RESERVE1 [3] |
| __IO uint32_t | SYS_T::PA_L_MFP |
| __IO uint32_t | SYS_T::PA_H_MFP |
| __IO uint32_t | SYS_T::PB_L_MFP |
| __IO uint32_t | SYS_T::PB_H_MFP |
| __IO uint32_t | SYS_T::PC_L_MFP |
| __IO uint32_t | SYS_T::PC_H_MFP |
| __IO uint32_t | SYS_T::PD_L_MFP |
| __IO uint32_t | SYS_T::PD_H_MFP |
| __IO uint32_t | SYS_T::PE_L_MFP |
| __IO uint32_t | SYS_T::PE_H_MFP |
| __IO uint32_t | SYS_T::PF_L_MFP |
| uint32_t | SYS_T::RESERVE2 [1] |
| __IO uint32_t | SYS_T::PORCTL |
| __IO uint32_t | SYS_T::BODCTL |
| __IO uint32_t | SYS_T::BODSTS |
| __IO uint32_t | SYS_T::Int_VREFCTL |
| uint32_t | SYS_T::RESERVE3 [4] |
| __IO uint32_t | SYS_T::IRCTRIMCTL |
| __IO uint32_t | SYS_T::IRCTRIMIEN |
| __IO uint32_t | SYS_T::IRCTRIMINT |
| uint32_t | SYS_T::RESERVE4 [29] |
| __IO uint32_t | SYS_T::RegLockAddr |
| __IO uint32_t | GPIO_T::PMD |
| __IO uint32_t | GPIO_T::OFFD |
| __IO uint32_t | GPIO_T::DOUT |
| __IO uint32_t | GPIO_T::DMASK |
| __I uint32_t | GPIO_T::PIN |
| __IO uint32_t | GPIO_T::DBEN |
| __IO uint32_t | GPIO_T::IMD |
| __IO uint32_t | GPIO_T::IER |
| __IO uint32_t | GPIO_T::ISRC |
| __IO uint32_t | GPIO_T::PUEN |
| __IO uint32_t | GP_DB_T::DBNCECON |
| __IO uint32_t | I2C_T::CON |
| __IO uint32_t | I2C_T::INTSTS |
| __I uint32_t | I2C_T::STATUS |
| __IO uint32_t | I2C_T::DIV |
| __IO uint32_t | I2C_T::TOUT |
| __IO uint32_t | I2C_T::DATA |
| __IO uint32_t | I2C_T::SADDR0 |
| __IO uint32_t | I2C_T::SADDR1 |
| uint32_t | I2C_T::RESERVE0 [2] |
| __IO uint32_t | I2C_T::SAMASK0 |
| __IO uint32_t | I2C_T::SAMASK1 |
| uint32_t | I2C_T::RESERVE1 [4] |
| __IO uint32_t | I2C_T::WKUPCON |
| __IO uint32_t | I2C_T::WKUPSTS |
| __IO uint32_t | I2S_T::CTRL |
| __IO uint32_t | I2S_T::CLKDIV |
| __IO uint32_t | I2S_T::INTEN |
| __IO uint32_t | I2S_T::STATUS |
| __O uint32_t | I2S_T::TXFIFO |
| __I uint32_t | I2S_T::RXFIFO |
| __I uint32_t | INTR_T::IRQSRC [32] |
| __IO uint32_t | INTR_T::NMI_SEL |
| __IO uint32_t | INTR_T::MCU_IRQ |
| __IO uint32_t | LCD_T::CTL |
| __IO uint32_t | LCD_T::DISPCTL |
| __IO uint32_t | LCD_T::MEM_0 |
| __IO uint32_t | LCD_T::MEM_1 |
| __IO uint32_t | LCD_T::MEM_2 |
| __IO uint32_t | LCD_T::MEM_3 |
| __IO uint32_t | LCD_T::MEM_4 |
| __IO uint32_t | LCD_T::MEM_5 |
| __IO uint32_t | LCD_T::MEM_6 |
| __IO uint32_t | LCD_T::MEM_7 |
| __IO uint32_t | LCD_T::MEM_8 |
| __IO uint32_t | LCD_T::MEM_9 |
| __IO uint32_t | LCD_T::FCR |
| __IO uint32_t | LCD_T::FCSTS |
| __IO uint32_t | DMA_CRC_T::CTL |
| __IO uint32_t | DMA_CRC_T::DMASAR |
| uint32_t | DMA_CRC_T::RESERVE0 [1] |
| __IO uint32_t | DMA_CRC_T::DMABCR |
| uint32_t | DMA_CRC_T::RESERVE1 [1] |
| __I uint32_t | DMA_CRC_T::DMACSAR |
| uint32_t | DMA_CRC_T::RESERVE2 [1] |
| __I uint32_t | DMA_CRC_T::DMACBCR |
| __IO uint32_t | DMA_CRC_T::DMAIER |
| __IO uint32_t | DMA_CRC_T::DMAISR |
| uint32_t | DMA_CRC_T::RESERVE3 [22] |
| __IO uint32_t | DMA_CRC_T::WDATA |
| __IO uint32_t | DMA_CRC_T::SEED |
| __I uint32_t | DMA_CRC_T::CHECKSUM |
| __IO uint32_t | DMA_GCR_T::GCRCSR |
| __IO uint32_t | DMA_GCR_T::DSSR0 |
| __IO uint32_t | DMA_GCR_T::DSSR1 |
| __I uint32_t | DMA_GCR_T::GCRISR |
| __IO uint32_t | PDMA_T::CSR |
| __IO uint32_t | PDMA_T::SAR |
| __IO uint32_t | PDMA_T::DAR |
| __IO uint32_t | PDMA_T::BCR |
| uint32_t | PDMA_T::RESERVE0 [1] |
| __I uint32_t | PDMA_T::CSAR |
| __I uint32_t | PDMA_T::CDAR |
| __I uint32_t | PDMA_T::CBCR |
| __IO uint32_t | PDMA_T::IER |
| __IO uint32_t | PDMA_T::ISR |
| __IO uint32_t | PDMA_T::TCR |
| __IO uint32_t | VDMA_T::CSR |
| __IO uint32_t | VDMA_T::SAR |
| __IO uint32_t | VDMA_T::DAR |
| __IO uint32_t | VDMA_T::BCR |
| uint32_t | VDMA_T::RESERVE0 [1] |
| __I uint32_t | VDMA_T::CSAR |
| __I uint32_t | VDMA_T::CDAR |
| __I uint32_t | VDMA_T::CBCR |
| __IO uint32_t | VDMA_T::IER |
| __IO uint32_t | VDMA_T::ISR |
| uint32_t | VDMA_T::RESERVE1 [1] |
| __IO uint32_t | VDMA_T::SASOCR |
| __IO uint32_t | VDMA_T::DASOCR |
| __IO uint32_t | PWM_T::PRES |
| __IO uint32_t | PWM_T::CLKSEL |
| __IO uint32_t | PWM_T::CTL |
| __IO uint32_t | PWM_T::INTEN |
| __IO uint32_t | PWM_T::INTSTS |
| __IO uint32_t | PWM_T::OE |
| uint32_t | PWM_T::RESERVE0 [1] |
| __IO uint32_t | PWM_T::DUTY0 |
| __I uint32_t | PWM_T::DATA0 |
| uint32_t | PWM_T::RESERVE1 [1] |
| __IO uint32_t | PWM_T::DUTY1 |
| __I uint32_t | PWM_T::DATA1 |
| uint32_t | PWM_T::RESERVE2 [1] |
| __IO uint32_t | PWM_T::DUTY2 |
| __I uint32_t | PWM_T::DATA2 |
| uint32_t | PWM_T::RESERVE3 [1] |
| __IO uint32_t | PWM_T::DUTY3 |
| __I uint32_t | PWM_T::DATA3 |
| uint32_t | PWM_T::RESERVE4 [3] |
| __IO uint32_t | PWM_T::CAPCTL |
| __IO uint32_t | PWM_T::CAPINTEN |
| __IO uint32_t | PWM_T::CAPINTSTS |
| __I uint32_t | PWM_T::CRL0 |
| __I uint32_t | PWM_T::CFL0 |
| __I uint32_t | PWM_T::CRL1 |
| __I uint32_t | PWM_T::CFL1 |
| __I uint32_t | PWM_T::CRL2 |
| __I uint32_t | PWM_T::CFL2 |
| __I uint32_t | PWM_T::CRL3 |
| __I uint32_t | PWM_T::CFL3 |
| __I uint32_t | PWM_T::PDMACH0 |
| __I uint32_t | PWM_T::PDMACH2 |
| __IO uint32_t | RTC_T::INIR |
| __IO uint32_t | RTC_T::AER |
| __IO uint32_t | RTC_T::FCR |
| __IO uint32_t | RTC_T::TLR |
| __IO uint32_t | RTC_T::CLR |
| __IO uint32_t | RTC_T::TSSR |
| __IO uint32_t | RTC_T::DWR |
| __IO uint32_t | RTC_T::TAR |
| __IO uint32_t | RTC_T::CAR |
| __I uint32_t | RTC_T::LIR |
| __IO uint32_t | RTC_T::RIER |
| __IO uint32_t | RTC_T::RIIR |
| __IO uint32_t | RTC_T::TTR |
| uint32_t | RTC_T::RESERVE0 [2] |
| __IO uint32_t | RTC_T::SPRCTL |
| __IO uint32_t | RTC_T::SPR [20] |
| __I uint32_t SC_T::RBR | |
| __O uint32_t SC_T::THR | |
| union { | |
| __I uint32_t SC_T::RBR | |
| __O uint32_t SC_T::THR | |
| }; | |
| __IO uint32_t | SC_T::CTL |
| __IO uint32_t | SC_T::ALTCTL |
| __IO uint32_t | SC_T::EGTR |
| __IO uint32_t | SC_T::RFTMR |
| __IO uint32_t | SC_T::ETUCR |
| __IO uint32_t | SC_T::IER |
| __IO uint32_t | SC_T::ISR |
| __IO uint32_t | SC_T::TRSR |
| __IO uint32_t | SC_T::PINCSR |
| __IO uint32_t | SC_T::TMR0 |
| __IO uint32_t | SC_T::TMR1 |
| __IO uint32_t | SC_T::TMR2 |
| __IO uint32_t | SC_T::UACTL |
| __I uint32_t | SC_T::TDRA |
| __I uint32_t | SC_T::TDRB |
| __IO uint32_t | SPI_T::CTL |
| __IO uint32_t | SPI_T::STATUS |
| __IO uint32_t | SPI_T::CLKDIV |
| __IO uint32_t | SPI_T::SSR |
| __I uint32_t | SPI_T::RX0 |
| __I uint32_t | SPI_T::RX1 |
| uint32_t | SPI_T::RESERVE0 [2] |
| __O uint32_t | SPI_T::TX0 |
| __O uint32_t | SPI_T::TX1 |
| uint32_t | SPI_T::RESERVE1 [3] |
| __IO uint32_t | SPI_T::VARCLK |
| __IO uint32_t | SPI_T::DMA |
| __IO uint32_t | SPI_T::FFCTL |
| __IO uint32_t | TIMER_T::CTL |
| __IO uint32_t | TIMER_T::PRECNT |
| __IO uint32_t | TIMER_T::CMPR |
| __IO uint32_t | TIMER_T::IER |
| __IO uint32_t | TIMER_T::ISR |
| __I uint32_t | TIMER_T::DR |
| __I uint32_t | TIMER_T::TCAP |
| __I uint32_t UART_T::RBR | |
| __O uint32_t UART_T::THR | |
| union { | |
| __I uint32_t UART_T::RBR | |
| __O uint32_t UART_T::THR | |
| }; | |
| __IO uint32_t | UART_T::CTL |
| __IO uint32_t | UART_T::TLCTL |
| __IO uint32_t | UART_T::IER |
| __IO uint32_t | UART_T::ISR |
| __IO uint32_t | UART_T::TRSR |
| __IO uint32_t | UART_T::FSR |
| __IO uint32_t | UART_T::MCSR |
| __IO uint32_t | UART_T::TMCTL |
| __IO uint32_t | UART_T::BAUD |
| uint32_t | UART_T::RESERVE0 [2] |
| __IO uint32_t | UART_T::IRCR |
| __IO uint32_t | UART_T::ALT_CTL |
| __IO uint32_t | UART_T::FUN_SEL |
| __IO uint32_t | USBD_EP_T::BUFSEG |
| __IO uint32_t | USBD_EP_T::MXPLD |
| __IO uint32_t | USBD_EP_T::CFG |
| uint32_t | USBD_EP_T::RESERVE |
| __IO uint32_t | USBD_T::CTL |
| __I uint32_t | USBD_T::BUSSTS |
| __IO uint32_t | USBD_T::INTEN |
| __IO uint32_t | USBD_T::INTSTS |
| __IO uint32_t | USBD_T::FADDR |
| __I uint32_t | USBD_T::EPSTS |
| __IO uint32_t | USBD_T::BUFSEG |
| __I uint32_t | USBD_T::EPSTS2 |
| USBD_EP_T | USBD_T::EP [8] |
| uint32_t | USBD_T::RESERVE0 |
| __IO uint32_t | USBD_T::PDMA |
| __IO uint32_t | WDT_T::CTL |
| __IO uint32_t | WDT_T::IER |
| __IO uint32_t | WDT_T::ISR |
| __O uint32_t | WWDT_T::RLD |
| __IO uint32_t | WWDT_T::CR |
| __IO uint32_t | WWDT_T::IER |
| __IO uint32_t | WWDT_T::STS |
| __I uint32_t | WWDT_T::VAL |
NANO100 Legacy Constants
| #define BIT0 (0x00000001) |
Bit 0 mask of an 32 bit integer.
Definition at line 11869 of file Nano100Series.h.
| #define BIT1 (0x00000002) |
Bit 1 mask of an 32 bit integer.
Definition at line 11870 of file Nano100Series.h.
| #define BIT10 (0x00000400) |
Bit 10 mask of an 32 bit integer.
Definition at line 11879 of file Nano100Series.h.
| #define BIT11 (0x00000800) |
Bit 11 mask of an 32 bit integer.
Definition at line 11880 of file Nano100Series.h.
| #define BIT12 (0x00001000) |
Bit 12 mask of an 32 bit integer.
Definition at line 11881 of file Nano100Series.h.
| #define BIT13 (0x00002000) |
Bit 13 mask of an 32 bit integer.
Definition at line 11882 of file Nano100Series.h.
| #define BIT14 (0x00004000) |
Bit 14 mask of an 32 bit integer.
Definition at line 11883 of file Nano100Series.h.
| #define BIT15 (0x00008000) |
Bit 15 mask of an 32 bit integer.
Definition at line 11884 of file Nano100Series.h.
| #define BIT16 (0x00010000) |
Bit 16 mask of an 32 bit integer.
Definition at line 11885 of file Nano100Series.h.
| #define BIT17 (0x00020000) |
Bit 17 mask of an 32 bit integer.
Definition at line 11886 of file Nano100Series.h.
| #define BIT18 (0x00040000) |
Bit 18 mask of an 32 bit integer.
Definition at line 11887 of file Nano100Series.h.
| #define BIT19 (0x00080000) |
Bit 19 mask of an 32 bit integer.
Definition at line 11888 of file Nano100Series.h.
| #define BIT2 (0x00000004) |
Bit 2 mask of an 32 bit integer.
Definition at line 11871 of file Nano100Series.h.
| #define BIT20 (0x00100000) |
Bit 20 mask of an 32 bit integer.
Definition at line 11889 of file Nano100Series.h.
| #define BIT21 (0x00200000) |
Bit 21 mask of an 32 bit integer.
Definition at line 11890 of file Nano100Series.h.
| #define BIT22 (0x00400000) |
Bit 22 mask of an 32 bit integer.
Definition at line 11891 of file Nano100Series.h.
| #define BIT23 (0x00800000) |
Bit 23 mask of an 32 bit integer.
Definition at line 11892 of file Nano100Series.h.
| #define BIT24 (0x01000000) |
Bit 24 mask of an 32 bit integer.
Definition at line 11893 of file Nano100Series.h.
| #define BIT25 (0x02000000) |
Bit 25 mask of an 32 bit integer.
Definition at line 11894 of file Nano100Series.h.
| #define BIT26 (0x04000000) |
Bit 26 mask of an 32 bit integer.
Definition at line 11895 of file Nano100Series.h.
| #define BIT27 (0x08000000) |
Bit 27 mask of an 32 bit integer.
Definition at line 11896 of file Nano100Series.h.
| #define BIT28 (0x10000000) |
Bit 28 mask of an 32 bit integer.
Definition at line 11897 of file Nano100Series.h.
| #define BIT29 (0x20000000) |
Bit 29 mask of an 32 bit integer.
Definition at line 11898 of file Nano100Series.h.
| #define BIT3 (0x00000008) |
Bit 3 mask of an 32 bit integer.
Definition at line 11872 of file Nano100Series.h.
| #define BIT30 (0x40000000) |
Bit 30 mask of an 32 bit integer.
Definition at line 11899 of file Nano100Series.h.
| #define BIT31 (0x80000000) |
Bit 31 mask of an 32 bit integer.
Definition at line 11900 of file Nano100Series.h.
| #define BIT4 (0x00000010) |
Bit 4 mask of an 32 bit integer.
Definition at line 11873 of file Nano100Series.h.
| #define BIT5 (0x00000020) |
Bit 5 mask of an 32 bit integer.
Definition at line 11874 of file Nano100Series.h.
| #define BIT6 (0x00000040) |
Bit 6 mask of an 32 bit integer.
Definition at line 11875 of file Nano100Series.h.
| #define BIT7 (0x00000080) |
Bit 7 mask of an 32 bit integer.
Definition at line 11876 of file Nano100Series.h.
| #define BIT8 (0x00000100) |
Bit 8 mask of an 32 bit integer.
Definition at line 11877 of file Nano100Series.h.
| #define BIT9 (0x00000200) |
Bit 9 mask of an 32 bit integer.
Definition at line 11878 of file Nano100Series.h.
| #define BYTE0_Msk (0x000000FF) |
Mask to get bit0~bit7 from a 32 bit integer.
Definition at line 11903 of file Nano100Series.h.
| #define BYTE1_Msk (0x0000FF00) |
Mask to get bit8~bit15 from a 32 bit integer.
Definition at line 11904 of file Nano100Series.h.
| #define BYTE2_Msk (0x00FF0000) |
Mask to get bit16~bit23 from a 32 bit integer.
Definition at line 11905 of file Nano100Series.h.
| #define BYTE3_Msk (0xFF000000) |
Mask to get bit24~bit31 from a 32 bit integer.
Definition at line 11906 of file Nano100Series.h.
| #define DISABLE (0) |
Disable, define to use in API parameters.
Definition at line 11866 of file Nano100Series.h.
| #define ENABLE (1) |
Enable, define to use in API parameters.
Definition at line 11865 of file Nano100Series.h.
| #define FALSE (0) |
Boolean false, define to use in API parameters or return value.
Definition at line 11863 of file Nano100Series.h.
| #define GET_BYTE0 | ( | u32Param | ) | ((u32Param & BYTE0_Msk) ) |
Extract Byte 0 (Bit 0~ 7) from parameter u32Param
Definition at line 11908 of file Nano100Series.h.
| #define GET_BYTE1 | ( | u32Param | ) | ((u32Param & BYTE1_Msk) >> 8) |
Extract Byte 1 (Bit 8~15) from parameter u32Param
Definition at line 11909 of file Nano100Series.h.
| #define GET_BYTE2 | ( | u32Param | ) | ((u32Param & BYTE2_Msk) >> 16) |
Extract Byte 2 (Bit 16~23) from parameter u32Param
Definition at line 11910 of file Nano100Series.h.
| #define GET_BYTE3 | ( | u32Param | ) | ((u32Param & BYTE3_Msk) >> 24) |
Extract Byte 3 (Bit 24~31) from parameter u32Param
Definition at line 11911 of file Nano100Series.h.
| #define NULL (0) |
NULL pointer.
Definition at line 11859 of file Nano100Series.h.
| #define TRUE (1) |
Boolean true, define to use in API parameters or return value.
Definition at line 11862 of file Nano100Series.h.
| union { ... } SC_T::@1 |
| union { ... } UART_T::@3 |
| __IO uint32_t RTC_T::AER |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | AER | RTC Register Access Enable Password (Write Only) |
| Enable RTC access after write 0xA965. Otherwise disable RTC access. | ||
| [16] | ENF | RTC Register Access Enable Flag (Read Only) |
| 1 = RTC register read/write Enabled. | ||
| 0 = RTC register read/write Disabled. | ||
| This bit will be set after AER[15:0] register is load a 0xA965, and be cleared automatically 512 RTC clocks or AER[15:0] is not 0xA965. |
Definition at line 7808 of file Nano100Series.h.
| __IO uint32_t CLK_T::AHBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GPIO_EN | GPIO Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | DMA_EN | DMA Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | ISP_EN | Flash ISP Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | EBI_EN | EBI Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | SRAM_EN | SRAM Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | TICK_EN | System Tick Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 817 of file Nano100Series.h.
| __IO uint32_t UART_T::ALT_CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | LIN_TX_BCNT | LIN TX Break Field Count Register |
| The field contains 3-bit LIN TX break field count. | ||
| Note: The break field length is LIN_TX_BCNT + 8. | ||
| [5:4] | LIN_HEAD_SEL | LIN Header Selection |
| 00 = The LIN header includes "break field". | ||
| 01 = The LIN header includes "break field + sync field". | ||
| 10 = The LIN header includes "break field + sync field + PID field". | ||
| 11 = Reserved. | ||
| [6] | LIN_RX_EN | LIN RX Enable |
| When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN) | ||
| 0 = LIN RX mode Disabled. | ||
| 1 = LIN RX mode Enabled. | ||
| [7] | LIN_TX_EN | LIN TX Header Trigger Enable |
| 0 = LIN TX Header Trigger Disabled. | ||
| 1 = LIN TX Header Trigger Enabled. | ||
| Note1: When TX header field (break field or break and sync field or break, sync and PID field) transfer operation finished, this bit will be cleared automatically and generate a interrupt to CPU (INT_LIN). | ||
| Note2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit. | ||
| [8] | Bit_ERR_EN | Bit Error Detect Enable |
| 0 = Bit error detection function Disabled. | ||
| 1 = Bit error detection Enabled. | ||
| Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN). | ||
| [16] | RS485_NMM | RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode) |
| 0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. | ||
| 1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. | ||
| Note: It can't be active in RS-485_AAD Operation mode. | ||
| [17] | RS485_AAD | RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode) |
| 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. | ||
| 1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. | ||
| Note: It can't be active in RS-485_NMM Operation mode. | ||
| [18] | RS485_AUD | RS-485 Auto Direction Mode (RS-485 AUD Mode) |
| 0 = RS-485 Auto Direction mode (AUD) Disabled. | ||
| 1 = RS-485 Auto Direction mode (AUD) Enabled. | ||
| Note: It can be active in RS-485_AAD or RS-485_NMM operation mode. | ||
| [19] | RS485_ADD_EN | RS-485 Address Detection Enable |
| This bit is used to enable RS-485 hardware address detection mode. | ||
| If hardware detects address byte, and then the controller will set UART_TRSR [RS485_ADDET_F] = "1". | ||
| 0 = Address detection mode Disabled. | ||
| 1 = Address detection mode Enabled. | ||
| Note: This field is used for RS-485 any operation mode. | ||
| [31:24] | ADDR_PID_MATCH | Address / PID Match Value Register |
| This field contains the RS-485 address match values in RS-485 Function mode. | ||
| This field contains the LIN protected identifier field n LIN Function mode, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1. | ||
| Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). |
Definition at line 10562 of file Nano100Series.h.
| __IO uint32_t SC_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TX_RST | TX Software Reset |
| When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles. | ||
| [1] | RX_RST | RX Software Reset |
| When RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles. | ||
| [2] | DACT_EN | Deactivation Sequence Generator Enable |
| This bit enables SC controller to initiate the card by deactivation sequence | ||
| 0 = No effect. | ||
| 1 = Deactivation sequence generator Enabled. | ||
| Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [3] | ACT_EN | Activation Sequence Generator Enable |
| This bit enables SC controller to initiate the card by activation sequence | ||
| 0 = No effect. | ||
| 1 = Activation sequence generator Enabled. | ||
| Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [4] | WARST_EN | Warm Reset Sequence Generator Enable |
| This bit enables SC controller to initiate the card by warm reset sequence | ||
| 0 = No effect. | ||
| 1 = Warm reset sequence generator Enabled. | ||
| Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [5] | TMR0_SEN | Internal Timer0 Start Enable |
| This bit enables Timer0 to start counting. | ||
| Software can fill "0" to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 24 bit timer when SC_CTL [TMR_SEL] = 01. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR0 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [6] | TMR1_SEN | Internal Timer1 Start Enable |
| This bit enables Timer "1" to start counting. | ||
| Software can fill 0 to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] = 01 or 10. | ||
| Don't filled TMR1_SEN when SC_CTL [TMR_SEL] = 00 or 11. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR1 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [7] | TMR2_SEN | Internal Timer2 Start Enable |
| This bit enables Timer2 to start counting. | ||
| Software can fill "0" to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] == 11. | ||
| Don't filled TMR2_SEN when SC_CTL [TMR_SEL] == 00 or 01 or 10. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR2 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [9:8] | INIT_SEL | Initial Timing Selection |
| This field indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
| [12] | RX_BGT_EN | Receiver Block Guard Time Function Enable |
| 0 = Receiver block guard time function Disabled. | ||
| 1 = Receiver block guard time function Enabled. | ||
| [13] | TMR0_ATV | Internal Timer0 Active State (Read Only) |
| This bit indicates the timer counter status of timer0. | ||
| 0 = Timer0 is not active. | ||
| 1 = Timer0 is active. | ||
| [14] | TMR1_ATV | Internal Timer1 Active State (Read Only) |
| This bit indicates the timer counter status of timer1. | ||
| 0 = Timer1 is not active. | ||
| 1 = Timer1 is active. | ||
| [15] | TMR2_ATV | Internal Timer2 Active State (Read Only) |
| This bit indicates the timer counter status of timer2. | ||
| 0 = Timer2 is not active. | ||
| 1 = Timer2 is active. |
Definition at line 8478 of file Nano100Series.h.
| __IO uint32_t CLK_T::APBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_EN | Watchdog Timer Clock Enable Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | RTC_EN | Real-Time-Clock Clock Enable Control |
| This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | TMR0_EN | Timer0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | TMR1_EN | Timer1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | TMR2_EN | Timer2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | TMR3_EN | Timer3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6] | FDIV_EN | Frequency Divider Output Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [7] | SC2_EN | SmartCard 2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [8] | I2C0_EN | I2C0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | I2C1_EN | I2C1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [12] | SPI0_EN | SPI0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [13] | SPI1_EN | SPI1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [14] | SPI2_EN | SPI2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [16] | UART0_EN | UART0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [17] | UART1_EN | UART1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [20] | PWM0_CH01_EN | PWM0 Channel 0 And Channel 1Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [21] | PWM0_CH23_EN | PWM0 Channel 2 And Channel 3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [22] | PWM1_CH01_EN | PWM1 Channel 0 And Channel 1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [23] | PWM1_CH23_EN | PWM1 Channel 2 And Channel 3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [25] | DAC_EN | 12-Bit DAC Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [26] | LCD_EN | LCD Controller Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [27] | USBD_EN | USB FS Device Controller Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [28] | ADC_EN | Analog-Digital-Converter (ADC) Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [29] | I2S_EN | I2S Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [30] | SC0_EN | SmartCard 0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [31] | SC1_EN | SmartCard 1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 908 of file Nano100Series.h.
| __IO uint32_t UART_T::BAUD |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | BRD | Baud Rate Divider |
| [31] | DIV_16_EN | Divider 16 Enable |
| The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [16 * (BRD + 1)]; The default value of M is 16. | ||
| 0 = The equation of baud rate is UART_CLK / [ (BRD+1)]. | ||
| 1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)]. | ||
| Note: In IrDA mode, this bit must disable. |
Definition at line 10487 of file Nano100Series.h.
| __IO uint32_t PDMA_T::BCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PDMA_BCR | PDMA Transfer Byte Count Register |
| This field indicates a 16-bit transfer byte count of PDMA. | ||
| Note: In Memory-to-memory (PDMA_CSR [MODE_SEL] = 00) mode, the transfer byte count must be word alignment. |
Definition at line 6000 of file Nano100Series.h.
| __IO uint32_t VDMA_T::BCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | VDMA_BCR | VDMA Transfer Byte Count Register |
| This field indicates a 16-bit transfer byte count of VDMA. | ||
| Note: In Stride Enable mode (VDMA_CSR [10] = "0"]), the transfer byte count (VDMA_BCR) must be an integer multiple of STBC (VDMA_SASOCR [31:16]). |
Definition at line 6185 of file Nano100Series.h.
| __IO uint32_t SYS_T::BODCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BOD17_EN | Brown-Out Detector 1.7V Function Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| The default value is set by flash controller user configuration register config0 bit[20:19] | ||
| Users can disable BOD17_EN but it takes effective (disabled) only in Power-down mode. | ||
| Once existing Power-down mode, BOD17 will be enabled by HW automatically. | ||
| When CPU reads this bit, CPU will read whether BOD17 function enabled or not. | ||
| In other words,CPU will always read high. | ||
| 0 = Brown-out Detector 1.7V function Disabled. | ||
| 1 = Brown-out Detector 1.7V function Enabled. | ||
| [1] | BOD20_EN | Brown-Out Detector 2.0 V Function Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Brown-out Detector 2.0 V function Disabled. | ||
| 1 = Brown-out Detector 2.0 V function Enabled. | ||
| BOD20_EN is default on. | ||
| If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode. | ||
| If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically. | ||
| [2] | BOD25_EN | Brown-Out Detector 2.5 V Function Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Brown-out Detector 2.5 V function Disabled. | ||
| 1 = Brown-out Detector 2.5 V function Enabled. | ||
| [4] | BOD17_RST_EN | BOD 1.7 V Reset Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Reset does not issue when BOD17 occurs. | ||
| 1 = Reset issues when BOD17 occurs. | ||
| The default value is set by flash controller user configuration register config0 bit[20:19] | ||
| BOD17_RST_EN can be controlled (enable or disable) only when BOD17_EN is high. | ||
| [5] | BOD20_RST_EN | BOD 2.0 V Reset Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Reset does not issue when BOD20 occurs. | ||
| 1 = Reset issues when BOD20 occurs. | ||
| The default value is set by flash controller user configuration register config0 bit[20:19] | ||
| [6] | BOD25_RST_EN | BOD 2.5 V Reset Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Reset does not issue when BOD25 occurs. | ||
| 1 = Reset issues when BOD25 occurs. | ||
| The default value is set by flash controller user configuration register config0 bit[20:19] | ||
| [8] | BOD17_INT_EN | BOD 1.7 V Interrupt Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Interrupt does not issue when BOD17 occurs. | ||
| 1 = Interrupt issues when BOD17 occurs. | ||
| [9] | BOD20_INT_EN | BOD 2.0 V Interrupt Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Interrupt does not issue when BOD20 occurs. | ||
| 1 = Interrupt issues when BOD20 occurs. | ||
| [10] | BOD25_INT_EN | BOD 2.5 V Interrupt Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Interrupt does not issue when BOD25 occurs. | ||
| 1 = Interrupt issues when BOD25 occurs. |
Definition at line 2774 of file Nano100Series.h.
| __IO uint32_t SYS_T::BODSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BOD_INT | Brown-Out Detector Interrupt Status |
| 1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1. | ||
| 0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled. | ||
| This bit is cleared by writing 1 to itself. | ||
| [1] | BOD17_drop | Brown-Out Detector Lower Than 1.7V Status |
| Setting BOD17_drop high means once the detected voltage is lower than target detected voltage setting (1.7V). | ||
| Software can write 1 to clear BOD17_drop. | ||
| [2] | BOD20_drop | Brown-Out Detector Lower Than 2.0V Status |
| Setting BOD20_drop high means once the detected voltage is lower than target detected voltage setting (2.0V). | ||
| Software can write 1 to clear BOD20_drop. | ||
| [3] | BOD25_drop | Brown-Out Detector Lower Than 2.5V Status |
| Setting BOD25_drop high means once the detected voltage is lower than target detected voltage setting (2.5V). | ||
| Software can write 1 to clear BOD25_drop. | ||
| [4] | BOD17_rise | Brown-Out Detector Higher Than 1.7V Status |
| Setting BOD17_rise high means once the detected voltage is higher than target detected voltage setting (1.7V). | ||
| Software can write 1 to clear BOD17_rise. | ||
| [5] | BOD20_rise | Brown-Out Detector Higher Than 2.0V Status |
| Setting BOD20_rise high means once the detected voltage is higher than target detected voltage setting (2.0V). | ||
| Software can write 1 to clear BOD20_rise. | ||
| [6] | BOD25_rise | Brown-Out Detector Higher Than 2.5V Status |
| Setting BOD25_rise high means once the detected voltage is higher than target detected voltage setting (2.5V). | ||
| Software can write 1 to clear BOD25_rise. |
Definition at line 2806 of file Nano100Series.h.
| __IO uint32_t USBD_EP_T::BUFSEG |
| Bits | Field | Descriptions |
|---|---|---|
| [8:3] | BUFSEG | It Is Used To Define The Offset Address For Each Endpoint With The USB SRAM Starting Address Its physical address is USB_SRAM address + {BUFSEG[5:0], 000}; where the USB_SRAM = USB_BASE + 0x100h. |
| Refer to the section <IP_ADDRESS> for the endpoint SRAM structure and its description. |
Definition at line 10853 of file Nano100Series.h.
| __IO uint32_t USBD_T::BUFSEG |
| Bits | Field | Descriptions |
|---|---|---|
| [8:3] | BUFSEG | This Register Is Used For Setup Token Only |
| It is used to define the offset address for the Setup Token with the USB SRAM starting address. | ||
| Its physical address is USB_SRAM address + {BUFSEG[5:0], 000} where the USB_SRAM = USB_BASE + 0x100h. |
Definition at line 11107 of file Nano100Series.h.
| __I uint32_t USBD_T::BUSSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | USBRST | USB Reset Status |
| 1 = Bus reset when SE0 (single-ended 0) more than 2.5uS. It is read only. | ||
| [1] | SUSPEND | Suspend Status |
| 1 = Bus idle more than 3 ms, either cable is plugged off or host is sleeping. It is read only. | ||
| [2] | RESUME | Resume Status |
| 1 = Resume from suspend. It is read only. | ||
| [3] | TIMEOUT | Time-Out Flag |
| 1 = Bus no any response more than 18 bits time. It is read only. | ||
| [4] | FLDET | Device Floating Detection |
| 0 = The controller didn't attach into the USB. | ||
| 1 = When the controller is attached into the USB, this bit will be set as "1". |
Definition at line 10971 of file Nano100Series.h.
| __IO uint32_t ADC_T::CALCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CALEN | Calibration Function Enable |
| Enable this bit to turn on the calibration function block. | ||
| 0 = Disable | ||
| 1 = Enabled. | ||
| [1] | CALSTART | Calibration Functional Block Start |
| 0 = Stops calibration functional block. | ||
| 1 = Starts calibration functional block. | ||
| Note: This bit is set by SW and clear by HW; don't write 1 to this bit while CALEN = 0. | ||
| [2] | CALDONE | Calibrate Functional Block Complete |
| 0 = Not yet. | ||
| 1 = Selected functional block complete. | ||
| [3] | CALSEL | Select Calibration Functional Block |
| 0 = Load calibration functional block. | ||
| 1 = Calibration functional block. |
Definition at line 499 of file Nano100Series.h.
| __IO uint32_t ADC_T::CALWORD |
| Bits | Field | Descriptions |
|---|---|---|
| [6:0] | CALWORD | Calibration Word Register |
| Write to this register with the previous calibration word before load calibration action | ||
| Read this register after calibration done | ||
| Note: The calibration block contains two parts "CALIBRATION" and "LOAD CALIBRATION"; if the calibration block is config as "CALIBRATION"; then this register represent the result of calibration when calibration is completed; if config as "LOAD CALIBRATION" ; config this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC;while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. |
Definition at line 513 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INV0 | Channel 0 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [1] | CAPCH0EN | Capture Channel 0 Transition Enable/Disable |
| 0 = Capture function on channel 0 Disabled. | ||
| 1 = Capture function on channel 0 Enabled. | ||
| When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL0 and PWM_CFL0, and disable Channel 0 Interrupt. | ||
| [2] | CAPCH0PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [3] | CH0PDMAEN | Channel 0 PDMA Enable |
| 0 = Channel 0 PDMA function Disabled. | ||
| 1 = Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory. | ||
| [5:4] | PDMACAPMOD0 | Select CRL0 Or CFL0 For PDMA Transfer |
| 00 = Reserved. | ||
| 01 = CRL0. | ||
| 10 = CFL0. | ||
| 11 = Both CRL0 and CFL0. | ||
| [6] | CAPRELOADREN0 | Reload CNR0 When CH0 Capture Rising Event Comes |
| 0 = Rising capture reload for CH0 Disabled. | ||
| 1 = Rising capture reload for CH0 Enabled. | ||
| [7] | CAPRELOADFEN0 | Reload CNR0 When CH0 Capture Falling Event Comes |
| 0 = Falling capture reload for CH0 Disabled. | ||
| 1 = Falling capture reload for CH0 Enabled. | ||
| [8] | INV1 | Channel 1 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [9] | CAPCH1EN | Capture Channel 1 Transition Enable/Disable |
| 0 = Capture function on channel 1 Disabled. | ||
| 1 = Capture function on channel 1 Enabled. | ||
| When Enabled, Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL1 and PWM_CFL1, and disable Channel 1 Interrupt. | ||
| [10] | CAPCH1PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [12] | CH0RFORDER | Channel 0 capture order control |
| Set this bit to determine whether the PWM_CRL0 or PWM_CFL0 is the first captured data transferred to memory through PDMA when PDMACAPMOD0 =2'b11. | ||
| 0 = PWM_CFL0 is the first captured data to memory. | ||
| 1 = PWM_CRL0 is the first captured data to memory. | ||
| [13] | CH01CASK | Cascade channel 0 and channel 1 PWM timer for capturing usage |
| [14] | CAPRELOADREN1 | Reload CNR1 When CH1 Capture Rising Event Comes |
| 0 = Rising capture reload for CH1 Disabled. | ||
| 1 = Rising capture reload for CH1 Enabled. | ||
| [15] | CAPRELOADFEN1 | Reload CNR1 When CH1 Capture Falling Event Coming |
| 0 = Capture falling reload for CH1 Disabled. | ||
| 1 = Capture falling reload for CH1 Enabled. | ||
| [16] | INV2 | Channel 2 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [17] | CAPCH2EN | Capture Channel 2 Transition Enable/Disable |
| 0 = Capture function on channel 2 Disabled. | ||
| 1 = Capture function on channel 2 Enabled. | ||
| When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL2 and PWM_CFL2, and disable Channel 2 Interrupt. | ||
| [18] | CAPCH2PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [19] | CH2PDMAEN | Channel 2 PDMA Enable |
| 0 = Channel 2 PDMA function Disabled. | ||
| 1 = Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory. | ||
| [21:20] | PDMACAPMOD2 | Select CRL2 Or CFL2 For PDMA Transfer |
| 00 = Reserved. | ||
| 01 = CRL2. | ||
| 10 = CFL2. | ||
| 11 = Both CRL2 and CFL2. | ||
| [22] | CAPRELOADREN2 | Reload CNR2 When CH2 Capture Rising Event Coming |
| 0 = Rising capture reload for CH2 Disabled. | ||
| 1 = Rising capture reload for CH2 Enabled. | ||
| [23] | CAPRELOADFEN2 | Reload CNR2 When CH2 Capture Failing Event Coming |
| 0 = Failing capture reload for CH2 Disabled. | ||
| 1 = Failing capture reload for CH2 Enabled. | ||
| [24] | INV3 | Channel 3 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [25] | CAPCH3EN | Capture Channel 3 Transition Enable/Disable |
| 0 = Capture function on channel 3 Disabled. | ||
| 1 = Capture function on channel 3 Enabled. | ||
| When Enabled, Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL3 and PWM_CFL3, and disable Channel 3 Interrupt. | ||
| [26] | CAPCH3PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [28] | CH2RFORDER | Channel 0 capture order control |
| Set this bit to determine whether the PWM_CRL2 or PWM_CFL2 is the first captured data transferred to memory through PDMA when PDMACAPMOD2 = 2'b11. | ||
| 0 = PWM_CFL2 is the first captured data to memory. | ||
| 1 = PWM_CRL2 is the first captured data to memory. | ||
| [29] | CH23CASK | Cascade channel 2 and channel 3 PWM counter for capturing usage |
| [30] | CAPRELOADREN3 | Reload CNR3 When CH3 Rising Capture Event Comes |
| 0 = Rising capture reload for CH3 Disabled. | ||
| 1 = Rising capture reload for CH3 Enabled. | ||
| [31] | CAPRELOADFEN3 | Reload CNR3 When CH3 Falling Capture Event Comes |
| 0 = Falling capture reload for CH3 Disabled. | ||
| 1 = Falling capture reload for CH3 Enabled. |
Definition at line 7085 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRL_IE0 | Channel 0 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt. | ||
| [1] | CFL_IE0 | Channel 0 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt. | ||
| [8] | CRL_IE1 | Channel 1 Rising Latch Interrupt Enable |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt. | ||
| [9] | CFL_IE1 | Channel 1 Falling Latch Interrupt Enable |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt. | ||
| [16] | CRL_IE2 | Channel 2 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt. | ||
| [17] | CFL_IE2 | Channel 2 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt. | ||
| [24] | CRL_IE3 | Channel 3 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt. | ||
| [25] | CFL_IE3 | Channel 3 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt. |
Definition at line 7127 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPIF0 | Capture0 Interrupt Indication Flag |
| If channel 0 rising latch interrupt is enabled (CRL_IE0 =1), a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFL_IE0 =1). | ||
| This flag is cleared by software with a write 1 on it. | ||
| [1] | CRLI0 | PWM_CRL0 Latched Indicator Bit |
| When input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [2] | CFLRI0 | PWM_CFL0 Latched Indicator Bit |
| When input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [3] | CAPOVR0 | Capture Rising Flag Over Run For Channel 0 |
| This flag indicate CRL0 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clears CRLI0 bit 1 of PWM_CAPINTSTS. | ||
| [4] | CAPOVF0 | Capture Falling Flag Over Run For Channel 0 |
| This flag indicate CFL0 update faster than software read it when it is set | ||
| This bit will be cleared automatically when user clear CFLI0 bit 2 of PWM_CAPINTSTS | ||
| [8] | CAPIF1 | Capture1 Interrupt Indication Flag |
| If channel 1 rising latch interrupt is enabled (CRL_IE1 =1), a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFL_IE1 =1). | ||
| This flag is cleared by software with a write 1 on it. | ||
| [9] | CRLI1 | PWM_CRL1 Latched Indicator Bit |
| When input channel 1 has a rising transition, PWM_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [10] | CFLI1 | PWM_CFL1 Latched Indicator Bit |
| When input channel 1 has a falling transition, PWM_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [11] | CAPOVR1 | Capture Rising Flag Over Run For Channel 1 |
| This flag indicate CRL1 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS | ||
| [12] | CAPOVF1 | Capture Falling Flag Over Run For Channel 1 |
| This flag indicate CFL1 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS | ||
| [16] | CAPIF2 | Capture2 Interrupt Indication Flag |
| If channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt is enabled (CFL_IE2=1). | ||
| This flag is cleared by software with a write 1 on it. | ||
| [17] | CRLI2 | PWM_CRL2 Latched Indicator Bit |
| When input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [18] | CFLI2 | PWM_CFL2 Latched Indicator Bit |
| When input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [19] | CAPOVR2 | Capture Rising Flag Over Run For Channel 2 |
| This flag indicate CRL2 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS | ||
| [20] | CAPOVF2 | Capture Falling Flag Over Run For Channel 2 |
| This flag indicate CFL2 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS | ||
| [24] | CAPIF3 | Capture3 Interrupt Indication Flag |
| If channel 3 rising latch interrupt is enabled (CRL_IE3 =1), a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt is enabled (CFL_IE3=1). | ||
| This flag is cleared by software with a write 1 on it. | ||
| [25] | CRLI3 | PWM_CRL3 Latched Indicator Bit |
| When input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [26] | CFLI3 | PWM_CFL3 Latched Indicator Bit |
| When input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [27] | CAPOVR3 | Capture Rising Flag Over Run For Channel 3 |
| This flag indicate CRL3update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS | ||
| [28] | CAPOVF3 | Capture Falling Flag Over Run For Channel 3 |
| This flag indicate CFL3 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS |
Definition at line 7189 of file Nano100Series.h.
| __IO uint32_t RTC_T::CAR |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | 1DAY | 1 Day Calendar Digit of Alarm Setting (0~9) |
| [5:4] | 10DAY | 10 Day Calendar Digit of Alarm Setting (0~3) |
| [11:8] | 1MON | 1 Month Calendar Digit of Alarm Setting (0~9) |
| [12] | 10MON | 10 Month Calendar Digit of Alarm Setting (0~1) |
| [19:16] | 1YEAR | 1 Year Calendar Digit of Alarm Setting (0~9) |
| [23:20] | 10YEAR | 10 Year Calendar Digit of Alarm Setting (0~9) |
Definition at line 7934 of file Nano100Series.h.
| __I uint32_t PDMA_T::CBCR |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | PDMA_CBCR | PDMA Current Byte Count Register (Read Only) |
| This field indicates the current remained byte count of PDMA. | ||
| Note: These fields will be changed when PDMA finish data transfer (data transfer to destination address), |
Definition at line 6039 of file Nano100Series.h.
| __I uint32_t VDMA_T::CBCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | VDMA_CBCR | VDMA Current Byte Count Register (Read Only) |
| This field indicates the current remained byte count of VDMA. |
Definition at line 6223 of file Nano100Series.h.
| __I uint32_t PDMA_T::CDAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDMA_CDAR | PDMA Current Destination Address Register (Read Only) |
| This field indicates the destination address where the PDMA transfer is just occurring. |
Definition at line 6026 of file Nano100Series.h.
| __I uint32_t VDMA_T::CDAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | VDMA_CDAR | VDMA Current Destination Address Register (Read Only) |
| This field indicates the destination address where the VDMA transfer is just occurring. |
Definition at line 6211 of file Nano100Series.h.
| __IO uint32_t USBD_EP_T::CFG |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | EP_NUM | Endpoint Number |
| These bits are used to define the endpoint number of the current endpoint | ||
| [4] | ISOCH | Isochronous Endpoint |
| This bit is used to set the endpoint as Isochronous endpoint, no handshake. | ||
| [6:5] | EPMODE | Endpoint Mode |
| 00 = Endpoint is disabled. | ||
| 01 = Out endpoint. | ||
| 10 = IN endpoint. | ||
| 11 = Undefined. | ||
| [7] | DSQ_SYNC | Data Sequence Synchronization |
| 0 = DATA0 PID. | ||
| 1 = DATA1 PID. | ||
| It is used to specify the DATA0 or DATA1 PID in the current transaction. | ||
| It will toggle automatically in IN token after host response ACK. | ||
| In the other tokens, the user shall take care of it to confirm the right PID in its transaction. | ||
| [8] | CSTALL | Clear STALL Response |
| 0 = Disable the device to clear the STALL handshake in setup stage. | ||
| 1 = Clear the device to response STALL handshake in setup stage. | ||
| [9] | SSTALL | Set STALL Response |
| 0 = Disable the device to response STALL. | ||
| 1 = Set the device to respond STALL automatically. | ||
| [15] | CLRRDY | Clear Ready |
| When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. | ||
| If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. | ||
| For IN token, write '1' to clear the IN token had ready to transmit the data to USB. | ||
| For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. | ||
| This bit is write 1 only and is always 0 when it is read back. |
Definition at line 10910 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 7217 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 7245 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 7273 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2, the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 7301 of file Nano100Series.h.
| __I uint32_t DMA_CRC_T::CHECKSUM |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CRC_CHECKSUM | CRC Checksum Register |
| This field indicates the CRC checksum |
Definition at line 5754 of file Nano100Series.h.
| __IO uint32_t ADC_T::CHEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHEN0 | Analog Input Channel 0 Enable (Convert Input Voltage From PA.0 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| If more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored. | ||
| [1] | CHEN1 | Analog Input Channel 1 Enable(Convert Input Voltage From PA.1 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | CHEN2 | Analog Input Channel 2 Enable (Convert Input Voltage From PA.2 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | CHEN3 | Analog Input Channel 3 Enable(Convert Input Voltage From PA.3 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | CHEN4 | Analog Input Channel 4 Enable (Convert Input Voltage From PA.4 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | CHEN5 | Analog Input Channel 5 Enable (Convert Input Voltage From PA.5 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6] | CHEN6 | Analog Input Channel 6 Enable (Convert Input Voltage From PA.6 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [7] | CHEN7 | Analog Input Channel 7 Enable (Convert Input Voltage From PA.7 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [8] | CHEN8 | Analog Input Channel 8 Enable For DAC0 (Convert Input Voltage From PD.0 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | CHEN9 | Analog Input Channel 9 Enable For DAC1 (Convert Input Voltage From PD.1 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [10] | CHEN10 | Analog Input Channel 10 Enable (Convert Input Voltage From PD.2 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [11] | CHEN11 | Analog Input Channel 11 Enable(Convert Input Voltage From PD.3 ) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [12] | CHEN12 | Analog Input Channel 12 Enable (Convert DAC0 Output Voltage) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [13] | CHEN13 | Analog Input Channel 13 Enable (Convert DAC1 Output Voltage) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [14] | CHEN14 | Analog Input Channel 14 Enable (Convert VTEMP) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [15] | CHEN15 | Analog Input Channel 15 Enable (Convert Int_VREF) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [16] | CHEN16 | Analog Input Channel 16 Enable (Convert AVDD) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [17] | CHEN17 | Analog Input Channel 17 Enable (Convert AVSS) |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 332 of file Nano100Series.h.
| __IO uint32_t I2S_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | MCLK_DIV | Master Clock Divider |
| If the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip. | ||
| If MCLK_DIV is set to "0", MCLK is the same as external clock input. | ||
| For example, sampling rate is 48 kHz and the external crystal clock is 12.288 MHz, set MCLK_DIV=0. | ||
| MCLK = I2SCLK/(2x(MCLK_DIV)). | ||
| [15:8] | BCLK_DIV | Bit Clock Divider |
| If I2S is operated in Master mode, bit clock is provided by this chip. | ||
| Software can program these bits to generate sampling rate clock frequency. | ||
| BCLK = I2SCLK /(2x(BCLK_DIV + 1)). |
Definition at line 4643 of file Nano100Series.h.
| __IO uint32_t SPI_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DIVIDER1 | Clock Divider 1 Register |
| The value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK. | ||
| The desired frequency is obtained according to the following equation: | ||
| Where | ||
| is the SPI engine clock source. It is defined in the CLK_SEL1. | ||
| [23:16] | DIVIDER2 | Clock Divider 2 Register |
| The value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK. | ||
| The desired frequency is obtained according to the following equation: |
Definition at line 9364 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKDIV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLK_N | HCLK Clock Divide Number From HCLK Clock Source |
| The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1). | ||
| [7:4] | USB_N | USB Clock Divide Number From PLL Clock |
| The USB clock frequency = (PLL frequency ) / (USB_N + 1). | ||
| [11:8] | UART_N | UART Clock Divide Number From UART Clock Source |
| The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1). | ||
| [15:12] | I2S_N | I2S Clock Divide Number From I2S Clock Source |
| The I2S clock frequency = (I2S Clock Source frequency ) / (I2S_N + 1). | ||
| [23:16] | ADC_N | ADC Clock Divide Number From ADC Clock Source |
| The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1). | ||
| [31:28] | SC0_N | SC 0 Clock Divide Number From SC 0 Clock Source |
| The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1). |
Definition at line 1091 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKDIV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | SC1_N | SC 1 Clock Divide Number From SC 1 Clock Source |
| The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1). | ||
| [7:4] | SC2_N | SC 2 Clock Divide Number From SC2 Clock Source |
| The SC 2 clock frequency = (SC 2 Clock Source frequency ) / (SC2_N + 1). |
Definition at line 1105 of file Nano100Series.h.
| __IO uint32_t PWM_T::CLKSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | CLKSEL0 | Timer 0 Clock Source Selection |
| Select clock input for timer 0. | ||
| (Table is the same as CLKSEL3) | ||
| [6:4] | CLKSEL1 | Timer 1 Clock Source Selection |
| Select clock input for timer 1. | ||
| (Table is the same as CLKSEL3) | ||
| [10:8] | CLKSEL2 | Timer 2Clock Source Selection |
| Select clock input for timer 2. | ||
| (Table is the same as CLKSEL3) | ||
| [14:12] | CLKSEL3 | Timer 3 Clock Source Selection |
| Select clock input for timer 3. | ||
| 000 = Input Clock Divided by 2. | ||
| 001 = Input Clock Divided by 4. | ||
| 010 = Input Clock Divided by 8. | ||
| 011 = Input Clock Divided by 16. | ||
| 100 = Input Clock Divided by 1. |
Definition at line 6633 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLK_S | HCLK Clock Source Selection |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Note: | ||
| Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on | ||
| The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset. | ||
| Therefore the default value is either 000b or 111b. | ||
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = PLL Clock | ||
| 011 = LIRC | ||
| 111 = HIRC | ||
| Others = Reserved |
Definition at line 959 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | UART_S | UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection) |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = PLL Clock | ||
| 11 = HIRC | ||
| [3:2] | ADC_S | ADC Clock Source Selection |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = PLL Clock | ||
| 11 = HIRC | ||
| [5:4] | PWM0_CH01_S | PWM0 Channel 0 And Channel 1 Clock Source Selection |
| PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [7:6] | PWM0_CH23_S | PWM0 Channel 2 And Channel 3 Clock Source Selection |
| PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [10:8] | TMR0_S | Timer0 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [14:12] | TMR1_S | Timer1 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [18] | LCD_S | LCD Clock Source Selection |
| 0 = Clock Source from LXT. | ||
| 1 = Reserved. |
Definition at line 1008 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:2] | FRQDIV_S | Clock Divider Clock Source Selection |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [5:4] | PWM1_CH01_S | PWM1 Channel 0 And Channel 1 Clock Source Selection |
| PWM1 channel 0 and channel 1 use the same Engine clock source, both of them with the same pre-scale | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [7:6] | PWM1_CH23_S | PWM1 Channel 2 And Channel 2 Clock Source Selection |
| PWM1 channel 2 and channel 3 use the same Engine clock source, both of them with the same pre-scale | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [10:8] | TMR2_S | Timer2 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [14:12] | TMR3_S | Timer3 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [17:16] | I2S_S | I2S Clock Source Selection |
| 00 = HXT | ||
| 01 = PLL Clock | ||
| 10 = HIRC | ||
| 11 = HIRC | ||
| [19:18] | SC_S | SC Clock Source Selection |
| 00 = HXT | ||
| 01 = PLL Clock | ||
| 10 = HIRC | ||
| 11 = HIRC | ||
| Note: SC0,SC1 and SC2 use the same Clock Source selection but they have different clock divider number. | ||
| [20] | SPI0_S | SPI0 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. | ||
| [21] | SPI1_S | SPI1 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. | ||
| [22] | SPI2_S | SPI2 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. |
Definition at line 1069 of file Nano100Series.h.
| __I uint32_t CLK_T::CLKSTATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXT_STB | HXT Clock Source Stable Flag |
| 0 = HXT clock is not stable or not enable. | ||
| 1 = HXT clock is stable. | ||
| [1] | LXT_STB | LXT Clock Source Stable Flag |
| 0 = LXT clock is not stable or not enable. | ||
| 1 = LXT clock is stable. | ||
| [2] | PLL_STB | PLL Clock Source Stable Flag |
| 0 = PLL clock is not stable or not enable. | ||
| 1 = PLL clock is stable. | ||
| [3] | LIRC_STB | LIRC Clock Source Stable Flag |
| 0 = LIRC clock is not stable or not enable. | ||
| 1 = LIRC clock is stable. | ||
| [4] | HIRC_STB | HIRC Clock Source Stable Flag |
| 0 = HIRC clock is not stable or not enable. | ||
| 1 = HIRC clock is stable. | ||
| [7] | CLK_SW_FAIL | Clock Switch Fail Flag |
| 0 = Clock switch success. | ||
| 1 = Clock switch fail. | ||
| This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear |
Definition at line 937 of file Nano100Series.h.
| __IO uint32_t RTC_T::CLR |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | 1DAY | 1 Day Calendar Digit (0~9) |
| [5:4] | 10DAY | 10 Day Calendar Digit (0~3) |
| [11:8] | 1MON | 1 Month Calendar Digit (0~9) |
| [12] | 10MON | 10 Month Calendar Digit (0~1) |
| [19:16] | 1YEAR | 1 Year Calendar Digit (0~9) |
| [23:20] | 10YEAR | 10 Year Calendar Digit (0~9) |
Definition at line 7870 of file Nano100Series.h.
| __IO uint32_t TIMER_T::CMPR |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TMR_CMP | Timer Compared Value |
| TMR_CMP is a 24-bit compared register. | ||
| When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled. | ||
| The TMR_CMP value defines the timer counting cycle time. | ||
| Time-out period = (Period of timer clock input) * (8-bit PRESCALE_CNT + 1) * (24-bit TMR_CMP). | ||
| Note1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state. | ||
| Note2: No matter TMR_CTL [TMR_EN] is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. |
Definition at line 9915 of file Nano100Series.h.
| __IO uint32_t ADC_T::CMPR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CMPEN | Compare Enable |
| 0 = Compare Disabled. | ||
| 1 = Compare Enabled. | ||
| Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register. | ||
| When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit | ||
| [1] | CMPIE | Compare Interrupt Enable |
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one. | ||
| Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. | ||
| [7:3] | CMPCH | Compare Channel Selection |
| This field selects the channel whose conversion result is selected to be compared. | ||
| [11:8] | CMPMATCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. | ||
| When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. | ||
| [27:16] | CMPD | Comparison Data |
| The 12 bits data is used to compare with conversion result of specified channel. | ||
| Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
Definition at line 363 of file Nano100Series.h.
| __IO uint32_t ADC_T::CMPR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CMPEN | Compare Enable |
| 0 = Compare Disabled. | ||
| 1 = Compare Enabled. | ||
| Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register. | ||
| When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit | ||
| [1] | CMPIE | Compare Interrupt Enable |
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one. | ||
| Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. | ||
| [7:3] | CMPCH | Compare Channel Selection |
| This field selects the channel whose conversion result is selected to be compared. | ||
| [11:8] | CMPMATCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. | ||
| When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. | ||
| [27:16] | CMPD | Comparison Data |
| The 12 bits data is used to compare with conversion result of specified channel. | ||
| Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
Definition at line 394 of file Nano100Series.h.
| __IO uint32_t DAC_T::COMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | WAITDACCONV | Wait DAC Conversion Complete |
| The DAC needs at least 2 us to settle down every time when each data deliver to DAC, which means user cannot update each DACx_data register faster than 2 us; otherwise data will lost. | ||
| Setting this register can adjust the time interval in PCLK unit between each DACx_data into DAC in order to meet the 2 us requirement. | ||
| [8] | DAC01GRP | Group DAC0 And DAC1 |
| 0 = Not grouped. | ||
| 1 = Grouped. | ||
| [10:9] | REFSEL | Reference Voltage Selection |
| 00 = AVDD | ||
| 01 = Internal reference voltage | ||
| 10 = External reference voltage | ||
| 11= Reserved |
Definition at line 1626 of file Nano100Series.h.
| __IO uint32_t I2C_T::CON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | IPEN | I2C Function Enable |
| When this bit is set to 1, the I2C serial function is enabled. | ||
| 0 = I2C function Disabled. | ||
| 1 = I2C function Enabled. | ||
| [1] | ACK | Assert Acknowledge Control Bit |
| 0 =: When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse. | ||
| 1 = When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when. | ||
| a. A slave is acknowledging the address sent from master | ||
| b. The receiver devices are acknowledging the data sent by transmitter. | ||
| [2] | STOP | I2C STOP Control Bit |
| In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically. | ||
| In Slave mode, set this bit to 1 to reset the controller to the defined "not addressed" Slave mode. | ||
| This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. | ||
| 0 = Will be cleared by hardware automatically if a STOP condition is detected. | ||
| 1 = Sends a STOP condition to bus in Master mode or reset the controller to "not addressed" in Slave mode. | ||
| [3] | START | I2C START Command |
| Setting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated. | ||
| 0 = After START or repeat START is active. | ||
| 1 = Sends a START or repeat START condition to bus. | ||
| [4] | I2C_STS | I2C Status |
| When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if the INTEN bit is set, the I2C interrupt is requested. | ||
| It must be cleared by software by writing one to this bit and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled. | ||
| 0 = I2C's Status disabled and the I2C protocol function will go ahead. | ||
| 1 = I2C's Status active. | ||
| [7] | INTEN | Interrupt Enable |
| 0 = I2C interrupt Disabled. | ||
| 1 = I2C interrupt Enabled. |
Definition at line 4253 of file Nano100Series.h.
| __IO uint32_t ADC_T::CR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADEN | A/D Converter Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Before starting A/D conversion, this bit should be set to 1. | ||
| Clear it to 0 to disable A/D converter analog circuit power consumption. | ||
| [1] | ADIE | A/D Interrupt Enable |
| 0 = A/D interrupt function Disabled. | ||
| 1 = A/D interrupt function Enabled. | ||
| A/D conversion end interrupt request is generated if ADIE bit is set to 1. | ||
| [3:2] | ADMD | A/D Converter Operation Mode |
| 00 = Single conversion | ||
| 01 = Reserved | ||
| 10 = Single-cycle scan | ||
| 11 = Continuous scan | ||
| [5:4] | TRGS | Hardware Trigger Source |
| This field must keep 00 | ||
| Software should disable TRGE and ADST before change TRGS. | ||
| In hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time. | ||
| [7:6] | TRGCOND | External Trigger Condition |
| These two bits decide external pin STADC trigger event is level or edge. | ||
| The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. | ||
| 00 = Low level | ||
| 01 = High level | ||
| 10 = Falling edge | ||
| 11 = Rising edge | ||
| [8] | TRGE | External Trigger Enable |
| Enable or disable triggering of A/D conversion by external STADC pin. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | PTEN | PDMA Transfer Enable |
| 0 = PDMA data transfer Disabled. | ||
| 1 = PDMA data transfer in ADC_RESULT 0~17 Enabled. | ||
| When A/D conversion is completed, the converted data is loaded into ADC_RESULT 0~10, software can enable this bit to generate a PDMA data transfer request. | ||
| When PTEN=1, software must set ADIE=0 to disable interrupt. | ||
| PDMA can access ADC_RESULT 0-17 registers by block or single transfer mode. | ||
| [10] | DIFF | Differential Mode Selection |
| 0 = ADC is operated in single-ended mode. | ||
| 1 = ADC is operated in differential mode. | ||
| The A/D analog input ADC_CH0/ADC_CH1 consists of a differential pair. | ||
| So as ADC_CH2/ADC_CH3, ADC_CH4/ADC_CH5, ADC_CH6/ADC_CH7, ADC_CH8/ADC_CH9 and ADC_CH10/ADC_CH11. | ||
| The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus). | ||
| Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus is the analog input; Vminus is the inverted analog input. | ||
| In differential input mode, only the even number of the two corresponding channels needs to be enabled in CHEN (ADCHER[11:0]). | ||
| The conversion result will be placed to the corresponding data register of the enabled channel. | ||
| Note: Calibration should calibrated each time when switching between single-ended and differential mode | ||
| [11] | ADST | A/D Conversion Start |
| 0 = Conversion stopped and A/D converter enter idle state. | ||
| 1 = Conversion starts. | ||
| ADST bit can be set to 1 from two sources: software write and external pin STADC. | ||
| ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. | ||
| In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset. | ||
| Note: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again. | ||
| [13:12] | TMSEL | Select A/D Enable Time-Out Source |
| 00 = TMR0 | ||
| 01 = TMR1 | ||
| 10 = TMR2 | ||
| 11 = TMR3 | ||
| [15] | TMTRGMOD | Timer Event Trigger ADC Conversion |
| 0 = This function Disabled. | ||
| 1 = ADC Enabled by TIMER OUT event. Setting TMSEL to select timer event from timer0~3 | ||
| [17:16] | REFSEL | Reference Voltage Source Selection |
| 00 = Reserved | ||
| 01 = Select Int_VREF as reference voltage | ||
| 10 = Select VREF as reference voltage | ||
| 11 = Reserved | ||
| [19:18] | RESSEL | Resolution Selection |
| 00 = 6 bits | ||
| 01 = 8 bits | ||
| 10 = 10 bits | ||
| 11 = 12 bits | ||
| [31:24] | TMPDMACNT | PDMA Count |
| When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting | ||
| Note: The total amount of PDMA transferring data should be set in PDMA byte count register. | ||
| When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred. |
Definition at line 267 of file Nano100Series.h.
| __IO uint32_t WWDT_T::CR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTEN | Window Watchdog Enable |
| Set this bit to enable Window Watchdog timer. | ||
| 0 = Window Watchdog timer function Disabled. | ||
| 1 = Window Watchdog timer function Enabled. | ||
| [11:8] | PERIODSEL | WWDT Pre-Scale Period Select |
| These three bits select the pre-scale for the WWDT counter period. | ||
| Please refer to Table 5-17 | ||
| [21:16] | WINCMP | WWDT Window Compare Register |
| Set this register to adjust the valid reload window. | ||
| Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. | ||
| If SW writes WWDTRLD when WWDT counter value larger than WWCMP, WWDT will generate RESET signal. | ||
| [31] | DBGEN | WWDT Debug Enable |
| 0 = WWDT stopped count if system is in Debug mode. | ||
| 1 = WWDT still counted even system is in Debug mode. |
Definition at line 11508 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 7203 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 7231 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 7259 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32-Bit Capture Data When Cascade Enabled |
| When cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 7287 of file Nano100Series.h.
| __I uint32_t PDMA_T::CSAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDMA_CSAR | PDMA Current Source Address Register (Read Only) |
| This field indicates the source address where the PDMA transfer is just occurring. |
Definition at line 6014 of file Nano100Series.h.
| __I uint32_t VDMA_T::CSAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | VDMA_CSAR | VDMA Current Source Address Register (Read Only) |
| This field indicates the source address where the VDMA transfer is just occurring. |
Definition at line 6199 of file Nano100Series.h.
| __IO uint32_t PDMA_T::CSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PDMACEN | PDMA Channel Enable |
| Setting this bit to "1" enables PDMA's operation. | ||
| If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. | ||
| Note: SW_RST will clear this bit. | ||
| [1] | SW_RST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal state machine and pointers. | ||
| The contents of control register will not be cleared. | ||
| This bit will be auto cleared after few clock cycles. | ||
| [3:2] | MODE_SEL | PDMA Mode Select |
| 00 = Memory to Memory mode (Memory-to-Memory). | ||
| 01 = IP to Memory mode (APB-to-Memory) | ||
| 10 = Memory to IP mode (Memory-to-APB). | ||
| 11 = Reserved. | ||
| [5:4] | SAD_SEL | Transfer Source Address Direction Selection |
| 00 = Transfer Source address is incremented successively. | ||
| 01 = Reserved. | ||
| 10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations). | ||
| 11 = Transfer Source address is wrap around (When the PDMA_CBCR is equal to zero, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. | ||
| PDMA will start another transfer without software trigger until PDMA_EN disabled. | ||
| When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address). | ||
| [7:6] | DAD_SEL | Transfer Destination Address Direction Selection |
| 00 = Transfer Destination address is incremented successively | ||
| 01 = Reserved. | ||
| 10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination) | ||
| 11 = Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to zero, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. | ||
| PDMA will start another transfer without software trigger until PDMA_EN disabled. | ||
| When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address). | ||
| [12] | TO_EN | Time-Out Enable |
| This bit will enable PDMA internal counter. While this counter counts to zero, the TO_IS will be set. | ||
| 0 = PDMA internal counter Disabled. | ||
| 1 = PDMA internal counter Enabled. | ||
| [20:19] | APB_TWS | Peripheral Transfer Width Selection |
| 00 = One word (32 bits) is transferred for every PDMA operation. | ||
| 01 = One byte (8 bits) is transferred for every PDMA operation. | ||
| 10 = One half-word (16 bits) is transferred for every PDMA operation. | ||
| 11 = Reserved. | ||
| Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). | ||
| [23] | TRIG_EN | TRIG_EN |
| 0 = No effect. | ||
| 1 = PDMA data read or write transfer Enabled. | ||
| Note1: When PDMA transfer completed, this bit will be cleared automatically. | ||
| Note2: If the bus error occurs, all PDMA transfer will be stopped. | ||
| Software must reset all PDMA channel, and then trig again. |
Definition at line 5961 of file Nano100Series.h.
| __IO uint32_t VDMA_T::CSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VDMACEN | VDMA Channel Enable |
| Setting this bit to "1" enables VDMA's operation. | ||
| If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state. | ||
| Note: SW_RST will clear this bit. | ||
| [1] | SW_RST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal state machine and pointers. | ||
| The contents of control register will not be cleared. | ||
| This bit will be auto cleared after few clock cycles. | ||
| [10] | STRIDE_EN | Stride Mode Enable |
| 0 = Stride transfer mode Disabled. | ||
| 1 = Stride transfer mode Enabled. | ||
| [11] | DIR_SEL | Transfer Source/Destination Address Direction Select |
| 0 = Transfer address is incremented successively. | ||
| 1 = Transfer address is decremented successively. | ||
| [23] | TRIG_EN | TRIG_EN |
| 0 = No effect. | ||
| 1 = VDMA data read or write transfer Enabled. | ||
| Note1: When VDMA transfer is completed, this bit will be cleared automatically. | ||
| Note2: If the bus error occurs, all VDMA transfer will be stopped. | ||
| Software must reset all VDMA channel, and then trig again. |
Definition at line 6148 of file Nano100Series.h.
| __IO uint32_t LCD_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EN | LCD Enable |
| 0 = LCD controller operation Disabled. | ||
| 1 = LCD controller operation Enabled. | ||
| [3:1] | MUX | Mux Select |
| 000 = Static. | ||
| 001 = 1/2 duty. | ||
| 010 = 1/3 duty. | ||
| 011 = 1/4 duty. | ||
| 100 = 1/5 duty. | ||
| 101 = 1/6 duty. | ||
| 110 = Reserved. | ||
| 111 = Reserved. | ||
| Note : User does not need to set PD_H_MFP bit field, but only to set the MUX bit field to switch LCD_SEG0 and LCD_SEG1 to LCD_COM4 and LCD_COM5 for Nano110 and Nano130 series. | ||
| [6:4] | FREQ | LCD Frequency Selection |
| 000 = LCDCLK Divided by 32. | ||
| 001 = LCDCLK Divided by 64. | ||
| 010 = LCDCLK Divided by 96. | ||
| 011 = LCDCLK Divided by 128. | ||
| 100 = LCDCLK Divided by 192. | ||
| 101 = LCDCLK Divided by 256. | ||
| 110 = LCDCLK Divided by 384. | ||
| 111 = LCDCLK Divided by 512. | ||
| [7] | BLINK | LCD Blinking Enable |
| 0 = Blinking Disabled. | ||
| 1 = Blinking Enabled. | ||
| [8] | PDDISP_EN | Power Down Display Enable |
| The LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting. | ||
| 0 = LCD display Disabled ( LCD is put out) at power down state. | ||
| 1 = LCD display Enabled (LCD keeps the display) at power down state. | ||
| [9] | PDINT_EN | Power Down Interrupt Enable |
| If the power down request is triggered from system management, LCD controller will execute the frame completely to avoid the DC component. | ||
| When the frame is executed completely, the LCD power down interrupt signal is generated to inform system management that LCD controller is ready to enter power down state, if PDINT_EN is set to 1. | ||
| Otherwise, if PDINT_EN is set to 0, the LCD power down interrupt signal is blocked and the interrupt is disabled to send to system management. | ||
| 0 = Power Down Interrupt Disabled. | ||
| 1 = Power Down Interrupt Enabled. |
Definition at line 5103 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRCCEN | CRC Channel Enable |
| Setting this bit to 1 enables CRC's operation. | ||
| When operating in CRC DMA mode (TRIG_EN = 1), if user clear this bit, the DMA operation will be continuous until all CRC DMA operation done, and the TRIG_EN bit will asserted until all CRC DMA operation done. | ||
| But in this case, the CRC_DMAISR [BLKD_IF] flag will inactive, user can read CRC result by reading CRC_CHECKSUM register when TRIG_EN = 0. | ||
| When operating in CRC DMA mode (TRIG_EN = 1), if user want to stop the transfer immediately, user can write 1 to CRC_RST bit to stop the transmission. | ||
| [1] | CRC_RST | CRC Engine Reset |
| 0 = Writing 0 to this bit has no effect. | ||
| 1 = Writing 1 to this bit will reset the internal CRC state machine and internal buffer. | ||
| The contents of control register will not be cleared. | ||
| This bit will be auto cleared after few clock cycles. | ||
| Note: When operating in CPU PIO mode, setting this bit will reload the initial seed value | ||
| [23] | TRIG_EN | Trigger Enable |
| 0 = No effect. | ||
| 1 = CRC DMA data read or write transfer Enabled. | ||
| Note1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register. | ||
| Note2: When CRC DMA transfer completed, this bit will be cleared automatically. | ||
| Note3: If the bus error occurs, all CRC DMA transfer will be stopped. | ||
| Software must reset all DMA channel, and then trigger again. | ||
| [24] | WDATA_RVS | Write Data Order Reverse |
| 0 = No bit order reverse for CRC write data in. | ||
| 1 = Bit order reverse for CRC write data in (per byre). | ||
| Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB | ||
| [25] | CHECKSUM_RVS | Checksum Reverse |
| 0 = No bit order reverse for CRC checksum. | ||
| 1 = Bit order reverse for CRC checksum. | ||
| Note: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB | ||
| [26] | WDATA_COM | Write Data Complement |
| 0 = No bit order reverse for CRC write data in. | ||
| 1 = 1's complement for CRC write data in. | ||
| [27] | CHECKSUM_COM | Checksum Complement |
| 0 = No bit order reverse for CRC checksum. | ||
| 1 = 1's complement for CRC checksum. | ||
| [29:28] | CPU_WDLEN | CPU Write Data Length |
| When operating in CPU PIO mode (CRCCEN= 1, TRIG_EN = 0), this field indicates the write data length. | ||
| 00 = The data length is 8-bit mode | ||
| 01 = The data length is 16-bit mode | ||
| 10 = The data length is 32-bit mode | ||
| 11 = Reserved | ||
| Note1: This field is only used for CPU PIO mode. | ||
| Note2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0], and if the data length is 16 bit mode, the valid data is CRC_WDATA [15:0]. | ||
| [31:30] | CRC_MODE | CRC Polynomial Mode |
| 00 = CRC-CCITT Polynomial Mode | ||
| 01 = CRC-8 Polynomial Mode | ||
| 10 = CRC-16 Polynomial Mode | ||
| 11 = CRC-32 Polynomial Mode |
Definition at line 5618 of file Nano100Series.h.
| __IO uint32_t PWM_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CH0EN | PWM-Timer 0 Enable/Disable Start Run |
| 0 = PWM-Timer 0 Running Stopped. | ||
| 1 = PWM-Timer 0 Start Run Enabled. | ||
| [2] | CH0INV | PWM-Timer 0 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [3] | CH0MOD | PWM-Timer 0 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared. | ||
| [4] | DZEN01 | Dead-Zone 0 Generator Enable/Disable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair. | ||
| [5] | DZEN23 | Dead-Zone 2 Generator Enable/Disable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair. | ||
| [8] | CH1EN | PWM-Timer 1 Enable/Disable Start Run |
| 0 = PWM-Timer 1 Running Stopped. | ||
| 1 = PWM-Timer 1 Start Run Enabled. | ||
| [10] | CH1INV | PWM-Timer 1 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [11] | CH1MOD | PWM-Timer 1 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared. | ||
| [16] | CH2EN | PWM-Timer 2 Enable/Disable Start Run |
| 0 = PWM-Timer 2 Running Stopped. | ||
| 1 = PWM-Timer 2 Start Run Enabled. | ||
| [18] | CH2INV | PWM-Timer 2 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [19] | CH2MOD | PWM-Timer 2 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared. | ||
| [24] | CH3EN | PWM-Timer 3 Enable/Disable Start Run |
| 0 = PWM-Timer 3 Running Stopped. | ||
| 1 = PWM-Timer 3 Start Run Enabled. | ||
| [26] | CH3INV | PWM-Timer 3 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [27] | CH3MOD | PWM-Timer 3 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared. |
Definition at line 6691 of file Nano100Series.h.
| __IO uint32_t SC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SC_CEN | SC Engine Enable |
| Set this bit to "1" to enable SC operation. | ||
| If this bit is cleared, SC will force all transition to IDLE state. | ||
| [1] | DIS_RX | RX Transition Disable |
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| [2] | DIS_TX | TX Transition Disable |
| 0 = Transceiver Enabled. | ||
| 1 = Transceiver Disabled. | ||
| [3] | AUTO_CON_EN | Auto Convention Enable |
| 0 = Auto-convention Disabled. | ||
| 1 = Auto-convention Enabled. | ||
| When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL will be set to 00 automatically, otherwise if the TS is inverse convention, CON_SEL will be set to 11. | ||
| If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F. | ||
| After hardware received first data and stored it at buffer, hardware will decided the convention and change the SC_CTL[CON_SEL] register automatically. | ||
| If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR(if SC_IER [ACON_ERR_IE = "1"] to CPU. | ||
| [5:4] | CON_SEL | Convention Selection |
| 00 = Direct convention. | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = Inverse convention. | ||
| Note: If AUTO_CON_EN is enabled, this field must be ignored. | ||
| [7:6] | RX_FTRI_LEV | RX Buffer Trigger Level |
| When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated). | ||
| 00 = INTR_RDA Trigger Level 1 byte. | ||
| 01 = INTR_RDA Trigger Level 2 bytes. | ||
| 10 = INTR_RDA Trigger Level 3 bytes. | ||
| 11 = Reserved. | ||
| [12:8] | BGT | Block Guard Time (BGT) |
| This field indicates the counter for block guard time. | ||
| According to ISO7816-3, in T=0 mode, software must fill 15 (real block guard time = 16) to this field and in T=1 mode software must fill 21 (real block guard time = 22) to it. | ||
| In TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data. | ||
| In RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. | ||
| If the incoming data timing less than BGT, an interrupt will be generated. | ||
| Note: The real block guard time is BGT + 1. | ||
| [14:13] | TMR_SEL | Timer Selection |
| 00 = Disable all internal timer function. | ||
| 01 = Enable internal 24 bit timer. | ||
| Software can configure it by setting SC_TMR0 [23:0]. | ||
| SC_TMR1 and SC_TMR2 will be ignored in this mode. | ||
| 10 = Enable internal 24 bit timer and 8 bit internal timer. | ||
| Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1 [7:0]. | ||
| SC_TMR2 will be ignored in this mode. | ||
| 11 = Enable internal 24 bit timer and two 8 bit timers. | ||
| Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]. | ||
| [15] | SLEN | Stop Bit Length |
| This field indicates the length of stop bit. | ||
| 0 = The stop bit length is 2 ETU. | ||
| 1 = The stop bit length is 1 ETU. | ||
| Note: The default stop bit length is 2. | ||
| [18:16] | RX_ERETRY | RX Error Retry Register |
| This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. | ||
| Note1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number. | ||
| Note2: This field can not be changed when RX_ERETRY_EN enabled. | ||
| The change flow is to disable RX_ETRTRY_EN first and then fill new retry value. | ||
| [19] | RX_ERETRY_EN | RX Error Retry Enable Register |
| This bit enables receiver retry function when parity error has occurred. | ||
| 0 = RX error retry function Disabled. | ||
| 1 = RX error retry function Enabled. | ||
| Note: User must fill RX_ERETRY value before enabling this bit. | ||
| [22:20] | TX_ERETRY | TX Error Retry Register |
| This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
| Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number. | ||
| Note2: This field can not be changed when TX_ERETRY_EN enabled. | ||
| The change flow is to disable TX_ETRTRY_EN first and then fill new retry value. | ||
| [23] | TX_ERETRY_EN | TX Error Retry Enable Register |
| This bit enables transmitter retry function when parity error has occurred. | ||
| 0 = TX error retry function Disabled. | ||
| 1 = TX error retry function Enabled. | ||
| Note: User must fill TX_ERETRY value before enabling this bit. | ||
| [25:24] | CD_DEB_SEL | Card Detect De-Bounce Select Register |
| This field indicates the card detect de-bounce selection. | ||
| This field indicates the card detect de-bounce selection. | ||
| 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. | ||
| 01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks. | ||
| 10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks. | ||
| 11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks. |
Definition at line 8388 of file Nano100Series.h.
| __IO uint32_t SPI_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GO_BUSY | SPI Transfer Control Bit And Busy Status |
| 0 = Writing this bit "0" will stop data transfer if SPI is transferring. | ||
| 1 = In Master mode, writing "1" to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master. | ||
| If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'. | ||
| As the transfer is finished, this bit will be cleared automatically. | ||
| Software can read this bit to check if the SPI is in busy status. | ||
| In FIFO mode, this bit will be controlled by hardware. | ||
| Software should not modify this bit. | ||
| In slave mode, this bit always returns 1 when software reads this register. | ||
| In master mode, this bit reflects the busy or idle status of SPI. | ||
| Note: | ||
| 1. When FIFO mode is disabled, all configurations should be set before writing "1" to the GO_BUSY bit in the SPI_CTL register. | ||
| 2. When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. | ||
| [1] | RX_NEG | Receive At Negative Edge |
| 0 = The received data is latched on the rising edge of SPI_SCLK. | ||
| 1 = The received data is latched on the falling edge of SPI_SCLK. | ||
| [2] | TX_NEG | Transmit At Negative Edge |
| 0 = The transmitted data output is changed on the rising edge of SPI_SCLK. | ||
| 1 = The transmitted data output is changed on the falling edge of SPI_SCLK. | ||
| [7:3] | TX_BIT_LEN | Transmit Bit Length |
| This field specifies how many bits can be transmitted / received in one transaction. | ||
| The minimum bit length is 8 bits and can be up to 32 bits. | ||
| TX_BIT_LEN Description | ||
| 01000 8 bits are transmitted in one transaction | ||
| 01001 9 bits are transmitted in one transaction | ||
| ---— -------— | ||
| 11111 31 bits are transmitted in one transaction | ||
| 00000 32 bits are transmitted in one transaction | ||
| [10] | LSB | Send LSB First |
| 0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BITLEN, is transmitted/received first. | ||
| 1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1). | ||
| [11] | CLKP | Clock Polarity |
| 0 = The default level of SCLK is low in idle state. | ||
| 1 = The default level of SCLK is high in idle state. | ||
| [15:12] | SP_CYCLE | Suspend Interval (Master Only) |
| These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. | ||
| The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = "0". | ||
| If CLKP = "1", the interval is from the rising clock edge to the falling clock edge. | ||
| The default value is 0x3. The desired suspend interval is obtained according to the following equation: | ||
| (SP_CYCLE[3:0) + 0.5) * period of SPICLK | ||
| Ex: | ||
| SP_CYCLE = 0x0 ... 0.5 SPICLK clock cycle. | ||
| SP_CYCLE = 0x1 ... 1.5 SPICLK clock cycle. | ||
| ...... | ||
| SP_CYCLE = 0xE ... 14.5 SPICLK clock cycle. | ||
| SP_CYCLE = 0xF ... 15.5 SPICLK clock cycle. | ||
| If the Variable Clock function is enabled, the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle | ||
| [17] | INTEN | Interrupt Enable |
| 0 = SPI Interrupt Disabled. | ||
| 1 = SPI Interrupt Enabled. | ||
| [18] | SLAVE | Slave Mode |
| 0 = SPI controller set as Master mode. | ||
| 1 = SPI controller set as Slave mode. | ||
| [19] | REORDER | Byte Reorder Function Enable |
| 0 = Disable byte reorder function | ||
| 1 = Enable byte reorder function and insert a byte suspend interval among each byte. | ||
| The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word). | ||
| The suspend interval is defined in SP_CYCLE. | ||
| Note: | ||
| 1. The byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits. | ||
| 2. In Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer. | ||
| 3. The byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled. | ||
| [21] | FIFOM | FIFO Mode Enable |
| 0 = Normal mode. | ||
| 1 = FIFO mode. | ||
| Note: | ||
| 1. Before enabling FIFO mode, the other related settings should be set in advance. | ||
| 2. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set "1" automatically after the data was written into the 8-depth FIFO. | ||
| The user can clear this FIFO bit after the transmit FIFO status is empty and the GO_BUSY back to 0. | ||
| [22] | TWOB | 2-Bit Transfer Mode Active |
| 0 = 2-bit transfer mode Disabled. | ||
| 1 = 2-bit transfer mode Enabled. | ||
| Note that when enabling TWOB, the serial transmitted 2-bits data are from SPI_TX1/0, and the received 2-bits data input are put into SPI_RX1/0. | ||
| [23] | VARCLK_EN | Variable Clock Enable |
| 0 = The serial clock output frequency is fixed and only decided by the value of DIVIDER1 | ||
| 1 = The serial clock output frequency is variable. | ||
| The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1, and DIVIDER2. | ||
| Note: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). | ||
| [28] | DUAL_IO_DIR | Dual IO Mode Direction |
| 0 = Date read in the Dual I/O Mode function. | ||
| 1 = Data write in the Dual I/O Mode function. | ||
| [29] | DUAL_IO_EN | Dual IO Mode Enable |
| 0 = Dual I/O Mode function Disabled. | ||
| 1 = Dual I/O Mode function Enabled. | ||
| [31] | WKEUP_EN | Wake-Up Enable |
| 0 = Wake-up function Disabled when the system enters Power-down mode. | ||
| 1 = Wake-up function Enabled. | ||
| When the system enters Power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. | ||
| After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. |
Definition at line 9291 of file Nano100Series.h.
| __IO uint32_t TIMER_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMR_EN | Timer Counter Enable Bit |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL [5:4] =2'b00) once the value of 24-bit up counter equals the TMRx_CMPR. | ||
| [1] | SW_RST | Software Reset |
| Set this bit will reset the timer counter, pre-scale counter and also force TMR_CTL [TMR_EN] to 0. | ||
| 0 = No effect. | ||
| 1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit. | ||
| Note: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles. | ||
| [2] | WAKE_EN | Wake-Up Enable |
| When WAKE_EN is set and the TMR_IS or TCAP_IS is set, the timer controller will generate a wake-up trigger event to CPU. | ||
| 0 = Wake-up trigger event Disabled. | ||
| 1 = Wake-up trigger event Enabled. | ||
| [3] | DBGACK_EN | ICE Debug Mode Acknowledge Ineffective Enable |
| 0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged. | ||
| 1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not. | ||
| [5:4] | MODE_SEL | Timer Operating Mode Select |
| 00 = The timer is operating in the one-shot mode. | ||
| In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPR. | ||
| And TMR_CTL [TMR_EN] is automatically cleared by hardware. | ||
| 01 = The timer is operating in the periodic mode. | ||
| In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR. | ||
| After that, the 24-bit counter will be reset and starts counting from zero again. | ||
| 10 = The timer is operating in the periodic mode with output toggling. | ||
| In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR. | ||
| After that, the 24-bit counter will be reset and starts counting from zero again. | ||
| At the same time, timer controller will also toggle the output pin TMRx_TOG_OUT to its inverse level (from low to high or from high to low). | ||
| Note: The default level of TMRx_TOG_OUT after reset is low. | ||
| 11 = The timer is operating in continuous counting mode. | ||
| In this mode, the associated interrupt signal is generated when TMR_DR = TMR_CMPR (if TMR_IER [TMR_IE] is enabled). | ||
| However, the 24-bit up-counter counts continuously without reset. | ||
| [7] | TMR_ACT | Timer Active Status Bit (Read Only) |
| This bit indicates the timer counter status of timer. | ||
| 0 = Timer is not active. | ||
| 1 = Timer is in active. | ||
| [8] | ADC_TEEN | TMR_IS Or TCAP_IS Trigger ADC Enable |
| This bit controls if TMR_IS or TCAP_IS could trigger ADC. | ||
| When ADC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to ADC controller. | ||
| When ADC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to ADC controller. | ||
| 0 = TMR_IS or TCAP_IS trigger ADC Disabled. | ||
| 1 = TMR_IS or TCAP_IS trigger ADC Enabled. | ||
| [9] | DAC_TEEN | TMR_IS Or TCAP_IS Trigger DAC Enable |
| This bit controls if TMR_IS or TCAP_IS could trigger DAC. | ||
| When DAC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to DAC controller. | ||
| When DAC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to DAC controller. | ||
| 0 = TMR_IS or TCAP_IS trigger DAC Disabled. | ||
| 1 = TMR_IS or TCAP_IS trigger DAC Enabled. | ||
| [10] | PDMA_TEEN | TMR_IS Or TCAP_IS Trigger PDMA Enable |
| This bit controls if TMR_IS or TCAP_IS could trigger PDMA. | ||
| When PDMA_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to PDMA controller. | ||
| When PDMA_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to PDMA controller. | ||
| 0 = TMR_IS or TCAP_IS trigger PDMA Disabled. | ||
| 1 = TMR_IS or TCAP_IS trigger PDMA Enabled. | ||
| [11] | CAP_TRG_EN | TCAP_IS Trigger Mode Enable |
| This bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA, DAC and ADC while TMR_IS or TCAP_IS is set. | ||
| If this bit is low and TMR_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set. | ||
| If this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA, DAC or ADC while related trigger enable bit (PDMA_TEEN, DAC_TEEN or ADC_TEEN) is also set. | ||
| 0 = TMR_IS is used to trigger PDMA, DAC and ADC. | ||
| 1 = TCAP_IS is used to trigger PDMA, DAC and ADC. | ||
| [12] | EVENT_EN | Event Counting Mode Enable |
| When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin. | ||
| While the transition of external event pin matches the definition of EVENT_EDGE, the 24-bit up-counting timer increases by 1. | ||
| Or, the 24-bit up-counting timer will keep its value unchanged. | ||
| 0 = Timer counting is not controlled by external event pin. | ||
| 1 = Timer counting is controlled by external event pin. | ||
| Note: When EVENT_EN is enabled, user can not choose EXT_TMx(GPB) as clock source. | ||
| However, the speed of chosen clock must 3 times greater than the speed of EXT_TMx(GPB). | ||
| [13] | EVENT_EDGE | Event Counting Mode Edge Selection |
| This bit indicates which edge of external event pin enabling the timer to increase 1. | ||
| 0 = A falling edge of external event enabling the timer to increase 1. | ||
| 1 = A rising edge of external event enabling the timer to increase 1. | ||
| [14] | EVNT_DEB_EN | External Event De-Bounce Enable |
| When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal. | ||
| In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK. | ||
| 0 = De-bounce circuit Disabled. | ||
| 1 = De-bounce circuit Enabled. | ||
| Note: When EVENT_EN is enabled, enable this bit is recommended. | ||
| And, while EVENT_EN is disabled, disable this bit is recommended to save power consumption. | ||
| [16] | TCAP_EN | Tcapture Pin Functional Enable |
| This bit controls if the transition on Tcapture pin could be used as timer counter reset function or timer capture function. | ||
| 0 = The transition on Tcapture pin is ignored. | ||
| 1 = The transition on Tcapture pin will result in the capture or reset of 24-bit timer counter. | ||
| Note: For TMRx_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to low and the Tcapture pin transition is ignored. | ||
| Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EN will be forced to high. | ||
| [17] | TCAP_MODE | Tcapture Pin Function Mode Selection |
| This bit indicates if the transition on Tcapture pin is used as timer counter reset function or timer capture function. | ||
| 0 = The transition on Tcapture pin is used as timer capture function. | ||
| 1 = The transition on Tcapture pin is used as timer counter reset function. | ||
| Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low. | ||
| [19:18] | TCAP_EDGE | Tcapture Pin Edge Detect Selection |
| This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function. | ||
| For timer counter reset function and free-counting mode of timer capture function, the configurations are: | ||
| 00 = A falling edge (1 to 0 transition) on Tcapture pin is an active transition. | ||
| 01 = A rising edge (0 to 1 transition) on Tcapture pin is an active transition. | ||
| 10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions. | ||
| 11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions. | ||
| For trigger-counting mode of timer capture function, the configurations are: | ||
| 00 = 1st falling edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting. | ||
| 01 = 1st rising edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting. | ||
| 10 = Falling edge on Tcapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting. | ||
| 11 = Rising edge on Tcapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting. | ||
| Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11. | ||
| [20] | TCAP_CNT_MODE | Timer Capture Counting Mode Selection |
| This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high. | ||
| If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL field. | ||
| When TCAP_EN is set, TCAP_MODE is 0, and the transition of Tcapture pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAPn. | ||
| If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. | ||
| When TCAP_EN is set, TCAP_MODE is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE setting, the 24-bit up-counting timer will start counting. | ||
| And then if the transition of external pin matches the 2nd transition of TCAP_EDGE setting, the 24-bit up-counting timer will stop counting. | ||
| And its value will be saved into register TMRx_TCAPn. | ||
| 0 = Capture with free-counting timer mode. | ||
| 1 = Capture with trigger-counting timer mode. | ||
| Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the CAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode. | ||
| [22] | TCAP_DEB_EN | Tcapture Pin De-Bounce Enable |
| When CAP_DEB_EN is set, the Tcapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal. | ||
| In de-bounce circuit the Tcapture pin signal will be sampled 4 times by TMRx_CLK. | ||
| 0 = De-bounce circuit Disabled. | ||
| 1 = De-bounce circuit Enabled. | ||
| Note: When TCAP_EN is enabled, enable this bit is recommended. | ||
| And, while TCAP_EN is disabled, disable this bit is recommended to save power consumption. | ||
| [24] | INTR_TRG_EN | Inter-Timer Trigger Mode Enable |
| This bit controls if Inter-timer Trigger mode is enabled. | ||
| If Inter-timer Trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. | ||
| And, TMRx+1 will be in trigger-counting mode of capture function. | ||
| 0 = Inter-timer trigger mode Disabled. | ||
| 1 = Inter-timer trigger mode Enabled. | ||
| Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0. |
Definition at line 9885 of file Nano100Series.h.
| __IO uint32_t UART_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_RST | RX Software Reset |
| When RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and take at least 3 UART engine clock cycles. | ||
| [1] | TX_RST | TX Software Reset |
| When TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and take at least 3 UART engine clock cycles. | ||
| [2] | RX_DIS | Receiver Disable Register |
| The receiver is disabled or not (set "1" to disable receiver) | ||
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| Note1: When used for RS-485 NMM mode, user can set this bit to receive data before detecting address byte. | ||
| Note2: In RS-485 AAD mode, this bit will be setting to "1" automatically. | ||
| Note3: In RS-485 AUD mode and LIN "break + sync +PID" header mode, hardware will control data automatically, so don't fill any value to this bit. | ||
| [3] | TX_DIS | Transfer Disable Register |
| The transceiver is disabled or not (set "1" to disable transceiver) | ||
| 0 = Transfer Enabled. | ||
| 1 = Transfer Disabled. | ||
| [4] | AUTO_RTS_EN | RTSn Auto-Flow Control Enable |
| 0 = RTSn auto-flow control. Disabled. | ||
| 1 = RTSn auto-flow control Enabled. | ||
| Note: When RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the UART_FCR [RTS_Tri_Lev], the UART will reassert RTSn signal. | ||
| [5] | AUTO_CTS_EN | CTSn Auto-Flow Control Enable |
| 0 = CTSn auto-flow control. Disabled | ||
| 1 = CTSn auto-flow control Enabled. | ||
| Note: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted). | ||
| [6] | DMA_RX_EN | RX DMA Enable |
| This bit can enable or disable RX PDMA service. | ||
| 0 = RX PDMA service function Disabled. | ||
| 1 = RX PDMA service function Enabled. | ||
| [7] | DMA_TX_EN | TX DMA Enable |
| This bit can enable or disable TX PDMA service. | ||
| 0 = TX PDMA service function Disabled. | ||
| 1 = TX PDMA service function Enabled. | ||
| [8] | WAKE_CTS_EN | CTSn Wake-Up Function Enable |
| 0 = CTSn wake-up system function Disabled. | ||
| 1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode. | ||
| [9] | WAKE_DATA_EN | Incoming Data Wake-Up Function Enable |
| 0 = Incoming data wake-up system Disabled. | ||
| 1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode. | ||
| Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable | ||
| [12] | ABAUD_EN | Auto-Baud Rate Detect Enable |
| 0 = Auto-baud rate detect function Disabled. | ||
| 1 = Auto-baud rate detect function Enabled. | ||
| Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If UART_IER [ABAUD_IE] be enabled). |
Definition at line 10187 of file Nano100Series.h.
| __IO uint32_t USBD_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | USB_EN | USB Function Enable |
| 0 = USB Disabled. | ||
| 1 = USB Enabled. | ||
| [1] | PHY_EN | PHY Transceiver Enable |
| 0 = PHY transceiver Disabled. | ||
| 1 = PHY transceiver Enabled. | ||
| [2] | PWRDB | Power Down PHY Transceiver, Low Active |
| 0 = Power-down related circuit of PHY transceiver. | ||
| 1 = Turn-on related circuit of PHY transceiver. | ||
| [3] | DPPU_EN | Pull-Up Resistor On USB_DP Enable |
| 0 = Pull-up resistor in USB_DP bus Disabled. | ||
| 1 = Pull-up resistor in USB_DP bus will be active. | ||
| [4] | DRVSE0 | Force USB PHY Transceiver To Drive SE0 (Single Ended Zero) |
| The Single Ended Zero is present when both lines (USB_DP, USB_DM) are being pulled low. | ||
| 0 = None. | ||
| 1 = Force USB PHY transceiver to drive SE0. | ||
| The default value is "1". | ||
| [8] | RWAKEUP | Remote Wake-Up |