|
Apollo Register Documentation v2.4.2
|
| Instance 0 Address: | 0x40021000 |
This register controls the enable for BLE BUCK.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
BLEBUCKEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:1 | RSVD | RO | RESERVED. |
| 0 | BLEBUCKEN | RW | Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed. EN = 0x1 - Enable the BLE Buck. DIS = 0x0 - Disable the BLE Buck. |
| Instance 0 Address: | 0x40021004 |
Provides an indicator for the BLE BUCK and SIMO BUCK status. Once the SIMO BUCK is powered up MEM and CORE LDOs are disabled.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
BLEBUCKON
0x0 |
SIMOBUCKON
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED. |
| 1 | BLEBUCKON | RO | Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate reature is allowed. LDO = 0x0 - Indicates the the LDO is supplying the BLE/Burst power domain BUCK = 0x1 - Indicates the the Buck is supplying the BLE/Burst power domain |
| 0 | SIMOBUCKON | RO | Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck. OFF = 0x0 - Indicates the the SIMO Buck is OFF. ON = 0x1 - Indicates the the SIMO Buck is ON. |
| Instance 0 Address: | 0x40021008 |
This enables various peripherals power domains.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PWRBLEL
0x0 |
PWRPDM
0x0 |
PWRMSPI
0x0 |
PWRSCARD
0x0 |
PWRADC
0x0 |
PWRUART1
0x0 |
PWRUART0
0x0 |
PWRIOM5
0x0 |
PWRIOM4
0x0 |
PWRIOM3
0x0 |
PWRIOM2
0x0 |
PWRIOM1
0x0 |
PWRIOM0
0x0 |
PWRIOS
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:14 | RSVD | RO | RESERVED. |
| 13 | PWRBLEL | RW | Power up BLE controller EN = 0x1 - Power up BLE controller DIS = 0x0 - Power down BLE controller |
| 12 | PWRPDM | RW | Power up PDM block EN = 0x1 - Power up PDM DIS = 0x0 - Power down PDM |
| 11 | PWRMSPI | RW | Power up MSPI Controller EN = 0x1 - Power up MSPI DIS = 0x0 - Power down MSPI |
| 10 | PWRSCARD | RW | Power up SCARD Controller EN = 0x1 - Power up SCARD DIS = 0x0 - Power down SCARD |
| 9 | PWRADC | RW | Power up ADC Digital Controller EN = 0x1 - Power up ADC DIS = 0x0 - Power Down ADC |
| 8 | PWRUART1 | RW | Power up UART Controller 1 EN = 0x1 - Power up UART 1 DIS = 0x0 - Power down UART 1 |
| 7 | PWRUART0 | RW | Power up UART Controller 0 EN = 0x1 - Power up UART 0 DIS = 0x0 - Power down UART 0 |
| 6 | PWRIOM5 | RW | Power up IO Master 5 EN = 0x1 - Power up IO Master 5 DIS = 0x0 - Power down IO Master 5 |
| 5 | PWRIOM4 | RW | Power up IO Master 4 EN = 0x1 - Power up IO Master 4 DIS = 0x0 - Power down IO Master 4 |
| 4 | PWRIOM3 | RW | Power up IO Master 3 EN = 0x1 - Power up IO Master 3 DIS = 0x0 - Power down IO Master 3 |
| 3 | PWRIOM2 | RW | Power up IO Master 2 EN = 0x1 - Power up IO Master 2 DIS = 0x0 - Power down IO Master 2 |
| 2 | PWRIOM1 | RW | Power up IO Master 1 EN = 0x1 - Power up IO Master 1 DIS = 0x0 - Power down IO Master 1 |
| 1 | PWRIOM0 | RW | Power up IO Master 0 EN = 0x1 - Power up IO Master 0 DIS = 0x0 - Power down IO Master 0 |
| 0 | PWRIOS | RW | Power up IO Slave EN = 0x1 - Power up IO slave DIS = 0x0 - Power down IO slave |
| Instance 0 Address: | 0x4002100C |
This controls the power down of the SRAM banks in deep sleep mode. If this is set, then the power for that SRAM bank will be gated when the core goes into deep sleep. Upon wake, the data within the SRAMs will be erased. If this is not set, retention voltage will be applied to the SRAM bank when the core goes into deep sleep. Upon wake, the data within the SRAMs are retained. Do not set this if the SRAM bank is used as the target for DMA transfer while CPU in deepsleep.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CACHEPWDSLP
0x0 |
RSVD
0x0 |
FLASH1PWDSLP
0x1 |
FLASH0PWDSLP
0x1 |
SRAMPWDSLP
0x0 |
DTCMPWDSLP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CACHEPWDSLP | RW | power down cache in deep sleep EN = 0x1 - Power down cache in deep sleep DIS = 0x0 - Retain cache in deep sleep |
| 30:15 | RSVD | RO | RESERVED. |
| 14 | FLASH1PWDSLP | RW | Powerdown flash1 in deep sleep EN = 0x1 - Flash1 is powered down during deepsleep DIS = 0x0 - Flash1 is kept powered on during deepsleep |
| 13 | FLASH0PWDSLP | RW | Powerdown flash0 in deep sleep EN = 0x1 - Flash0 is powered down during deepsleep DIS = 0x0 - Flash0 is kept powered on during deepsleep |
| 12:3 | SRAMPWDSLP | RW | Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost. NONE = 0x0 - All banks retained GROUP0 = 0x1 - SRAM GROUP0 powered down (64KB-96KB) GROUP1 = 0x2 - SRAM GROUP1 powered down (96KB-128KB) GROUP2 = 0x4 - SRAM GROUP2 powered down (128KB-160KB) GROUP3 = 0x8 - SRAM GROUP3 powered down (160KB-192KB) GROUP4 = 0x10 - SRAM GROUP4 powered down (192KB-224KB) GROUP5 = 0x20 - SRAM GROUP5 powered down (224KB-256KB) GROUP6 = 0x40 - SRAM GROUP6 powered down (256KB-288KB) GROUP7 = 0x80 - SRAM GROUP7 powered down (288KB-320KB) GROUP8 = 0x100 - SRAM GROUP8 powered down (320KB-352KB) GROUP9 = 0x200 - SRAM GROUP9 powered down (352KB-384KB) SRAM32K = 0x1 - Powerdown lower 32k SRAM (64KB-96KB) SRAM64K = 0x3 - Powerdown lower 64k SRAM (64KB-128KB) SRAM128K = 0xF - Powerdown lower 128k SRAM (64KB-192KB) ALLBUTLOWER32K = 0x3FE - All SRAM banks but lower 32k powered down (96KB-384KB). ALLBUTLOWER64K = 0x3FC - All banks but lower 64k powered down. ALLBUTLOWER128K = 0x3F0 - All banks but lower 128k powered down. ALL = 0x3FF - All banks powered down. |
| 2:0 | DTCMPWDSLP | RW | power down DTCM in deep sleep NONE = 0x0 - All DTCM retained GROUP0DTCM0 = 0x1 - Group0_DTCM0 powered down in deep sleep (0KB-8KB) GROUP0DTCM1 = 0x2 - Group0_DTCM1 powered down in deep sleep (8KB-32KB) GROUP0 = 0x3 - Both DTCMs in group0 are powered down in deep sleep (0KB-32KB) ALLBUTGROUP0DTCM0 = 0x6 - Group1 and Group0_DTCM1 are powered down in deep sleep (8KB-64KB) GROUP1 = 0x4 - Group1 DTCM powered down in deep sleep (32KB-64KB) ALL = 0x7 - All DTCMs powered down in deep sleep (0KB-64KB) |
| Instance 0 Address: | 0x40021010 |
This register enables the individual banks for the memories. When set, power will be enabled to the banks. This register works in conjection with the MEMPWDINSLEEP register. When this register is set, then the MEMPWRINSLEEP register will determine whether power is enabled to the SRAMs in deep sleep. If this register is not set, then power will always be disabled to the memory bank.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CACHEB2
0x1 |
CACHEB0
0x1 |
RSVD
0x0 |
FLASH1
0x1 |
FLASH0
0x1 |
SRAM
0x3ff |
DTCM
0x7 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CACHEB2 | RW | Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank2, cache has to be enabled and this bit has to be set. EN = 0x1 - Power up Cache Bank 2 DIS = 0x0 - Power down Cache Bank 2 |
| 30 | CACHEB0 | RW | Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank0, cache has to be enabled and this bit has to be set. EN = 0x1 - Power up Cache Bank 0 DIS = 0x0 - Power down Cache Bank 0 |
| 29:15 | RSVD | RO | RESERVED. |
| 14 | FLASH1 | RW | Power up Flash1 EN = 0x1 - Power up Flash1 DIS = 0x0 - Power down Flash1 |
| 13 | FLASH0 | RW | Power up Flash0 EN = 0x1 - Power up Flash0 DIS = 0x0 - Power down Flash0 |
| 12:3 | SRAM | RW | Power up SRAM groups NONE = 0x0 - Do not power ON any of the SRAM banks GROUP0 = 0x1 - Power ON only SRAM group0 (0KB-32KB) GROUP1 = 0x2 - Power ON only SRAM group1 (32KB-64KB) GROUP2 = 0x4 - Power ON only SRAM group2 (64KB-96KB) GROUP3 = 0x8 - Power ON only SRAM group3 (96KB-128KB) GROUP4 = 0x10 - Power ON only SRAM group4 (128KB-160KB) GROUP5 = 0x20 - Power ON only SRAM group5 (160KB-192KB) GROUP6 = 0x40 - Power ON only SRAM group6 (192KB-224KB) GROUP7 = 0x80 - Power ON only SRAM group7 (224KB-256KB) GROUP8 = 0x100 - Power ON only SRAM group8 (256KB-288KB) GROUP9 = 0x200 - Power ON only SRAM group9 (288KB-320KB) SRAM32K = 0x1 - Power ON only lower 32k SRAM64K = 0x3 - Power ON only lower 64k SRAM128K = 0xF - Power ON only lower 128k SRAM256K = 0xFF - Power ON only lower 256k ALL = 0x3FF - All SRAM banks (320K) powered ON |
| 2:0 | DTCM | RW | Power up DTCM NONE = 0x0 - Do not enable power to any DTCMs GROUP0DTCM0 = 0x1 - Power ON only GROUP0_DTCM0 GROUP0DTCM1 = 0x2 - Power ON only GROUP0_DTCM1 GROUP0 = 0x3 - Power ON only DTCMs in group0 GROUP1 = 0x4 - Power ON only DTCMs in group1 ALL = 0x7 - Power ON all DTCMs |
| Instance 0 Address: | 0x40021014 |
It provides the power status for all the memory banks including- caches, flash (0 and 1) and all the SRAM groups. The status here should reflect the enable provided by the MEMPWREN register. There may be a lag time between setting the bits in MEMPWREN register and MEMPWRSTATUS register, due to the need to cycle the power gate and isolation seqeunces to the memory banks.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CACHEB2
0x0 |
CACHEB0
0x0 |
FLASH1
0x1 |
FLASH0
0x1 |
SRAM9
0x1 |
SRAM8
0x1 |
SRAM7
0x1 |
SRAM6
0x1 |
SRAM5
0x1 |
SRAM4
0x1 |
SRAM3
0x1 |
SRAM2
0x1 |
SRAM1
0x1 |
SRAM0
0x1 |
DTCM1
0x1 |
DTCM01
0x1 |
DTCM00
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:17 | RSVD | RO | This bitfield is reserved for future use. |
| 16 | CACHEB2 | RO | This bit is 1 if power is supplied to Cache Bank 2 |
| 15 | CACHEB0 | RO | This bit is 1 if power is supplied to Cache Bank 0 |
| 14 | FLASH1 | RO | This bit is 1 if power is supplied to FLASH 1 |
| 13 | FLASH0 | RO | This bit is 1 if power is supplied to FLASH 0 |
| 12 | SRAM9 | RO | This bit is 1 if power is supplied to SRAM GROUP9 |
| 11 | SRAM8 | RO | This bit is 1 if power is supplied to SRAM GROUP8 |
| 10 | SRAM7 | RO | This bit is 1 if power is supplied to SRAM GROUP7 |
| 9 | SRAM6 | RO | This bit is 1 if power is supplied to SRAM GROUP6 |
| 8 | SRAM5 | RO | This bit is 1 if power is supplied to SRAM GROUP5 |
| 7 | SRAM4 | RO | This bit is 1 if power is supplied to SRAM GROUP4 |
| 6 | SRAM3 | RO | This bit is 1 if power is supplied to SRAM GROUP3 |
| 5 | SRAM2 | RO | This bit is 1 if power is supplied to SRAM GROUP2 |
| 4 | SRAM1 | RO | This bit is 1 if power is supplied to SRAM GROUP1 |
| 3 | SRAM0 | RO | This bit is 1 if power is supplied to SRAM GROUP0 |
| 2 | DTCM1 | RO | This bit is 1 if power is supplied to DTCM GROUP1 |
| 1 | DTCM01 | RO | This bit is 1 if power is supplied to DTCM GROUP0_1 |
| 0 | DTCM00 | RO | This bit is 1 if power is supplied to DTCM GROUP0_0 |
| Instance 0 Address: | 0x40021018 |
This provides the power status for the peripheral devices- BLEL, PDM, PDM, MSPI, SCARD, ADC, UART0 & 1, IOM5 to 0, IOSLAVE and MCUL (DMA and Fabrics) and MCUH (ARM core). The status here should reflect the enable provided by the DEVPWREN register. There may be a lag time between setting the bits in DEVPWREN register and DEVPWRSTATUS register, due to the need to cycle the power gate, isolation and reset seqeunces to the device power domains.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SYSDEEPSLEEP
0x0 |
COREDEEPSLEEP
0x0 |
CORESLEEP
0x0 |
RSVD
0x0 |
BLEH
0x0 |
BLEL
0x0 |
PWRPDM
0x0 |
PWRMSPI
0x0 |
PWRADC
0x0 |
HCPC
0x0 |
HCPB
0x0 |
HCPA
0x0 |
MCUH
0x1 |
MCUL
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | SYSDEEPSLEEP | RO | This bit is 1 if SYSTEM has been in Deep Sleep. Write '1' to this bit to clear it. |
| 30 | COREDEEPSLEEP | RO | This bit is 1 if CORE has been in Deep Sleep. Write '1' to this bit to clear it. |
| 29 | CORESLEEP | RO | This bit is 1 if CORE has been in SLEEP State. Write '1' to this bit to clear it. |
| 28:10 | RSVD | RO | This bitfield is reserved for future use. |
| 9 | BLEH | RO | This bit is 1 if power is supplied to BLEH |
| 8 | BLEL | RO | This bit is 1 if power is supplied to BLEL |
| 7 | PWRPDM | RO | This bit is 1 if power is supplied to PDM |
| 6 | PWRMSPI | RO | This bit is 1 if power is supplied to MSPI |
| 5 | PWRADC | RO | This bit is 1 if power is supplied to ADC |
| 4 | HCPC | RO | This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6) |
| 3 | HCPB | RO | This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2) |
| 2 | HCPA | RO | This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD) |
| 1 | MCUH | RO | This bit is 1 if power is supplied to MCUH |
| 0 | MCUL | RO | This bit is 1 if power is supplied to MCUL |
| Instance 0 Address: | 0x4002101C |
This register provides additional fine-tune power management controls for the SRAMs and the SRAM controller. This includes enabling light sleep for the SRAM and TCM banks, and clock gating for reduced dynamic power.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
SRAMLIGHTSLEEP
0x0 |
RSVD
0x0 |
SRAMMASTERCLKGATE
0x0 |
SRAMCLKGATE
0x0 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:20 | RSVD | RO | This bitfield is reserved for future use. |
| 19:8 | SRAMLIGHTSLEEP | RW | Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses. ALL = 0xFF - Enable LIGHT SLEEP for ALL SRAMs DIS = 0x0 - Disables LIGHT SLEEP for ALL SRAMs |
| 7:3 | RSVD | RO | This bitfield is reserved for future use. |
| 2 | SRAMMASTERCLKGATE | RW | This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block) EN = 0x1 - Enable Master SRAM Clock Gate DIS = 0x0 - Disables Master SRAM Clock Gating |
| 1 | SRAMCLKGATE | RW | This bit is 1 if clock gating is allowed for individual system SRAMs EN = 0x1 - Enable Individual SRAM Clock Gating DIS = 0x0 - Disables Individual SRAM Clock Gating |
| 0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x40021020 |
This provides the power status for various blocks within the ADC. These status comes directly from the ADC module and is captured through this interface.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
REFBUFPWD
0x1 |
REFKEEPPWD
0x1 |
VBATPWD
0x1 |
VPTATPWD
0x1 |
BGTPWD
0x1 |
ADCPWD
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:6 | RSVD | RO | RESERVED. |
| 5 | REFBUFPWD | RO | This bit indicates that the ADC REFBUF is powered down |
| 4 | REFKEEPPWD | RO | This bit indicates that the ADC REFKEEP is powered down |
| 3 | VBATPWD | RO | This bit indicates that the ADC VBAT resistor divider is powered down |
| 2 | VPTATPWD | RO | This bit indicates that the ADC temperature sensor input buffer is powered down |
| 1 | BGTPWD | RO | This bit indicates that the ADC Band Gap is powered down |
| 0 | ADCPWD | RO | This bit indicates that the ADC is powered down |
| Instance 0 Address: | 0x40021024 |
This register includes additional debug control bits. This is an internal Ambiq-only register. Customers should not attempt to change this or else functionality cannot be guaranteed.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FORCEBLEBUCKACT
0x0 |
MEMVRLPBLE
0x0 |
FORCEMEMVRADC
0x0 |
FORCEMEMVRLPTIMERS
0x0 |
FORCECOREVRLPTIMERS
0x0 |
FORCECOREVRLPPDM
0x0 |
SIMOBUCKEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:8 | RSVD | RO | RESERVED. |
| 7 | FORCEBLEBUCKACT | RW | Control Bit to enable BLE Buck to be in active state when BLE Buck is enabled. Default behavior is to be in active only when Burst or BLEH power on are requested. |
| 6 | MEMVRLPBLE | RW | Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it. EN = 0x1 - Mem VR can go to lp mode even when BLE is powered on. DIS = 0x0 - Mem VR will stay in active mode when BLE is powered on. |
| 5:4 | FORCEMEMVRADC | RW | Control Bit to force mem VR to LP or ACT mode in deep sleep when ADC is powered ON. 0x3 results in picking LP mode. ACT = 0x2 - In this mode if all the other domains but ADC are powered down, mem VR will stay in ACT mode. LP = 0x1 - In this mode if all the other domains but ADC are powered down, mem VR will stay in LP mode. DIS = 0x0 - In this mode if all the other domains but ADC are powered down, mem VR will duty cycle between active and LP modes depending on ADC sampling. |
| 3 | FORCEMEMVRLPTIMERS | RW | Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running. |
| 2 | FORCECOREVRLPTIMERS | RW | Control Bit to force Core VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running. |
| 1 | FORCECOREVRLPPDM | RW | Control bit to enable the core VR to go into LP mode with HCPA/B/C/MSPI are powered off but PDM is powered on |
| 0 | SIMOBUCKEN | RW | Enables and Selects the SIMO Buck as the supply for the low-voltage power domain. It takes the initial value from the bit set in Customer INFO space. EN = 0x1 - Enable the SIMO Buck DIS = 0x0 - Disable the SIMO Buck |
| Instance 0 Address: | 0x40021028 |
This register controls which feature trigger will result in an event to the CPU. It includes all the power on status for the core domains, as well as the Burst event. If any bits are set, then if the domain is turned on, it will result in an event to the ARM core.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BURSTEVEN
0x0 |
BURSTFEATUREEVEN
0x0 |
BLEFEATUREEVEN
0x0 |
RSVD
0x0 |
BLELEVEN
0x0 |
PDMEVEN
0x0 |
MSPIEVEN
0x0 |
ADCEVEN
0x0 |
HCPCEVEN
0x0 |
HCPBEVEN
0x0 |
HCPAEVEN
0x0 |
MCUHEVEN
0x0 |
MCULEVEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | BURSTEVEN | RW | Control BURST status event EN = 0x1 - Enable BURST status event DIS = 0x0 - Disable BURST status event |
| 30 | BURSTFEATUREEVEN | RW | Control BURSTFEATURE status event EN = 0x1 - Enable BURSTFEATURE status event DIS = 0x0 - Disable BURSTFEATURE status event |
| 29 | BLEFEATUREEVEN | RW | Control BLEFEATURE status event EN = 0x1 - Enable BLEFEATURE status event DIS = 0x0 - Disable BLEFEATURE status event |
| 28:9 | RSVD | RO | RESERVED. |
| 8 | BLELEVEN | RW | Control BLE power-on status event EN = 0x1 - Enable BLE power-on status event DIS = 0x0 - Disable BLE power-on status event |
| 7 | PDMEVEN | RW | Control PDM power-on status event EN = 0x1 - Enable PDM power-on status event DIS = 0x0 - Disable PDM power-on status event |
| 6 | MSPIEVEN | RW | Control MSPI power-on status event EN = 0x1 - Enable MSPI power-on status event DIS = 0x0 - Disable MSPI power-on status event |
| 5 | ADCEVEN | RW | Control ADC power-on status event EN = 0x1 - Enable ADC power-on status event DIS = 0x0 - Disable ADC power-on status event |
| 4 | HCPCEVEN | RW | Control HCPC power-on status event EN = 0x1 - Enable HCPC power-on status event DIS = 0x0 - Disable HCPC power-on status event |
| 3 | HCPBEVEN | RW | Control HCPB power-on status event EN = 0x1 - Enable HCPB power-on status event DIS = 0x0 - Disable HCPB power-on status event |
| 2 | HCPAEVEN | RW | Control HCPA power-on status event EN = 0x1 - Enable HCPA power-on status event DIS = 0x0 - Disable HCPA power-on status event |
| 1 | MCUHEVEN | RW | Control MCUH power-on status event EN = 0x1 - Enable MCHU power-on status event DIS = 0x0 - Disable MCUH power-on status event |
| 0 | MCULEVEN | RW | Control MCUL power-on status event EN = 0x1 - Enable MCUL power-on status event DIS = 0x0 - Disable MCUL power-on status event |
| Instance 0 Address: | 0x4002102C |
This register controls which power enable for the memories will result in an event to the CPU. It includes all the power on status for the memory domains. If any bits are set, then if the domain is turned on, it will result in an event to the ARM core.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CACHEB2EN
0x0 |
CACHEB0EN
0x0 |
RSVD
0x0 |
FLASH1EN
0x0 |
FLASH0EN
0x0 |
SRAMEN
0x0 |
DTCMEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CACHEB2EN | RW | Control CACHEB2 power-on status event EN = 0x1 - Enable CACHE BANK 2 status event DIS = 0x0 - Disable CACHE BANK 2 status event |
| 30 | CACHEB0EN | RW | Control CACHE BANK 0 power-on status event EN = 0x1 - Enable CACHE BANK 0 status event DIS = 0x0 - Disable CACHE BANK 0 status event |
| 29:15 | RSVD | RO | RESERVED. |
| 14 | FLASH1EN | RW | Control Flash power-on status event EN = 0x1 - Enable FLASH status event DIS = 0x0 - Disables FLASH status event |
| 13 | FLASH0EN | RW | Control Flash power-on status event EN = 0x1 - Enable FLASH status event DIS = 0x0 - Disables FLASH status event |
| 12:3 | SRAMEN | RW | Control SRAM power-on status event NONE = 0x0 - Disable SRAM power-on status event GROUP0EN = 0x1 - Enable SRAM group0 (0KB-32KB) power on status event GROUP1EN = 0x2 - Enable SRAM group1 (32KB-64KB) power on status event GROUP2EN = 0x4 - Enable SRAM group2 (64KB-96KB) power on status event GROUP3EN = 0x8 - Enable SRAM group3 (96KB-128KB) power on status event GROUP4EN = 0x10 - Enable SRAM group4 (128KB-160KB) power on status event GROUP5EN = 0x20 - Enable SRAM group5 (160KB-192KB) power on status event GROUP6EN = 0x40 - Enable SRAM group6 (192KB-224KB) power on status event GROUP7EN = 0x80 - Enable SRAM group7 (224KB-256KB) power on status event GROUP8EN = 0x100 - Enable SRAM group8 (256KB-288KB) power on status event GROUP9EN = 0x200 - Enable SRAM group9 (288KB-320KB) power on status event |
| 2:0 | DTCMEN | RW | Enable DTCM power-on status event NONE = 0x0 - Do not enable DTCM power-on status event GROUP0DTCM0EN = 0x1 - Enable GROUP0_DTCM0 power on status event GROUP0DTCM1EN = 0x2 - Enable GROUP0_DTCM1 power on status event GROUP0EN = 0x3 - Enable DTCMs in group0 power on status event GROUP1EN = 0x4 - Enable DTCMs in group1 power on status event ALL = 0x7 - Enable all DTCM power on status event |


My name is Rimpy Saini. I have done masters in biotechnology. I was working with a multinational company as "Pharmacovigilance Associate and Trainer". I have a lot of interest in genetics and immunology . Apart from that I like playing chess and badminton. I also like listening to music.
There are number of reasons as to why we should learn coding....
At first I was a bit scared, as this was a new field altogether for me but later when I started learning HTML and CSS I got interested in this and I found it to be easy and fun. But But But..... When we started with Java in week three, it again shook my confidence but I hope with a lot more effort I will be able to cope with this as well. It's really interesting and fun to see how we can design our website and play around it with so many stylings.
next


DfE enquiries
Central newsdesk 020 7783 8300
General enquiries 0370 000 2288
Press release
Young people urged to help the government shape new peer support networks so they can talk openly about mental health.
A £1.5 million fund driven by young people to help them develop support networks and talk about mental health, with online advice and workshops to help set them up, has been announced today (17 February 2016) by Education Secretary Nicky Morgan.
Within this, a digital innovation fund will be used to provide new and engaging online resources for parents and young people such as mobile phone apps.
We know that young people are often the first to spot when something is wrong with their friends and often confide in each other first - whether that’s a friend who is suffering from an eating disorder or someone not coping with exam stress at school. That’s why we must train them in how to spot the signs so they can then get the help they need.
A new advisory group will gather evidence from young people about their experiences and work with schools that are running successful peer to peer support networks, so this approach can be extended to thousands of schools across the country.
The group will be supported by experts from charities, including Young Minds; headteachers, and young people themselves.
Young people want to be involved and to share their views, and often turn to social media to do this. So today, Education Secretary Nicky Morgan is urging young people to get involved and tell the government what help they would need to set up peer support networks.
The call for evidence has been launched on social media platforms such as Twitter and sites such as Sugarscape to make it easier for young people to get involved.
Education Secretary Nicky Morgan said:
We know that if mental health issues aren’t tackled in children, it can blight their lives as adults. That’s why I think all schools should be having an open and frank conversation about mental health so that we continue to tackle the stigma that still surrounds it and ensure every child gets the support they need.
The truth is that the people who best understand the pressures that young people face are their classmates and friends - they’re the ones that spot the telltale signs that their friends are experiencing problems, and the people to whom children are most likely to turn for support. That’s why today’s announcements are about giving young people the training they need to spot the signs of mental health issues and get the support they need. To do that we will be working with schools, mental health experts, charities - and most importantly young people themselves.
The information gathered through the call for evidence, launched today, will be used by the advisory group to develop peer support pilot schemes - setting up projects learning from those that are already doing it well - to inspire other young people.
The group will also be looking at key issues that affect specific groups of young people, such as helping vulnerable groups, including children in care, as well as helping parents understand how to talk about mental health with their children and working with schools.
Today’s announcement builds on the package of support announced by the Prime Minister this week, which included £1 billion to put mental health and physical health on an equal footing by 2020 providing mental health care to 70,000 more children and young people.
It is part of a wider package of work being done by the Department for Education to improve children’s mental health, including a £3 million joint pilot scheme with NHS England for schools and local mental health services to provide more joined up support; counselling guidance, and the appointment of Sam Gyimah as the first ever DfE Minister with responsibility for mental health.
Peer support networks can mean anything from informal buddying schemes to one-on-one and group sessions with trained support, and can happen face-to-face or online.
They can help young people show solidarity with their classmates and friends; tackle the isolation and insecurity that often accompany mental illness; and help take the stigma out of mental health by improving young people’s understanding.
There are already great examples of this kind of support happening. In Sandon School in Essex pupils volunteer as mentors and wear a badge so they can be easily identified by other pupils who might need someone to talk to about issues they are facing.
At any one time, 1 in 10 children are suffering from a mental illness. More than half of all adults who face mental health problems later on in life were diagnosed with these issues as a child - demonstrating why it is so important that they are able to access support at school.
For example eating disorders, including anorexia, kill more young people than any other mental illness. That is why the government has introduced a new eating disorder waiting time standard - aiming for 95% of patients being seen within 4 weeks, or 1 week for urgent cases, by 2020. We want to complement this by also providing support in schools, through early intervention and peer support.
Peer support can also help build character and resilience, ensuring no child is left behind, whatever their background or start in life.
Earlier this week, the Mental Health Taskforce identified clear links between work and good mental health. Young people need good mental health, character and resilience to be able to succeed later in life.
Education and Childcare Minister Sam Gyimah said:
We are at a turning point in how we tackle children’s mental health issues and we are determined to put children and young people at the heart of this process.
That’s why today, I am excited to announce this funding to help encourage young people to champion each other’s mental wellbeing, and work together to promote good mental health.
I have met some impressive young people who have shown that peer support can work really well, and I want to see more of this high-quality support benefiting young people up and down the country.
Helen Newman, Assistant Head Teacher at Sandon School and member of the advisory group, said:
Peer support is a very important part of our school. The work that peer mentors and their mentees do together builds resilience and self-esteem on both sides. Young people that would otherwise find it difficult to engage with support feel reassured knowing that they have someone in school to turn to who is close to them in age, who may have had similar experiences to them and who won’t judge them. Mentors, some of whom have been mentees themselves in the past, embrace the responsibility for supporting others and the high esteem in which they are held by students and staff helps them develop their own confidence.
The Department for Education has also today updated its counselling guidance , which provides practical, evidence-based advice, informed by experts on how to make sure school counselling works for children and young people. This will help all schools make counselling available to their pupils.
See the call for evidence .
The Department for Education has already invested £3 million in 22 mental health pilots to provide a single point of contact between schools and their local NHS health services. The pilot is working with teachers, parents and pupils to better understand mental health issues, helping them access the right support and ensuring that the any referrals are timely and appropriate.
Sam Gyimah is the first minister in DfE to have specific responsibility for mental health in his portfolio and he is working closely with Alistair Burt, the minister responsible for mental health in the Department of Health.
Natasha Devon has been appointed as the department’s first mental health champion. She will use her experience to encourage more young people to talk openly about mental health issues.
The department has worked with expert organisations to provide guidance and lesson plans on how to teach about mental health. It has also given schools advice on how to run high-quality, school-based counselling and support pupils.
See the updated school counselling guidance .
Central newsdesk 020 7783 8300
General enquiries 0370 000 2288
Published: 17 February 2016


{% extends 'base_email.html' %} {% load review_tags %} {% block body %}
{{current_tenant.name}}’s procurement team is piloting a supplier platform to capture knowledge and collaborate with our suppliers at {{ tenant_url }}. This private website will allow {{current_tenant.name}} employees to search and find existing {{current_tenant.name}} suppliers, view work history with {{current_tenant.name}}, and initiate requests.
{{ portfolio_item.vendor }} has indicated that they worked with you on “{{portfolio_item.title}}” project.
If this is true, could you add a review so that other {{current_tenant.name}} employees can benefit from your experience.
Review {{ portfolio_item.vendor }}
If you haven't worked with this supplier or if the project information is incorrect, please contact the supplier directly or {{ current_tenant.email }} and we can work with the supplier to make the necessary corrections.
This private website {{ tenant_url }} will be available to all {{current_tenant.name}} employees from the {{current_tenant.name}} Intranet and will be powered by the Proven platform. If you have any questions about the Proven platform, please contact Suzanne Jordan at<EMAIL_ADDRESS>Best,
{{ portfolio_item.vendor }},


Exosystem
Modera Apartment
Hawaii
VA
Amazon
Fiancee’s Co-workers
Disability Compensation
USA
Korea
Housing Price
Austin, TX
Self
Modera Apartment
Hawaii
VA
Amazon
Fiancee’s Co-workers
Disability Compensation
USA
Korea
Housing Price
Austin, TX
Self


To-Do List
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wavepipe
Want to help make an awesome web UI for wavepipe? Contact Matt: mdlayher (at) gmail (dot) com!


|
BTK
0.3dev.0
Open-source library to visualize/process biomechanical data
|
Container of analog channels representing an inertial measurement unit (IMU). More...
#include <btkIMU.h>
Public Types | |
| typedef SharedPtr< const IMU > | ConstPointer |
| typedef SharedPtr< IMU > | Pointer |
| typedef Eigen::Matrix< double, 3, 3 > | Rotation |
| Public Types inherited from btk::DataObjectLabeled | |
| typedef SharedPtr< const DataObjectLabeled > | ConstPointer |
| typedef SharedPtr < DataObjectLabeled > | Pointer |
| Public Types inherited from btk::DataObject | |
| typedef SharedPtr< const DataObject > | ConstPointer |
| typedef SharedPtr< DataObject > | Pointer |
| Public Types inherited from btk::Object | |
| typedef SharedPtr< const Object > | ConstPointer |
| typedef SharedPtr< Object > | Pointer |
Static Public Member Functions | |
| static Pointer | New (const std::string &label="IMU", const std::string &desc="") |
Protected Member Functions | |
| IMU (int type, const std::string &label, const std::string &desc) | |
| IMU (const IMU &toCopy) | |
| Protected Member Functions inherited from btk::DataObjectLabeled | |
| DataObjectLabeled (const std::string &label="", const std::string &description="") | |
| DataObjectLabeled (const DataObjectLabeled &toCopy) | |
| Protected Member Functions inherited from btk::DataObject | |
| DataObject () | |
| DataObject (const DataObject &toCopy) | |
| virtual | ~DataObject () |
| Protected Member Functions inherited from btk::Object | |
| Object () | |
| Object (const Object &toCopy) | |
| virtual | ~Object () |
Additional Inherited Members | |
| Protected Attributes inherited from btk::DataObjectLabeled | |
| std::string | m_Description |
| std::string | m_Label |
Container of analog channels representing an inertial measurement unit (IMU).
This class proposes to store any number of analog channels but the 6 first channels could be used for 3 accelerometers and 3 gyroscopes as some convenient methods are proposed in this way (see SetChannels(), GetAccelerometerX(), GetAccelerometerY(), GetAccelerometerZ(), GetGyroscopeX(), GetGyroscopeY(), GetGyroscopeZ()).
The storage of the channel is done using an ID and not an array index. You can then use the same ID for some kind of sensor even if other are missing (i.e. IMU with accelerometers disabled or configured with 1 acc, and 2 gyros., etc.).
Note: This class is still experimental and could be modified in the next release.
Smart pointer associated with a const IMU object.
Smart pointer associated with a IMU object.
Type definition for Eigen 3x3 rotation matrix (of double).
|
protected |
Constructor
|
protected |
Constructor of copy
|
inline |
Deep copy of the current object.
|
inline |
Convenient method to return the analog channel with the ID 0 (which should correspond to an accelerometer measuring data on the X axis of the IMU).
|
inline |
Convenient method to return the analog channel with the ID 1 (which should correspond to an accelerometer measuring data on the Y axis of the IMU).
|
inline |
Convenient method to return the analog channel with the ID 2 (which should correspond to an accelerometer measuring data on the Z axis of the IMU).
| Analog::Pointer btk::IMU::GetChannel | ( | int | id | ) |
Returns the analog channel with the given ID. If there is no analog channel with the given ID, then an exception is thrown.
| Analog::ConstPointer btk::IMU::GetChannel | ( | int | id | ) | const |
Returns the analog channel with the given ID. If there is no analog channel with the given ID, then an exception is thrown.
| Analog::Pointer btk::IMU::GetChannel | ( | const std::string & | label | ) |
Returns the analog channel with the given label. If there is no analog channel with the given label, then an exception is thrown.
| Analog::ConstPointer btk::IMU::GetChannel | ( | const std::string & | label | ) | const |
Returns the analog channel with the given label. If there is no analog channel with the given label, then an exception is thrown.
| AnalogCollection::Pointer btk::IMU::GetChannels | ( | ) |
Returns the analog channels of the IMU in a collection. The analog channels are pushed in the collection by using their ID.
|
inline |
Returns the number of frames set in this IMU.
|
inline |
Returns the frequency set to the IMU. (by default it is 0 Hz).
|
inline |
Convenient method to return the analog channel with the ID 3 (which should correspond to a gyroscope measuring data on the X axis of the IMU).
|
inline |
Convenient method to return the analog channel with the ID 4 (which should correspond to a gyroscope measuring data on the Y axis of the IMU).
|
inline |
Convenient method to return the analog channel with the ID 5 (which should correspond to a gyroscope measuring data on the Z axis of the IMU).
|
inlinestatic |
Creates a smart pointer associated with a IMU object.
| void btk::IMU::Rotate | ( | const Rotation & | R | ) |
Convenient method to rotate the analog channels with the IDs 0-5. This method handles the case where some of these analog channels are missing.
| void btk::IMU::SetChannel | ( | int | id, |
| Analog::Pointer | channel | ||
| ) |
Sets an analog channel to the given ID. If an analog channel is already set to this ID, then it is replaced.
| void btk::IMU::SetChannels | ( | Analog::Pointer | accX, |
| Analog::Pointer | accY, | ||
| Analog::Pointer | accZ, | ||
| Analog::Pointer | gyroX, | ||
| Analog::Pointer | gyroY, | ||
| Analog::Pointer | gyroZ | ||
| ) |
Sets the 6 first channels of the IMUs with the analog channels accX, accY, accZ, gyroX, gyroY, gyroZ.
| void btk::IMU::SetFrameNumber | ( | int | fn | ) |
Set the number of frames for the IMU and modify also the number of frames for the channels.
| void btk::IMU::SetFrequency | ( | double | f | ) |
Sets the acquisition sample rate associated to the IMU.


{%extends "main/base.html"%} {% load static %} {% block content %}
Gayatri Mantra - A Universal Prayer
Here are your notes:
{% for note_i in notes %}{{note_i.note}}
{% endfor %}Om Bhur Bhuvaḥ Swaḥ
Tat-savitur Vareñyaṃ
Bhargo Devasya Dheemahi
Dhiyo Yonaḥ Prachodayāt
General meaning:
We meditate on that most adored Supreme Lord, the creator, whose effulgence (divine light) illumines all realms (physical, mental and spiritual). May this divine
light illumine our intellect.
Word meaning:
Om:The primeval sound;
Bhur: the physical body/physical realm;
Bhuvah: the life force/the mental realm
Suvah: the soul/spiritual realm;
Tat: That (God);
Savitur: the Sun, Creator (source of all life);
Vareñyam: adore;
Bhargo: effulgence (divine light);
Devasya: supreme Lord;
Dhīmahi: meditate;
Dhiyo: the intellect;
Yo: May this light;
Nah: our;
Prachodayāt: illumine/inspire.


MassFX v3 Update! [$]
Alberto Gonzalez writes:
MassFX for Blender 2.8 is finally here.
Since the first release for Blender 2.79, everything has been re-worked completely. The add-on now operates as a brush where you can switch between two modes: Drop & Paint:
Storing your items has never been this easy. You now have a collection manager. Where you can store a group of objects & switch between the collection you want to drop on the fly.
Many new features have been included in this release. Here are the list of features:
● New Physics Painter
● Particle based brush
● Simplified, User-friendly UI
● Options at hand, both brush & physics settings
You can find more information about the tool on Blender Market. I have also put together a video explaining the recent changes made to the add-on.
Happy Blending & Thanks for your support!


The joy of elderly people doing the Thriller dance
by David PescovitzEnjoy the funk of, er, 65+ years in this video of the annual Thriller dance at the Abbington Senior Living Mapleton center in Utah.
For me, this clip has a similar charm as David Greenberger's eternally amazing Duplex Planet interviews with elderly people.


Class $o.OQHelper
an observer object attached to detects changes in a target object or Array. These helpers are created internally when change tracking over an object/Array is activated.
- Defined in: objbind.js
| Constructor Attributes | Constructor Name and Description |
|---|---|
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$o.OQHelper(obj)
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Method Summary
| Method Attributes | Method Name and Description |
|---|---|
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bind(eventType, eventData, handler)
binds functions to events on target object (for multiple bindings, a map of functions can be used as argument)
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intercepts all functions that modify target Array contents
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Intercepts all properties in target object (adds setters and getters)
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interceptProperty(obj, property)
Intercepts a property on an object
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lookup()
lookups for undetected changes (eg: new properties, setting length Array property) and triggers change events accordingly
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override(name, func)
overrides a function from target object
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overrideProperty(property, setter, getter)
adds setter and getter to a property in target object
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prop(name, value)
sets or gets (if no 2nd arguments is provided) a property value on target object
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removes all added interceptors from target object (eg: property interceptors or Array function wrappers)
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trigger(eventType)
Triggers an event on the target object, aditional arguments are passed to subscribed event handlers
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unbind(eventType, handler)
Unbinds event handlers
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unoverride(name)
removes a function override from target object
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unoverrideProperty(property)
Removes getter and setter from an overriden property in target object
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Class Detail
$o.OQHelper(obj)
- Parameters:
- {Object|Array} obj
- target object or Array to track for changes
Method Detail
-
bind(eventType, eventData, handler)binds functions to events on target object (for multiple bindings, a map of functions can be used as argument)
- Parameters:
- {string} eventType
- {Object} eventData
- {function()} handler
-
interceptArrayModifiers()intercepts all functions that modify target Array contents
-
interceptProperties()Intercepts all properties in target object (adds setters and getters)
-
interceptProperty(obj, property)Intercepts a property on an object
- Parameters:
- {Object} obj
- {string} property
- name
-
lookup()lookups for undetected changes (eg: new properties, setting length Array property) and triggers change events accordingly
-
override(name, func)overrides a function from target object
- Parameters:
- {string} name
- {function()} func
- replacement function
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overrideProperty(property, setter, getter)adds setter and getter to a property in target object
- Parameters:
- {string} property
- name
- {function()} setter
- {function()} getter
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prop(name, value)sets or gets (if no 2nd arguments is provided) a property value on target object
- Parameters:
- {string} name
- property name
- {Object} value
- Returns:
- property value if not 2nd argument is provided
-
removeInterceptors()removes all added interceptors from target object (eg: property interceptors or Array function wrappers)
-
trigger(eventType)Triggers an event on the target object, aditional arguments are passed to subscribed event handlers
- Parameters:
- {string} eventType
-
unbind(eventType, handler)Unbinds event handlers
- Parameters:
- {Object} eventType
- {function()} handler Optional
-
unoverride(name)removes a function override from target object
- Parameters:
- {string} name
-
unoverrideProperty(property)Removes getter and setter from an overriden property in target object
- Parameters:
- {string} property
- name


This is the "replace next" dynamic page creation example, which never reaches the first/last application page.


This site has data from the current legislative session. If you're searching for something older, you can browse the {{ CITY_COUNCIL_NAME }} Legistar site .
We'd be happy to help you find what you're looking for - contact us!


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java.lang.Object com.hoodcomputing.natpmp.Message
public abstract class Message
The message class manages a message that is being sent to a NAT-PMP gateway. The class respects the back-off time defined in the NAT-PMP specification. Consumers of this class need to ensure that only one message is being sent at a time to remain compliant with the NAT-PMP specification. This class is thread-safe.
ExternalAddressRequestMessage
,
MapRequestMessage
| Method Summary | |
|---|---|
NatPmpException |
getResponseException()
Gets the excpetion associated with the response. |
ResultCode |
getResultCode()
Gets the result code. |
java.lang.Long |
getSecondsSinceEpoch()
Gets the seconds since epoch as received from the NAT-PMP gateway. |
| Methods inherited from class java.lang.Object |
|---|
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait |
| Method Detail |
|---|
public NatPmpException getResponseException()
NatPmpException
associated with the response.public ResultCode getResultCode() throws NatPmpException
NatPmpException
- Thrown when no response has been received or the
response parsing ran into some trouble.public java.lang.Long getSecondsSinceEpoch() throws NatPmpException
NatPmpException
- Thrown when no response has been received or the
response parsing ran into some trouble.
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@********************************************************* * Dashboard panel for Graphs * * panel that gives status of graph and allows you to * * use pivot browser to search graph * * NOT IMPLEMENTED * ********************************************************@


Birth of the Dragon
Birth of the Dragon is a movie starring Billy Magnussen, Yu Xia, and Philip Ng. Set against the backdrop of 1960s San Francisco, BIRTH OF THE DRAGON is a modern take on the classic movies that Bruce Lee was known for. It takes its...


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{% load static %}
User: {{cinfo.u_name}}
Class: {{cinfo.cl_name}}
Character Level: {{cinfo.pc_level}}
Character Race: {{cinfo.bg_race}}
Character Age: {{cinfo.bg_age}}
Character Alignment: {{cinfo.bg_alignment}}
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| {{winfo.wpn_name}} | {{winfo.wpn_range}} | {{winfo.wpn_damage}} | {{winfo.clwpn_prof}} |
| Spell | Spell Slot Level | Spell Range (ft) | Spell Cast Time | Spell Type | What is Rolled? |
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| {{spinfo.sp_name}} | {{spinfo.sp_slotLevel}} | {{spinfo.sp_range}} | {{spinfo.sp_castingtype}} | {{spinfo.sp_effect}} | {{spinfo.sp_die}} |


{% include "base/head.html" %}
UAVCAN is an open lightweight protocol designed for reliable intravehicular communication in aerospace and robotic applications over robust networks such as CAN bus.
It is created to address the challenge of deterministic on-board data exchange between systems and components of next-generation intelligent vehicles: manned and unmanned aircraft, spacecraft, robots, and cars.
UAVCAN is a standard open to everyone, and it will always remain this way. No licensing or approval of any kind is necessary for its implementation, distribution, or use.
First, read the official UAVCAN specification document and familiarize yourself with the regulated DSDL repository. If you have questions or feedback, bring them to the discussion forum.
Pick one of the free open source implementations (MIT licensed) for use in your application:
None of the implementations suit your needs? Write your own! UAVCAN is a very simple protocol; an experienced developer can easily create a custom implementation from scratch to address the unique needs of their application.
The open source tools will help you design, develop, and maintain your UAVCAN-based application:
The old version of the website is still available for historical reasons, but it will be taken down eventually. It contains an older, pre-release edition of the specification and documentation entries that are now obsolete.
{% set fallback_image = '/static/images/logo-square.svg' %} {% if forum_feed_entries %}Join the forum to start a new discussion. Also, feel free to participate in the weekly dev call.
{% endif %} {% if development_feed_entries %}|
{% if e.is_important %}{% endif %}
{{ e.text | safe }}
{% if e.is_important %}{% endif %}
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