// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR1A6
0x0 |
CMPR0A6
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR1A6 | RW | Counter/Timer A6 Compare Register 1. |
| 15:0 | CMPR0A6 | RW | Counter/Timer A6 Compare Register 0. |
| Instance 0 Address: | 0x400080C8 |
This register holds the compare limits for timer half B.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR1B6
0x0 |
CMPR0B6
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR1B6 | RW | Counter/Timer B6 Compare Register 1. |
| 15:0 | CMPR0B6 | RW | Counter/Timer B6 Compare Register 0. |
| Instance 0 Address: | 0x400080CC |
This register holds the control bit fields for both halves of timer 6.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTLINK6
0x0 |
RSVD
0x0 |
TMRB6POL
0x0 |
TMRB6CLR
0x0 |
TMRB6IE1
0x0 |
TMRB6IE0
0x0 |
TMRB6FN
0x0 |
TMRB6CLK
0x0 |
TMRB6EN
0x0 |
RSVD
0x0 |
TMRA6POL
0x0 |
TMRA6CLR
0x0 |
TMRA6IE1
0x0 |
TMRA6IE0
0x0 |
TMRA6FN
0x0 |
TMRA6CLK
0x0 |
TMRA6EN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTLINK6 | RW | Counter/Timer A6/B6 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A6/B6 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A6/B6 timers into a single 32-bit timer. |
| 30:29 | RSVD | RO | RESERVED |
| 28 | TMRB6POL | RW | Counter/Timer B6 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB6 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB6 pin is the inverse of the timer output. |
| 27 | TMRB6CLR | RW | Counter/Timer B6 Clear bit. RUN = 0x0 - Allow counter/timer B6 to run CLEAR = 0x1 - Holds counter/timer B6 at 0x0000. |
| 26 | TMRB6IE1 | RW | Counter/Timer B6 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B6 to generate an interrupt based on COMPR1. |
| 25 | TMRB6IE0 | RW | Counter/Timer B6 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B6 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B6 to generate an interrupt based on COMPR0 |
| 24:22 | TMRB6FN | RW | Counter/Timer B6 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B6, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B6, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B6, assert, count to CMPR1B6, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B6, assert, count to CMPR1B6, deassert, restart. SINGLEPATTERN = 0x4 - Single pattern. REPEATPATTERN = 0x5 - Repeated pattern. CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously. ALTPWN = 0x7 - Alternate PWM |
| 21:17 | TMRB6CLK | RW | Counter/Timer B6 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV128 = 0x9 - Clock source is XT / 128 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) XT_DIV4 = 0x10 - Clock source is XT / 4 XT_DIV8 = 0x11 - Clock source is XT / 8 XT_DIV32 = 0x12 - Clock source is XT / 32 RSVD = 0x13 - Clock source is Reserved. CTMRA6 = 0x14 - Clock source is CTIMERA6 OUT. CTMRA3 = 0x15 - Clock source is CTIMERA3 OUT. CTMRB3 = 0x16 - Clock source is CTIMERB3 OUT. CTMRA7 = 0x17 - Clock source is CTIMERA7 OUT. CTMRB7 = 0x18 - Clock source is CTIMERB7 OUT. CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT. CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT. CTMRB2 = 0x1B - Clock source is CTIMERB2 OUT. CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT. BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses. BUCKB = 0x1E - Clock source is Memory buck converter TON pulses. BUCKA = 0x1F - Clock source is CPU buck converter TON pulses. |
| 16 | TMRB6EN | RW | Counter/Timer B6 Enable bit. DIS = 0x0 - Counter/Timer B6 Disable. EN = 0x1 - Counter/Timer B6 Enable. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | TMRA6POL | RW | Counter/Timer A6 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA6 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA6 pin is the inverse of the timer output. |
| 11 | TMRA6CLR | RW | Counter/Timer A6 Clear bit. RUN = 0x0 - Allow counter/timer A6 to run CLEAR = 0x1 - Holds counter/timer A6 at 0x0000. |
| 10 | TMRA6IE1 | RW | Counter/Timer A6 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A6 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A6 to generate an interrupt based on COMPR1. |
| 9 | TMRA6IE0 | RW | Counter/Timer A6 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A6 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A6 to generate an interrupt based on COMPR0. |
| 8:6 | TMRA6FN | RW | Counter/Timer A6 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A6, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A6, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A6, assert, count to CMPR1A6, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A6, assert, count to CMPR1A6, deassert, restart. SINGLEPATTERN = 0x4 - Single pattern. REPEATPATTERN = 0x5 - Repeated pattern. CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously. ALTPWN = 0x7 - Alternate PWM |
| 5:1 | TMRA6CLK | RW | Counter/Timer A6 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV128 = 0x9 - Clock source is XT / 128 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) XT_DIV4 = 0x10 - Clock source is XT / 4 XT_DIV8 = 0x11 - Clock source is XT / 8 XT_DIV32 = 0x12 - Clock source is XT / 32 RSVD = 0x13 - Clock source is Reserved. CTMRB6 = 0x14 - Clock source is CTIMERB6 OUT. CTMRA3 = 0x15 - Clock source is CTIMERA3 OUT. CTMRB3 = 0x16 - Clock source is CTIMERB3 OUT. CTMRA7 = 0x17 - Clock source is CTIMERA7 OUT. CTMRB7 = 0x18 - Clock source is CTIMERB7 OUT. CTMRB0 = 0x19 - Clock source is CTIMERB0 OUT. CTMRB1 = 0x1A - Clock source is CTIMERB1 OUT. CTMRB2 = 0x1B - Clock source is CTIMERB2 OUT. CTMRB4 = 0x1C - Clock source is CTIMERB4 OUT. BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses. BUCKB = 0x1E - Clock source is Memory buck converter TON pulses. BUCKA = 0x1F - Clock source is CPU buck converter TON pulses. |
| 0 | TMRA6EN | RW | Counter/Timer A6 Enable bit. DIS = 0x0 - Counter/Timer A6 Disable. EN = 0x1 - Counter/Timer A6 Enable. |
| Instance 0 Address: | 0x400080D4 |
Enhanced compare limits for timer half A.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR3A6
0x0 |
CMPR2A6
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR3A6 | RW | Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A. |
| 15:0 | CMPR2A6 | RW | Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A. |
| Instance 0 Address: | 0x400080D8 |
Enhanced compare limits for timer half B.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR3B6
0x0 |
CMPR2B6
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR3B6 | RW | Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B. |
| 15:0 | CMPR2B6 | RW | Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B. |
| Instance 0 Address: | 0x400080DC |
Control bit fields for both halves of timer 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
TMRB6EN23
0x0 |
TMRB6POL23
0x0 |
TMRB6TINV
0x0 |
TMRB6NOSYNC
0x0 |
TMRB6TRIG
0x0 |
RSVD
0x0 |
TMRB6LMT
0x0 |
RSVD
0x0 |
TMRA6EN23
0x0 |
TMRA6POL23
0x0 |
TMRA6TINV
0x0 |
TMRA6NOSYNC
0x0 |
TMRA6TRIG
0x0 |
TMRA6LMT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30 | TMRB6EN23 | RW | Counter/Timer B6 Upper compare enable. DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. |
| 29 | TMRB6POL23 | RW | Upper output polarity NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. |
| 28 | TMRB6TINV | RW | Counter/Timer B6 Invert on trigger. DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger |
| 27 | TMRB6NOSYNC | RW | Source clock synchronization control. DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock |
| 26:23 | TMRB6TRIG | RW | Counter/Timer B6 Trigger Select. DIS = 0x0 - Trigger source is disabled. A6OUT = 0x1 - Trigger source is CTIMERA6 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A4OUT = 0x4 - Trigger source is CTIMERA4 OUT. B4OUT = 0x5 - Trigger source is CTIMERB4 OUT. A1OUT = 0x6 - Trigger source is CTIMERA1 OUT. B1OUT = 0x7 - Trigger source is CTIMERB1 OUT. B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2. A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2. A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2. B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2. A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge. A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge. B0OUT2DUAL = 0xE - Trigger source is CTIMERB0 OUT2, dual edge. A0OUT2DUAL = 0xF - Trigger source is CTIMERA0 OUT2, dual edge. |
| 22 | RSVD | RO | RESERVED |
| 21:16 | TMRB6LMT | RW | Counter/Timer B6 Pattern Limit Count. |
| 15 | RSVD | RO | RESERVED |
| 14 | TMRA6EN23 | RW | Counter/Timer A6 Upper compare enable. DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. |
| 13 | TMRA6POL23 | RW | Counter/Timer A6 Upper output polarity NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. |
| 12 | TMRA6TINV | RW | Counter/Timer A6 Invert on trigger. DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger |
| 11 | TMRA6NOSYNC | RW | Source clock synchronization control. DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock |
| 10:7 | TMRA6TRIG | RW | Counter/Timer A6 Trigger Select. DIS = 0x0 - Trigger source is disabled. B6OUT = 0x1 - Trigger source is CTIMERB6 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A5OUT = 0x4 - Trigger source is CTIMERA5 OUT. B5OUT = 0x5 - Trigger source is CTIMERB5 OUT. A1OUT = 0x6 - Trigger source is CTIMERA1 OUT. B1OUT = 0x7 - Trigger source is CTIMERB1 OUT. B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2. A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2. A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2. B2OUT2 = 0xB - Trigger source is CTIMERBb OUT2. A5OUT2DUAL = 0xC - Trigger source is CTIMERA5 OUT2, dual edge. A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge. B0OUT2DUAL = 0xE - Trigger source is CTIMERB0 OUT2, dual edge. A0OUT2DUAL = 0xF - Trigger source is CTIMERA0 OUT2, dual edge. |
| 6:0 | TMRA6LMT | RW | Counter/Timer A6 Pattern Limit Count. |
| Instance 0 Address: | 0x400080E0 |
Counter/Timer Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTTMRB7
0x0 |
CTTMRA7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CTTMRB7 | RO | Counter/Timer B7. |
| 15:0 | CTTMRA7 | RO | Counter/Timer A7. |
| Instance 0 Address: | 0x400080E4 |
This register holds the compare limits for timer half A.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR1A7
0x0 |
CMPR0A7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR1A7 | RW | Counter/Timer A7 Compare Register 1. |
| 15:0 | CMPR0A7 | RW | Counter/Timer A7 Compare Register 0. |
| Instance 0 Address: | 0x400080E8 |
This register holds the compare limits for timer half B.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR1B7
0x0 |
CMPR0B7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR1B7 | RW | Counter/Timer B3 Compare Register 1. |
| 15:0 | CMPR0B7 | RW | Counter/Timer B3 Compare Register 0. |
| Instance 0 Address: | 0x400080EC |
This register holds the control bit fields for both halves of timer 7.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTLINK7
0x0 |
RSVD
0x0 |
TMRB7POL
0x0 |
TMRB7CLR
0x0 |
TMRB7IE1
0x0 |
TMRB7IE0
0x0 |
TMRB7FN
0x0 |
TMRB7CLK
0x0 |
TMRB7EN
0x0 |
RSVD
0x0 |
TMRA7POL
0x0 |
TMRA7CLR
0x0 |
TMRA7IE1
0x0 |
TMRA7IE0
0x0 |
TMRA7FN
0x0 |
TMRA7CLK
0x0 |
TMRA7EN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTLINK7 | RW | Counter/Timer A7/B7 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A7/B7 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A7/B7 timers into a single 32-bit timer. |
| 30:29 | RSVD | RO | RESERVED |
| 28 | TMRB7POL | RW | Counter/Timer B7 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB7 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB7 pin is the inverse of the timer output. |
| 27 | TMRB7CLR | RW | Counter/Timer B7 Clear bit. RUN = 0x0 - Allow counter/timer B7 to run CLEAR = 0x1 - Holds counter/timer B7 at 0x0000. |
| 26 | TMRB7IE1 | RW | Counter/Timer B7 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B7 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B7 to generate an interrupt based on COMPR1. |
| 25 | TMRB7IE0 | RW | Counter/Timer B7 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B7 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B7 to generate an interrupt based on COMPR0 |
| 24:22 | TMRB7FN | RW | Counter/Timer B7 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B7, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B7, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B7, assert, count to CMPR1B7, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B7, assert, count to CMPR1B7, deassert, restart. SINGLEPATTERN = 0x4 - Single pattern. REPEATPATTERN = 0x5 - Repeated pattern. CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously. ALTPWN = 0x7 - Alternate PWM |
| 21:17 | TMRB7CLK | RW | Counter/Timer B7 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV128 = 0x9 - Clock source is XT / 128 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) XT_DIV4 = 0x10 - Clock source is XT / 4 XT_DIV8 = 0x11 - Clock source is XT / 8 XT_DIV32 = 0x12 - Clock source is XT / 32 RSVD = 0x13 - Clock source is Reserved. CTMRA7 = 0x14 - Clock source is CTIMERA7 OUT. CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT. CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT. CTMRA0 = 0x17 - Clock source is CTIMERA0 OUT. CTMRB0 = 0x18 - Clock source is CTIMERB0 OUT. CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT. CTMRB3 = 0x1A - Clock source is CTIMERB3 OUT. CTMRB4 = 0x1B - Clock source is CTIMERB4 OUT. CTMRB5 = 0x1C - Clock source is CTIMERB5 OUT. BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses. BUCKB = 0x1E - Clock source is Memory buck converter TON pulses. BUCKA = 0x1F - Clock source is CPU buck converter TON pulses. |
| 16 | TMRB7EN | RW | Counter/Timer B7 Enable bit. DIS = 0x0 - Counter/Timer B7 Disable. EN = 0x1 - Counter/Timer B7 Enable. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | TMRA7POL | RW | Counter/Timer A7 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA7 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA7 pin is the inverse of the timer output. |
| 11 | TMRA7CLR | RW | Counter/Timer A7 Clear bit. RUN = 0x0 - Allow counter/timer A7 to run CLEAR = 0x1 - Holds counter/timer A7 at 0x0000. |
| 10 | TMRA7IE1 | RW | Counter/Timer A7 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A7 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A7 to generate an interrupt based on COMPR1. |
| 9 | TMRA7IE0 | RW | Counter/Timer A7 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A7 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A7 to generate an interrupt based on COMPR0. |
| 8:6 | TMRA7FN | RW | Counter/Timer A7 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A7, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A7, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A7, assert, count to CMPR1A7, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A7, assert, count to CMPR1A7, deassert, restart. SINGLEPATTERN = 0x4 - Single pattern. REPEATPATTERN = 0x5 - Repeated pattern. CONTINUOUS = 0x6 - Continuous run (aka Free Run). Count continuously. ALTPWN = 0x7 - Alternate PWM |
| 5:1 | TMRA7CLK | RW | Counter/Timer A7 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4 HFRC_DIV16 = 0x2 - Clock source is HFRC / 16 HFRC_DIV256 = 0x3 - Clock source is HFRC / 256 HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV128 = 0x9 - Clock source is XT / 128 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only available when MCU is in active mode) XT_DIV4 = 0x10 - Clock source is XT / 4 XT_DIV8 = 0x11 - Clock source is XT / 8 XT_DIV32 = 0x12 - Clock source is XT / 32 RSVD = 0x13 - Clock source is Reserved. CTMRB7 = 0x14 - Clock source is CTIMERB7 OUT. CTMRA2 = 0x15 - Clock source is CTIMERA2 OUT. CTMRB2 = 0x16 - Clock source is CTIMERB2 OUT. CTMRA0 = 0x17 - Clock source is CTIMERA0 OUT. CTMRB0 = 0x18 - Clock source is CTIMERB0 OUT. CTMRB1 = 0x19 - Clock source is CTIMERB1 OUT. CTMRB3 = 0x1A - Clock source is CTIMERB3 OUT. CTMRB4 = 0x1B - Clock source is CTIMERB4 OUT. CTMRB5 = 0x1C - Clock source is CTIMERB5 OUT. BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses. BUCKB = 0x1E - Clock source is Memory buck converter TON pulses. BUCKA = 0x1F - Clock source is CPU buck converter TON pulses. |
| 0 | TMRA7EN | RW | Counter/Timer A7 Enable bit. DIS = 0x0 - Counter/Timer A7 Disable. EN = 0x1 - Counter/Timer A7 Enable. |
| Instance 0 Address: | 0x400080F4 |
Enhanced compare limits for timer half A.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR3A7
0x0 |
CMPR2A7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR3A7 | RW | Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A. |
| 15:0 | CMPR2A7 | RW | Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A. |
| Instance 0 Address: | 0x400080F8 |
Enhanced compare limits for timer half B.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPR3B7
0x0 |
CMPR2B7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CMPR3B7 | RW | Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B. |
| 15:0 | CMPR2B7 | RW | Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B. |
| Instance 0 Address: | 0x400080FC |
Control bit fields for both halves of timer 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
TMRB7EN23
0x0 |
TMRB7POL23
0x0 |
TMRB7TINV
0x0 |
TMRB7NOSYNC
0x0 |
TMRB7TRIG
0x0 |
RSVD
0x0 |
TMRB7LMT
0x0 |
RSVD
0x0 |
TMRA7EN23
0x0 |
TMRA7POL23
0x0 |
TMRA7TINV
0x0 |
TMRA7NOSYNC
0x0 |
TMRA7TRIG
0x0 |
TMRA7LMT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30 | TMRB7EN23 | RW | Counter/Timer B7 Upper compare enable. DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. |
| 29 | TMRB7POL23 | RW | Upper output polarity NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. |
| 28 | TMRB7TINV | RW | Counter/Timer B7 Invert on trigger. DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger |
| 27 | TMRB7NOSYNC | RW | Source clock synchronization control. DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock |
| 26:23 | TMRB7TRIG | RW | Counter/Timer B7 Trigger Select. DIS = 0x0 - Trigger source is disabled. A7OUT = 0x1 - Trigger source is CTIMERA7 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A5OUT = 0x4 - Trigger source is CTIMERA5 OUT. B5OUT = 0x5 - Trigger source is CTIMERB5 OUT. A2OUT = 0x6 - Trigger source is CTIMERA2 OUT. B2OUT = 0x7 - Trigger source is CTIMERB2 OUT. B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2. A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2. A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2. B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2. A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge. A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge. B1OUT2DUAL = 0xE - Trigger source is CTIMERB1 OUT2, dual edge. A1OUT2DUAL = 0xF - Trigger source is CTIMERA1 OUT2, dual edge. |
| 22 | RSVD | RO | RESERVED |
| 21:16 | TMRB7LMT | RW | Counter/Timer B7 Pattern Limit Count. |
| 15 | RSVD | RO | RESERVED |
| 14 | TMRA7EN23 | RW | Counter/Timer A7 Upper compare enable. DIS = 0x1 - Disable enhanced functions. EN = 0x0 - Enable enhanced functions. |
| 13 | TMRA7POL23 | RW | Counter/Timer A7 Upper output polarity NORM = 0x0 - Upper output normal polarity INV = 0x1 - Upper output inverted polarity. |
| 12 | TMRA7TINV | RW | Counter/Timer A7 Invert on trigger. DIS = 0x0 - Disable invert on trigger EN = 0x1 - Enable invert on trigger |
| 11 | TMRA7NOSYNC | RW | Source clock synchronization control. DIS = 0x0 - Synchronization on source clock NOSYNC = 0x1 - No synchronization on source clock |
| 10:7 | TMRA7TRIG | RW | Counter/Timer A7 Trigger Select. DIS = 0x0 - Trigger source is disabled. B7OUT = 0x1 - Trigger source is CTIMERB7 OUT. B3OUT = 0x2 - Trigger source is CTIMERB3 OUT. A3OUT = 0x3 - Trigger source is CTIMERA3 OUT. A1OUT = 0x4 - Trigger source is CTIMERA1 OUT. B1OUT = 0x5 - Trigger source is CTIMERB1 OUT. A4OUT = 0x6 - Trigger source is CTIMERA4 OUT. B4OUT = 0x7 - Trigger source is CTIMERB4 OUT. B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2. A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2. A2OUT2 = 0xA - Trigger source is CTIMERA2 OUT2. B2OUT2 = 0xB - Trigger source is CTIMERB2 OUT2. A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge. A5OUT2DUAL = 0xD - Trigger source is CTIMERA5 OUT2, dual edge. B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge. A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge. |
| 6:0 | TMRA7LMT | RW | Counter/Timer A7 Pattern Limit Count. |
| Instance 0 Address: | 0x40008100 |
Alternate enables for all CTIMERs.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ENB7
0x1 |
ENA7
0x1 |
ENB6
0x1 |
ENA6
0x1 |
ENB5
0x1 |
ENA5
0x1 |
ENB4
0x1 |
ENA4
0x1 |
ENB3
0x1 |
ENA3
0x1 |
ENB2
0x1 |
ENA2
0x1 |
ENB1
0x1 |
ENA1
0x1 |
ENB0
0x1 |
ENA0
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | RESERVED |
| 15 | ENB7 | RW | Alternate enable for B7. LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 14 | ENA7 | RW | Alternate enable for A7 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 13 | ENB6 | RW | Alternate enable for B6 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 12 | ENA6 | RW | Alternate enable for A6 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 11 | ENB5 | RW | Alternate enable for B5 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 10 | ENA5 | RW | Alternate enable for A5 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 9 | ENB4 | RW | Alternate enable for B4 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 8 | ENA4 | RW | Alternate enable for A4 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 7 | ENB3 | RW | Alternate enable for B3. LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 6 | ENA3 | RW | Alternate enable for A3 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 5 | ENB2 | RW | Alternate enable for B2 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 4 | ENA2 | RW | Alternate enable for A2 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 3 | ENB1 | RW | Alternate enable for B1 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 2 | ENA1 | RW | Alternate enable for A1 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 1 | ENB0 | RW | Alternate enable for B0 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| 0 | ENA0 | RW | Alternate enable for A0 LCO = 0x1 - Use local enable. DIS = 0x0 - Disable CTIMER. |
| Instance 0 Address: | 0x40008104 |
Pad output configuration 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CFG9
0x2 |
CFG8
0x2 |
CFG7
0x2 |
CFG6
0x2 |
CFG5
0x2 |
RSVD
0x0 |
CFG4
0x2 |
CFG3
0x1 |
CFG2
0x2 |
CFG1
0x2 |
CFG0
0x2 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30:28 | CFG9 | RW | Pad output 9 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT = 0x5 - Output is B0OUT. A4OUT = 0x4 - Output is A4OUT. A2OUT = 0x3 - Output is A2OUT. A2OUT2 = 0x2 - Output is A2OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 27:25 | CFG8 | RW | Pad output 8 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B6OUT = 0x5 - Output is B6OUT. A4OUT2 = 0x4 - Output is A4OUT2. A3OUT2 = 0x3 - Output is A3OUT. A2OUT = 0x2 - Output is A2OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 24:22 | CFG7 | RW | Pad output 7 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A7OUT = 0x5 - Output is A7OUT. B5OUT = 0x4 - Output is B5OUT. B1OUT = 0x3 - Output is B1OUT. B1OUT2 = 0x2 - Output is B1OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 21:19 | CFG6 | RW | Pad output 6 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B7OUT = 0x5 - Output is B7OUT. B5OUT2 = 0x4 - Output is B5OUT2. A1OUT = 0x3 - Output is A1OUT. B1OUT = 0x2 - Output is B1OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 18:16 | CFG5 | RW | Pad output 5 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A7OUT = 0x5 - Output is A7OUT. B6OUT = 0x4 - Output is A5OUT. A1OUT = 0x3 - Output is A1OUT. A1OUT2 = 0x2 - Output is A1OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 15 | RSVD | RO | RESERVED |
| 14:12 | CFG4 | RW | Pad output 4 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B5OUT = 0x5 - Output is B5OUT. A5OUT2 = 0x4 - Output is A5OUT2. A2OUT2 = 0x3 - Output is A2OUT2. A1OUT = 0x2 - Output is A1OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 11:9 | CFG3 | RW | Pad output 3 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A6OUT = 0x5 - Output is A6OUT. A1OUT = 0x4 - Output is A1OUT. B0OUT = 0x3 - Output is B0OUT. B0OUT2 = 0x2 - Output is B0OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 8:6 | CFG2 | RW | Pad output 2 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A7OUT = 0x5 - Output is A7OUT. B6OUT2 = 0x4 - Output is B6OUT2. B1OUT2 = 0x3 - Output is B1OUT2. B0OUT = 0x2 - Output is B0OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 5:3 | CFG1 | RW | Pad output 1 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B7OUT2 = 0x5 - Output is B7OUT2. A5OUT = 0x4 - Output is A5OUT. A0OUT = 0x3 - Output is A0OUT. A0OUT2 = 0x2 - Output is A0OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 2:0 | CFG0 | RW | Pad output 0 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A6OUT = 0x5 - Output is A6OUT. A5OUT2 = 0x4 - Output is A5OUT2. B2OUT2 = 0x3 - Output is B2OUT2. A0OUT = 0x2 - Output is A0OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| Instance 0 Address: | 0x40008108 |
Pad output configuration 1.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CFG19
0x2 |
CFG18
0x2 |
CFG17
0x2 |
CFG16
0x2 |
CFG15
0x2 |
RSVD
0x0 |
CFG14
0x2 |
CFG13
0x1 |
CFG12
0x2 |
CFG11
0x2 |
CFG10
0x2 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30:28 | CFG19 | RW | Pad output 19 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B1OUT2 = 0x5 - Output is B1OUT2. B4OUT = 0x4 - Output is B4OUT. A2OUT = 0x3 - Output is A2OUT. B4OUT2 = 0x2 - Output is B4OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 27:25 | CFG18 | RW | Pad output 18 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A3OUT2 = 0x5 - Output is A3OUT2. A0OUT = 0x4 - Output is A0OUT. B0OUT = 0x3 - Output is B0OUT. B4OUT = 0x2 - Output is B4OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 24:22 | CFG17 | RW | Pad output 17 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A1OUT2 = 0x5 - Output is A1OUT2. A4OUT = 0x4 - Output is A4OUT. B7OUT = 0x3 - Output is B7OUT. A4OUT2 = 0x2 - Output is A4OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 21:19 | CFG16 | RW | Pad output 16 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B3OUT2 = 0x5 - Output is B3OUT2. A0OUT2 = 0x4 - Output is A0OUT2. A0OUT = 0x3 - Output is A0OUT. A4OUT = 0x2 - Output is A4OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 18:16 | CFG15 | RW | Pad output 15 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A4OUT2 = 0x5 - Output is A4OUT2. A7OUT = 0x4 - Output is A7OUT. B3OUT = 0x3 - Output is B3OUT. B3OUT2 = 0x2 - Output is B3OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 15 | RSVD | RO | RESERVED |
| 14:12 | CFG14 | RW | Pad output 14 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A7OUT = 0x5 - Output is A7OUT. B7OUT2 = 0x4 - Output is B7OUT2. B1OUT = 0x3 - Output is B1OUT. B3OUT = 0x2 - Output is B3OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 11:9 | CFG13 | RW | Pad output 13 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B4OUT2 = 0x5 - Output is B4OUT2. A6OUT = 0x4 - Output is A6OUT. A3OUT = 0x3 - Output is A3OUT. A3OUT2 = 0x2 - Output is A3OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 8:6 | CFG12 | RW | Pad output 12 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B6OUT2 = 0x5 - Output is B6OUT2. B0OUT2 = 0x4 - Output is B0OUT2. B1OUT = 0x3 - Output is B1OUT. A3OUT = 0x2 - Output is A3OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 5:3 | CFG11 | RW | Pad output 11 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B5OUT2 = 0x5 - Output is B5OUT2. B4OUT = 0x4 - Output is B4OUT. B2OUT = 0x3 - Output is B2OUT. B2OUT2 = 0x2 - Output is B2OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 2:0 | CFG10 | RW | Pad output 10 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A6OUT = 0x5 - Output is A6OUT. B4OUT2 = 0x4 - Output is B4OUT2. B3OUT2 = 0x3 - Output is B3OUT2. B2OUT = 0x2 - Output is B2OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| Instance 0 Address: | 0x4000810C |
Pad output configuration 2.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CFG29
0x2 |
CFG28
0x2 |
CFG27
0x2 |
CFG26
0x2 |
CFG25
0x2 |
RSVD
0x0 |
CFG24
0x2 |
CFG23
0x1 |
CFG22
0x2 |
CFG21
0x2 |
CFG20
0x2 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30:28 | CFG29 | RW | Pad output 29 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A3OUT2 = 0x5 - Output is A3OUT2. A7OUT = 0x4 - Output is A7OUT. A1OUT = 0x3 - Output is A1OUT. B5OUT2 = 0x2 - Output is B5OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 27:25 | CFG28 | RW | Pad output 28 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT2 = 0x5 - Output is B0OUT2. A5OUT2 = 0x4 - Output is A5OUT2. A3OUT = 0x3 - Output is A3OUT. A7OUT = 0x2 - Output is A7OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 24:22 | CFG27 | RW | Pad output 27 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B2OUT2 = 0x5 - Output is B2OUT2. B6OUT = 0x4 - Output is B6OUT. A1OUT = 0x3 - Output is A1OUT. B6OUT2 = 0x2 - Output is B6OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 21:19 | CFG26 | RW | Pad output 26 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A1OUT2 = 0x5 - Output is A1OUT2. A5OUT = 0x4 - Output is A5OUT. B2OUT = 0x3 - Output is B2OUT. B6OUT = 0x2 - Output is B6OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 18:16 | CFG25 | RW | Pad output 25 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A2OUT2 = 0x5 - Output is A2OUT2. A6OUT = 0x4 - Output is A6OUT. B2OUT = 0x3 - Output is B2OUT. B4OUT2 = 0x2 - Output is B4OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 15 | RSVD | RO | RESERVED |
| 14:12 | CFG24 | RW | Pad output 24 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B1OUT2 = 0x5 - Output is B1OUT2. A1OUT = 0x4 - Output is A1OUT. A2OUT = 0x3 - Output is A2OUT. A6OUT = 0x2 - Output is A6OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 11:9 | CFG23 | RW | Pad output 23 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B0OUT2 = 0x5 - Output is B0OUT2. A5OUT = 0x4 - Output is A5OUT. A7OUT = 0x3 - Output is A7OUT. B5OUT2 = 0x2 - Output is B5OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 8:6 | CFG22 | RW | Pad output 22 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A2OUT2 = 0x5 - Output is A2OUT2. A1OUT = 0x4 - Output is A1OUT. A6OUT = 0x3 - Output is A6OUT. B5OUT = 0x2 - Output is B5OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 5:3 | CFG21 | RW | Pad output 21 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A0OUT2 = 0x5 - Output is A0OUT2. B5OUT = 0x4 - Output is B5OUT. A1OUT = 0x3 - Output is A1OUT. A5OUT2 = 0x2 - Output is A5OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 2:0 | CFG20 | RW | Pad output 20 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B2OUT2 = 0x5 - Output is B2OUT2. A1OUT2 = 0x4 - Output is A1OUT2. A1OUT = 0x3 - Output is A1OUT. A5OUT = 0x2 - Output is A5OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| Instance 0 Address: | 0x40008114 |
Pad output configuration 3.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CFG31
0x2 |
CFG30
0x2 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:6 | RSVD | RO | RESERVED |
| 5:3 | CFG31 | RW | Pad output 31 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. B3OUT2 = 0x5 - Output is B3OUT2. B7OUT = 0x4 - Output is B7OUT. A6OUT = 0x3 - Output is A6OUT. B7OUT2 = 0x2 - Output is B7OUT2 ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| 2:0 | CFG30 | RW | Pad output 30 configuration A7OUT2 = 0x7 - Output is A7OUT2. A6OUT2 = 0x6 - Output is A6OUT2. A0OUT2 = 0x5 - Output is A0OUT2. A4OUT2 = 0x4 - Output is A4OUT2. B3OUT = 0x3 - Output is B3OUT. B7OUT = 0x2 - Output is B7OUT ONE = 0x1 - Force output to 1. ZERO = 0x0 - Force output to 0 |
| Instance 0 Address: | 0x40008118 |
Pad input configuration.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CFGB7
0x0 |
CFGA7
0x0 |
CFGB6
0x0 |
CFGA6
0x0 |
CFGB5
0x0 |
CFGA5
0x0 |
CFGB4
0x0 |
CFGA4
0x0 |
CFGB3
0x0 |
CFGA3
0x0 |
CFGB2
0x0 |
CFGA2
0x0 |
CFGB1
0x0 |
CFGA1
0x0 |
CFGB0
0x0 |
CFGA0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | RESERVED |
| 15 | CFGB7 | RW | CTIMER B7 input configuration CT31 = 0x1 - Input is CT31 CT30 = 0x0 - Input is CT30 |
| 14 | CFGA7 | RW | CTIMER A7 input configuration CT29 = 0x1 - Input is CT29 CT28 = 0x0 - Input is CT28 |
| 13 | CFGB6 | RW | CTIMER B6 input configuration CT27 = 0x1 - Input is CT27 CT26 = 0x0 - Input is CT26 |
| 12 | CFGA6 | RW | CTIMER A6 input configuration CT25 = 0x1 - Input is CT25 CT24 = 0x0 - Input is CT24 |
| 11 | CFGB5 | RW | CTIMER B5 input configuration CT23 = 0x1 - Input is CT23 CT22 = 0x0 - Input is CT22 |
| 10 | CFGA5 | RW | CTIMER A5 input configuration CT21 = 0x1 - Input is CT21 CT20 = 0x0 - Input is CT20 |
| 9 | CFGB4 | RW | CTIMER B4 input configuration CT19 = 0x1 - Input is CT19 CT18 = 0x0 - Input is CT18 |
| 8 | CFGA4 | RW | CTIMER A4 input configuration CT17 = 0x1 - Input is CT17 CT16 = 0x0 - Input is CT16 |
| 7 | CFGB3 | RW | CTIMER B3 input configuration CT15 = 0x1 - Input is CT15 CT14 = 0x0 - Input is CT14 |
| 6 | CFGA3 | RW | CTIMER A3 input configuration CT13 = 0x1 - Input is CT13 CT12 = 0x0 - Input is CT12 |
| 5 | CFGB2 | RW | CTIMER B2 input configuration CT11 = 0x1 - Input is CT11 CT10 = 0x0 - Input is CT10 |
| 4 | CFGA2 | RW | CTIMER A2 input configuration CT9 = 0x1 - Input is CT9 CT8 = 0x0 - Input is CT8 |
| 3 | CFGB1 | RW | CTIMER B1 input configuration CT7 = 0x1 - Input is CT7 CT6 = 0x0 - Input is CT6 |
| 2 | CFGA1 | RW | CTIMER A1 input configuration CT5 = 0x1 - Input is CT5 CT4 = 0x0 - Input is CT4 |
| 1 | CFGB0 | RW | CTIMER B0 input configuration CT3 = 0x1 - Input is CT3 CT2 = 0x0 - Input is CT2 |
| 0 | CFGA0 | RW | CTIMER A0 input configuration CT1 = 0x1 - Input is CT1 CT0 = 0x0 - Input is CT0 |
| Instance 0 Address: | 0x40008140 |
The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FREEZE
0x1 |
CLEAR
0x0 |
RSVD
0x0 |
COMPARE_H_EN
0x0 |
COMPARE_G_EN
0x0 |
COMPARE_F_EN
0x0 |
COMPARE_E_EN
0x0 |
COMPARE_D_EN
0x0 |
COMPARE_C_EN
0x0 |
COMPARE_B_EN
0x0 |
COMPARE_A_EN
0x0 |
RSVD
0x0 |
CLKSEL
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | FREEZE | RW | Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume. THAW = 0x0 - Let the COUNTER register run on its input clock. FREEZE = 0x1 - Stop the COUNTER register for loading. |
| 30 | CLEAR | RW | Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running. RUN = 0x0 - Let the COUNTER register run on its input clock. CLEAR = 0x1 - Stop the COUNTER register for loading. |
| 29:16 | RSVD | RO | RESERVED. |
| 15 | COMPARE_H_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare H disabled. ENABLE = 0x1 - Compare H enabled. |
| 14 | COMPARE_G_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare G disabled. ENABLE = 0x1 - Compare G enabled. |
| 13 | COMPARE_F_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare F disabled. ENABLE = 0x1 - Compare F enabled. |
| 12 | COMPARE_E_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare E disabled. ENABLE = 0x1 - Compare E enabled. |
| 11 | COMPARE_D_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare D disabled. ENABLE = 0x1 - Compare D enabled. |
| 10 | COMPARE_C_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare C disabled. ENABLE = 0x1 - Compare C enabled. |
| 9 | COMPARE_B_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare B disabled. ENABLE = 0x1 - Compare B enabled. |
| 8 | COMPARE_A_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare A disabled. ENABLE = 0x1 - Compare A enabled. |
| 7:4 | RSVD | RO | RESERVED. |
| 3:0 | CLKSEL | RW | Selects an appropriate clock source and divider to use for the System Timer clock. NOCLK = 0x0 - No clock enabled. HFRC_DIV16 = 0x1 - 3MHz from the HFRC clock divider. HFRC_DIV256 = 0x2 - 187.5KHz from the HFRC clock divider. XTAL_DIV1 = 0x3 - 32768Hz from the crystal oscillator. XTAL_DIV2 = 0x4 - 16384Hz from the crystal oscillator. XTAL_DIV32 = 0x5 - 1024Hz from the crystal oscillator. LFRC_DIV1 = 0x6 - Approximately 1KHz from the LFRC oscillator (uncalibrated). CTIMER0A = 0x7 - Use CTIMER 0 section A as a prescaler for the clock source. CTIMER0B = 0x8 - Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source. |
| Instance 0 Address: | 0x40008144 |
The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is this counter value that is compared against the various compare registers. This register cannot be written, but can be cleared to 0 for a deterministic value. Use the FREEZE bit will stop this counter from incrementing.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| STTMR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | STTMR | RO | Value of the 32-bit counter as it ticks over. |
| Instance 0 Address: | 0x40008148 |
The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source, enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control individual capture registers atomically.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| RSVD
0x0 |
CAPTURE3
0x0 |
CAPTURE2
0x0 |
CAPTURE1
0x0 |
CAPTURE0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:4 | RSVD | RO | RESERVED. |
| 3 | CAPTURE3 | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled. |
| 2 | CAPTURE2 | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled. |
| 1 | CAPTURE1 | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled. |
| 0 | CAPTURE0 | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled. |
| Instance 0 Address: | 0x40008150 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCMPR0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR0 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x40008154 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCMPR1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR1 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x40008158 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SCMPR2
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR2 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x4000815C |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCMPR3
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR3 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x40008160 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SCMPR4
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR4 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x40008164 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCMPR5
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR5 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x40008168 |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCMPR6
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR6 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x4000816C |
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SCMPR7
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCMPR7 | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register. |
| Instance 0 Address: | 0x400081E0 |
The STIMER capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted. This register holds a time stamp for the event.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SCAPT0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCAPT0 | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. |
| Instance 0 Address: | 0x400081E4 |
The STIMER capture Register B grabs the VALUE in the COUNTER register whenever capture condition (event) B is asserted. This register holds a time stamp for the event.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCAPT1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCAPT1 | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. |
| Instance 0 Address: | 0x400081E8 |
The STIMER capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted. This register holds a time stamp for the event.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| SCAPT2
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCAPT2 | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. |
| Instance 0 Address: | 0x400081EC |
The STIMER capture Register D grabs the VALUE in the COUNTER register whenever capture condition (event) D is asserted. This register holds a time stamp for the event.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SCAPT3
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SCAPT3 | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. |
| Instance 0 Address: | 0x400081F0 |
The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SNVR0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SNVR0 | RW | Value of the 32-bit counter as it ticks over. |
| Instance 0 Address: | 0x400081F4 |
The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SNVR1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SNVR1 | RW | Value of the 32-bit counter as it ticks over. |
| Instance 0 Address: | 0x400081F8 |
The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SNVR2
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SNVR2 | RW | Value of the 32-bit counter as it ticks over. |
| Instance 0 Address: | 0x400081FC |
The NVRAM_D Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SNVR3
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | SNVR3 | RW | Value of the 32-bit counter as it ticks over. |
| Instance 0 Address: | 0x40008200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTMRB7C1INT
0x0 |
CTMRA7C1INT
0x0 |
CTMRB6C1INT
0x0 |
CTMRA6C1INT
0x0 |
CTMRB5C1INT
0x0 |
CTMRA5C1INT
0x0 |
CTMRB4C1INT
0x0 |
CTMRA4C1INT
0x0 |
CTMRB3C1INT
0x0 |
CTMRA3C1INT
0x0 |
CTMRB2C1INT
0x0 |
CTMRA2C1INT
0x0 |
CTMRB1C1INT
0x0 |
CTMRA1C1INT
0x0 |
CTMRB0C1INT
0x0 |
CTMRA0C1INT
0x0 |
CTMRB7C0INT
0x0 |
CTMRA7C0INT
0x0 |
CTMRB6C0INT
0x0 |
CTMRA6C0INT
0x0 |
CTMRB5C0INT
0x0 |
CTMRA5C0INT
0x0 |
CTMRB4C0INT
0x0 |
CTMRA4C0INT
0x0 |
CTMRB3C0INT
0x0 |
CTMRA3C0INT
0x0 |
CTMRB2C0INT
0x0 |
CTMRA2C0INT
0x0 |
CTMRB1C0INT
0x0 |
CTMRA1C0INT
0x0 |
CTMRB0C0INT
0x0 |
CTMRA0C0INT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTMRB7C1INT | RW | Counter/Timer B7 interrupt based on COMPR1. |
| 30 | CTMRA7C1INT | RW | Counter/Timer A7 interrupt based on COMPR1. |
| 29 | CTMRB6C1INT | RW | Counter/Timer B6 interrupt based on COMPR1. |
| 28 | CTMRA6C1INT | RW | Counter/Timer A6 interrupt based on COMPR1. |
| 27 | CTMRB5C1INT | RW | Counter/Timer B5 interrupt based on COMPR1. |
| 26 | CTMRA5C1INT | RW | Counter/Timer A5 interrupt based on COMPR1. |
| 25 | CTMRB4C1INT | RW | Counter/Timer B4 interrupt based on COMPR1. |
| 24 | CTMRA4C1INT | RW | Counter/Timer A4 interrupt based on COMPR1. |
| 23 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1. |
| 22 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1. |
| 21 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1. |
| 20 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1. |
| 19 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1. |
| 18 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1. |
| 17 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1. |
| 16 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1. |
| 15 | CTMRB7C0INT | RW | Counter/Timer B7 interrupt based on COMPR0. |
| 14 | CTMRA7C0INT | RW | Counter/Timer A7 interrupt based on COMPR0. |
| 13 | CTMRB6C0INT | RW | Counter/Timer B6 interrupt based on COMPR0. |
| 12 | CTMRA6C0INT | RW | Counter/Timer A6 interrupt based on COMPR0. |
| 11 | CTMRB5C0INT | RW | Counter/Timer B5 interrupt based on COMPR0. |
| 10 | CTMRA5C0INT | RW | Counter/Timer A5 interrupt based on COMPR0. |
| 9 | CTMRB4C0INT | RW | Counter/Timer B4 interrupt based on COMPR0. |
| 8 | CTMRA4C0INT | RW | Counter/Timer A4 interrupt based on COMPR0. |
| 7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0. |
| 6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0. |
| 5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0. |
| 4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0. |
| 3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0. |
| 2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0. |
| 1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0. |
| 0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0. |
| Instance 0 Address: | 0x40008204 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTMRB7C1INT
0x0 |
CTMRA7C1INT
0x0 |
CTMRB6C1INT
0x0 |
CTMRA6C1INT
0x0 |
CTMRB5C1INT
0x0 |
CTMRA5C1INT
0x0 |
CTMRB4C1INT
0x0 |
CTMRA4C1INT
0x0 |
CTMRB3C1INT
0x0 |
CTMRA3C1INT
0x0 |
CTMRB2C1INT
0x0 |
CTMRA2C1INT
0x0 |
CTMRB1C1INT
0x0 |
CTMRA1C1INT
0x0 |
CTMRB0C1INT
0x0 |
CTMRA0C1INT
0x0 |
CTMRB7C0INT
0x0 |
CTMRA7C0INT
0x0 |
CTMRB6C0INT
0x0 |
CTMRA6C0INT
0x0 |
CTMRB5C0INT
0x0 |
CTMRA5C0INT
0x0 |
CTMRB4C0INT
0x0 |
CTMRA4C0INT
0x0 |
CTMRB3C0INT
0x0 |
CTMRA3C0INT
0x0 |
CTMRB2C0INT
0x0 |
CTMRA2C0INT
0x0 |
CTMRB1C0INT
0x0 |
CTMRA1C0INT
0x0 |
CTMRB0C0INT
0x0 |
CTMRA0C0INT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTMRB7C1INT | RW | Counter/Timer B7 interrupt based on COMPR1. |
| 30 | CTMRA7C1INT | RW | Counter/Timer A7 interrupt based on COMPR1. |
| 29 | CTMRB6C1INT | RW | Counter/Timer B6 interrupt based on COMPR1. |
| 28 | CTMRA6C1INT | RW | Counter/Timer A6 interrupt based on COMPR1. |
| 27 | CTMRB5C1INT | RW | Counter/Timer B5 interrupt based on COMPR1. |
| 26 | CTMRA5C1INT | RW | Counter/Timer A5 interrupt based on COMPR1. |
| 25 | CTMRB4C1INT | RW | Counter/Timer B4 interrupt based on COMPR1. |
| 24 | CTMRA4C1INT | RW | Counter/Timer A4 interrupt based on COMPR1. |
| 23 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1. |
| 22 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1. |
| 21 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1. |
| 20 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1. |
| 19 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1. |
| 18 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1. |
| 17 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1. |
| 16 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1. |
| 15 | CTMRB7C0INT | RW | Counter/Timer B7 interrupt based on COMPR0. |
| 14 | CTMRA7C0INT | RW | Counter/Timer A7 interrupt based on COMPR0. |
| 13 | CTMRB6C0INT | RW | Counter/Timer B6 interrupt based on COMPR0. |
| 12 | CTMRA6C0INT | RW | Counter/Timer A6 interrupt based on COMPR0. |
| 11 | CTMRB5C0INT | RW | Counter/Timer B5 interrupt based on COMPR0. |
| 10 | CTMRA5C0INT | RW | Counter/Timer A5 interrupt based on COMPR0. |
| 9 | CTMRB4C0INT | RW | Counter/Timer B4 interrupt based on COMPR0. |
| 8 | CTMRA4C0INT | RW | Counter/Timer A4 interrupt based on COMPR0. |
| 7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0. |
| 6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0. |
| 5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0. |
| 4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0. |
| 3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0. |
| 2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0. |
| 1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0. |
| 0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0. |
| Instance 0 Address: | 0x40008208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTMRB7C1INT
0x0 |
CTMRA7C1INT
0x0 |
CTMRB6C1INT
0x0 |
CTMRA6C1INT
0x0 |
CTMRB5C1INT
0x0 |
CTMRA5C1INT
0x0 |
CTMRB4C1INT
0x0 |
CTMRA4C1INT
0x0 |
CTMRB3C1INT
0x0 |
CTMRA3C1INT
0x0 |
CTMRB2C1INT
0x0 |
CTMRA2C1INT
0x0 |
CTMRB1C1INT
0x0 |
CTMRA1C1INT
0x0 |
CTMRB0C1INT
0x0 |
CTMRA0C1INT
0x0 |
CTMRB7C0INT
0x0 |
CTMRA7C0INT
0x0 |
CTMRB6C0INT
0x0 |
CTMRA6C0INT
0x0 |
CTMRB5C0INT
0x0 |
CTMRA5C0INT
0x0 |
CTMRB4C0INT
0x0 |
CTMRA4C0INT
0x0 |
CTMRB3C0INT
0x0 |
CTMRA3C0INT
0x0 |
CTMRB2C0INT
0x0 |
CTMRA2C0INT
0x0 |
CTMRB1C0INT
0x0 |
CTMRA1C0INT
0x0 |
CTMRB0C0INT
0x0 |
CTMRA0C0INT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTMRB7C1INT | RW | Counter/Timer B7 interrupt based on COMPR1. |
| 30 | CTMRA7C1INT | RW | Counter/Timer A7 interrupt based on COMPR1. |
| 29 | CTMRB6C1INT | RW | Counter/Timer B6 interrupt based on COMPR1. |
| 28 | CTMRA6C1INT | RW | Counter/Timer A6 interrupt based on COMPR1. |
| 27 | CTMRB5C1INT | RW | Counter/Timer B5 interrupt based on COMPR1. |
| 26 | CTMRA5C1INT | RW | Counter/Timer A5 interrupt based on COMPR1. |
| 25 | CTMRB4C1INT | RW | Counter/Timer B4 interrupt based on COMPR1. |
| 24 | CTMRA4C1INT | RW | Counter/Timer A4 interrupt based on COMPR1. |
| 23 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1. |
| 22 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1. |
| 21 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1. |
| 20 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1. |
| 19 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1. |
| 18 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1. |
| 17 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1. |
| 16 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1. |
| 15 | CTMRB7C0INT | RW | Counter/Timer B7 interrupt based on COMPR0. |
| 14 | CTMRA7C0INT | RW | Counter/Timer A7 interrupt based on COMPR0. |
| 13 | CTMRB6C0INT | RW | Counter/Timer B6 interrupt based on COMPR0. |
| 12 | CTMRA6C0INT | RW | Counter/Timer A6 interrupt based on COMPR0. |
| 11 | CTMRB5C0INT | RW | Counter/Timer B5 interrupt based on COMPR0. |
| 10 | CTMRA5C0INT | RW | Counter/Timer A5 interrupt based on COMPR0. |
| 9 | CTMRB4C0INT | RW | Counter/Timer B4 interrupt based on COMPR0. |
| 8 | CTMRA4C0INT | RW | Counter/Timer A4 interrupt based on COMPR0. |
| 7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0. |
| 6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0. |
| 5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0. |
| 4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0. |
| 3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0. |
| 2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0. |
| 1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0. |
| 0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0. |
| Instance 0 Address: | 0x4000820C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CTMRB7C1INT
0x0 |
CTMRA7C1INT
0x0 |
CTMRB6C1INT
0x0 |
CTMRA6C1INT
0x0 |
CTMRB5C1INT
0x0 |
CTMRA5C1INT
0x0 |
CTMRB4C1INT
0x0 |
CTMRA4C1INT
0x0 |
CTMRB3C1INT
0x0 |
CTMRA3C1INT
0x0 |
CTMRB2C1INT
0x0 |
CTMRA2C1INT
0x0 |
CTMRB1C1INT
0x0 |
CTMRA1C1INT
0x0 |
CTMRB0C1INT
0x0 |
CTMRA0C1INT
0x0 |
CTMRB7C0INT
0x0 |
CTMRA7C0INT
0x0 |
CTMRB6C0INT
0x0 |
CTMRA6C0INT
0x0 |
CTMRB5C0INT
0x0 |
CTMRA5C0INT
0x0 |
CTMRB4C0INT
0x0 |
CTMRA4C0INT
0x0 |
CTMRB3C0INT
0x0 |
CTMRA3C0INT
0x0 |
CTMRB2C0INT
0x0 |
CTMRA2C0INT
0x0 |
CTMRB1C0INT
0x0 |
CTMRA1C0INT
0x0 |
CTMRB0C0INT
0x0 |
CTMRA0C0INT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | CTMRB7C1INT | RW | Counter/Timer B7 interrupt based on COMPR1. |
| 30 | CTMRA7C1INT | RW | Counter/Timer A7 interrupt based on COMPR1. |
| 29 | CTMRB6C1INT | RW | Counter/Timer B6 interrupt based on COMPR1. |
| 28 | CTMRA6C1INT | RW | Counter/Timer A6 interrupt based on COMPR1. |
| 27 | CTMRB5C1INT | RW | Counter/Timer B5 interrupt based on COMPR1. |
| 26 | CTMRA5C1INT | RW | Counter/Timer A5 interrupt based on COMPR1. |
| 25 | CTMRB4C1INT | RW | Counter/Timer B4 interrupt based on COMPR1. |
| 24 | CTMRA4C1INT | RW | Counter/Timer A4 interrupt based on COMPR1. |
| 23 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1. |
| 22 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1. |
| 21 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1. |
| 20 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1. |
| 19 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1. |
| 18 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1. |
| 17 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1. |
| 16 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1. |
| 15 | CTMRB7C0INT | RW | Counter/Timer B7 interrupt based on COMPR0. |
| 14 | CTMRA7C0INT | RW | Counter/Timer A7 interrupt based on COMPR0. |
| 13 | CTMRB6C0INT | RW | Counter/Timer B6 interrupt based on COMPR0. |
| 12 | CTMRA6C0INT | RW | Counter/Timer A6 interrupt based on COMPR0. |
| 11 | CTMRB5C0INT | RW | Counter/Timer B5 interrupt based on COMPR0. |
| 10 | CTMRA5C0INT | RW | Counter/Timer A5 interrupt based on COMPR0. |
| 9 | CTMRB4C0INT | RW | Counter/Timer B4 interrupt based on COMPR0. |
| 8 | CTMRA4C0INT | RW | Counter/Timer A4 interrupt based on COMPR0. |
| 7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0. |
| 6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0. |
| 5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0. |
| 4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0. |
| 3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0. |
| 2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0. |
| 1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0. |
| 0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0. |
| Instance 0 Address: | 0x40008300 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CAPTURED
0x0 |
CAPTUREC
0x0 |
CAPTUREB
0x0 |
CAPTUREA
0x0 |
OVERFLOW
0x0 |
COMPAREH
0x0 |
COMPAREG
0x0 |
COMPAREF
0x0 |
COMPAREE
0x0 |
COMPARED
0x0 |
COMPAREC
0x0 |
COMPAREB
0x0 |
COMPAREA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:13 | RSVD | RO | RESERVED. |
| 12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set. |
| 11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set. |
| 10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set. |
| 9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set. |
| 8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set. |
| 7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| Instance 0 Address: | 0x40008304 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CAPTURED
0x0 |
CAPTUREC
0x0 |
CAPTUREB
0x0 |
CAPTUREA
0x0 |
OVERFLOW
0x0 |
COMPAREH
0x0 |
COMPAREG
0x0 |
COMPAREF
0x0 |
COMPAREE
0x0 |
COMPARED
0x0 |
COMPAREC
0x0 |
COMPAREB
0x0 |
COMPAREA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:13 | RSVD | RO | RESERVED. |
| 12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set. |
| 11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set. |
| 10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set. |
| 9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set. |
| 8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set. |
| 7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| Instance 0 Address: | 0x40008308 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CAPTURED
0x0 |
CAPTUREC
0x0 |
CAPTUREB
0x0 |
CAPTUREA
0x0 |
OVERFLOW
0x0 |
COMPAREH
0x0 |
COMPAREG
0x0 |
COMPAREF
0x0 |
COMPAREE
0x0 |
COMPARED
0x0 |
COMPAREC
0x0 |
COMPAREB
0x0 |
COMPAREA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:13 | RSVD | RO | RESERVED. |
| 12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set. |
| 11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set. |
| 10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set. |
| 9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set. |
| 8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set. |
| 7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| 0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register. |
| Instance 0 Address: | 0x4000830C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CAPTURED
0x0 |
CAPTUREC
0x0 |
CAPTUREB
0x0 |
CAPTUREA
0x0 |
OVERFLOW
0x0 |
COMPAREH
0x0 |
COMPAREG
0x0 |
COMPAREF
0x0 |
COMPAREE
0x0 |
COMPARED
0x0 |
COMPAREC
0x0 |
COMPAREB
0x0 |
COMPAREA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:13 | RSVD | RO | RESERVED. |
| 12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set. |
| 11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set. |