Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i2 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.742ns (37.2% logic, 62.8% route), 4 logic levels.
Constraint Details:
4.742ns physical path delay m_DS18B20Z/SLICE_343 to m_DS18B20Z/SLICE_171 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.685ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_343 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C4C.CLK to R19C4C.Q0 m_DS18B20Z/SLICE_343 (from sys_clk_c)
ROUTE 58 1.749 R19C4C.Q0 to R18C4B.A0 state_back_2_N_122_2
CTOF_DEL --- 0.452 R18C4B.A0 to R18C4B.F0 m_DS18B20Z/SLICE_876
ROUTE 2 0.618 R18C4B.F0 to R18C4A.B1 m_DS18B20Z/n25378
CTOF_DEL --- 0.452 R18C4A.B1 to R18C4A.F1 m_DS18B20Z/SLICE_171
ROUTE 1 0.610 R18C4A.F1 to R18C4A.B0 m_DS18B20Z/n26651
CTOF_DEL --- 0.452 R18C4A.B0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
4.742 (37.2% logic, 62.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_343:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C4C.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.414ns (weighted slack = -14.387ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_init_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.471ns (44.2% logic, 55.8% route), 4 logic levels.
Constraint Details:
4.471ns physical path delay m_DS18B20Z/SLICE_150 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.414ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_150 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R18C3B.CLK to R18C3B.Q0 m_DS18B20Z/SLICE_150 (from sys_clk_c)
ROUTE 15 0.942 R18C3B.Q0 to R18C5C.B1 m_DS18B20Z/cnt_init_0
CTOF_DEL --- 0.452 R18C5C.B1 to R18C5C.F1 m_DS18B20Z/SLICE_971
ROUTE 1 0.882 R18C5C.F1 to R18C4C.B0 m_DS18B20Z/n27710
CTOOFX_DEL --- 0.661 R18C4C.B0 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.673 R18C4C.OFX0 to R18C4D.C0 m_DS18B20Z/one_wire_N_283
CTOF_DEL --- 0.452 R18C4D.C0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.471 (44.2% logic, 55.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_150:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R18C3B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.409ns (weighted slack = -14.357ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_write_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.466ns (44.2% logic, 55.8% route), 4 logic levels.
Constraint Details:
4.466ns physical path delay m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.409ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C4B.CLK to R19C4B.Q1 m_DS18B20Z/SLICE_156 (from sys_clk_c)
ROUTE 15 0.931 R19C4B.Q1 to R19C4A.B0 m_DS18B20Z/cnt_write_1
CTOF_DEL --- 0.452 R19C4A.B0 to R19C4A.F0 m_DS18B20Z/SLICE_974
ROUTE 3 0.888 R19C4A.F0 to R18C4C.A0 m_DS18B20Z/n27642
CTOOFX_DEL --- 0.661 R18C4C.A0 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.673 R18C4C.OFX0 to R18C4D.C0 m_DS18B20Z/one_wire_N_283
CTOF_DEL --- 0.452 R18C4D.C0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.466 (44.2% logic, 55.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_156:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C4B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.359ns (weighted slack = -14.059ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_wr_buffer_i0_i6 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.416ns (44.7% logic, 55.3% route), 4 logic levels.
Constraint Details:
4.416ns physical path delay m_DS18B20Z/SLICE_853 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.359ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_853 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C7A.CLK to R19C7A.Q1 m_DS18B20Z/SLICE_853 (from sys_clk_c)
ROUTE 1 0.882 R19C7A.Q1 to R19C6A.B1 m_DS18B20Z/data_wr_buffer_6
CTOOFX_DEL --- 0.661 R19C6A.B1 to R19C6A.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 0.678 R19C6A.OFX0 to R19C4A.C1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 R19C4A.C1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.882 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.416 (44.7% logic, 55.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_853:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C7A.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.216ns (weighted slack = -13.207ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_write_i0_i3 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.273ns (41.3% logic, 58.7% route), 4 logic levels.
Constraint Details:
4.273ns physical path delay m_DS18B20Z/SLICE_157 to m_DS18B20Z/SLICE_171 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.216ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_157 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C4D.CLK to R19C4D.Q1 m_DS18B20Z/SLICE_157 (from sys_clk_c)
ROUTE 14 1.280 R19C4D.Q1 to R18C4B.B0 m_DS18B20Z/cnt_write_3
CTOF_DEL --- 0.452 R18C4B.B0 to R18C4B.F0 m_DS18B20Z/SLICE_876
ROUTE 2 0.618 R18C4B.F0 to R18C4A.B1 m_DS18B20Z/n25378
CTOF_DEL --- 0.452 R18C4A.B1 to R18C4A.F1 m_DS18B20Z/SLICE_171
ROUTE 1 0.610 R18C4A.F1 to R18C4A.B0 m_DS18B20Z/n26651
CTOF_DEL --- 0.452 R18C4A.B0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
4.273 (41.3% logic, 58.7% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_157:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C4D.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.194ns (weighted slack = -13.076ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_init_i0_i2 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.251ns (46.4% logic, 53.6% route), 4 logic levels.
Constraint Details:
4.251ns physical path delay m_DS18B20Z/SLICE_151 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.194ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_151 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R20C5C.CLK to R20C5C.Q0 m_DS18B20Z/SLICE_151 (from sys_clk_c)
ROUTE 15 0.722 R20C5C.Q0 to R18C5C.C1 m_DS18B20Z/cnt_init_2
CTOF_DEL --- 0.452 R18C5C.C1 to R18C5C.F1 m_DS18B20Z/SLICE_971
ROUTE 1 0.882 R18C5C.F1 to R18C4C.B0 m_DS18B20Z/n27710
CTOOFX_DEL --- 0.661 R18C4C.B0 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.673 R18C4C.OFX0 to R18C4D.C0 m_DS18B20Z/one_wire_N_283
CTOF_DEL --- 0.452 R18C4D.C0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.251 (46.4% logic, 53.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_151:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5C.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.189ns (weighted slack = -13.046ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.246ns (46.5% logic, 53.5% route), 4 logic levels.
Constraint Details:
4.246ns physical path delay m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.189ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C6B.CLK to R19C6B.Q0 m_DS18B20Z/SLICE_146 (from sys_clk_c)
ROUTE 15 0.712 R19C6B.Q0 to R19C6A.C1 m_DS18B20Z/cnt_0
CTOOFX_DEL --- 0.661 R19C6A.C1 to R19C6A.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 0.678 R19C6A.OFX0 to R19C4A.C1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 R19C4A.C1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.882 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.246 (46.5% logic, 53.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_146:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C6B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Error: The following path exceeds requirements by 2.189ns (weighted slack = -13.046ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 4.246ns (46.5% logic, 53.5% route), 4 logic levels.
Constraint Details:
4.246ns physical path delay m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
-1.636ns skew and
0.150ns DIN_SET requirement (totaling 2.057ns) by 2.189ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R19C6B.CLK to R19C6B.Q0 m_DS18B20Z/SLICE_146 (from sys_clk_c)
ROUTE 15 0.712 R19C6B.Q0 to R19C6A.C0 m_DS18B20Z/cnt_0
CTOOFX_DEL --- 0.661 R19C6A.C0 to R19C6A.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 0.678 R19C6A.OFX0 to R19C4A.C1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 R19C4A.C1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.882 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
4.246 (46.5% logic, 53.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_146:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R19C6B.CLK sys_clk_c
--------
3.922 (28.9% logic, 71.1% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.132 C1.PAD to C1.PADDI sys_clk
ROUTE 262 2.790 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.409 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 1.227 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
5.558 (27.7% logic, 72.3% route), 2 logic levels.
Warning: 50.816MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clk_c" 103.756000 | | |
MHz ; | 103.756 MHz| 4.805 MHz| 5 *
| | |
FREQUENCY NET "m_uart_tx/clk_en" | | |
112.880000 MHz ; | 112.880 MHz| 15.709 MHz| 10 *
| | |
FREQUENCY NET "m_uart_tx/clk_uart" | | |
203.957000 MHz ; | 203.957 MHz| 24.116 MHz| 5 *
| | |
FREQUENCY NET "m_clock/clk_1ms" | | |
217.297000 MHz ; | 217.297 MHz| 5.268 MHz| 5 *
| | |
FREQUENCY NET "m_clock/clk_500ms" | | |
136.986000 MHz ; | 136.986 MHz| 7.425 MHz| 9 *
| | |
FREQUENCY NET "m_DS18B20Z/clk_1mhz" | | |
293.858000 MHz ; | 293.858 MHz| 50.816 MHz| 4 *
| | |
----------------------------------------------------------------------------
6 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n26544 | 3| 4096| 36.87%
| | |
uart_data_120_N_1005_5 | 14| 4075| 36.69%
| | |
n25294 | 4| 2369| 21.33%
| | |
m_uart_tx/n26542 | 1| 2343| 21.09%
| | |
m_bcd_8421/n6_adj_1656 | 1| 1769| 15.93%
| | |
n27540 | 6| 1736| 15.63%
| | |
m_bcd_8421/n25255 | 2| 1691| 15.22%
| | |
m_OLED12832/char_reg_7_N_535_2 | 1| 1641| 14.77%
| | |
m_OLED12832/n64 | 1| 1641| 14.77%
| | |
m_OLED12832/n28518 | 1| 1641| 14.77%
| | |
m_OLED12832/n24 | 1| 1641| 14.77%
| | |
m_uart_tx/n4 | 1| 1545| 13.91%
| | |
m_OLED12832/n28514 | 1| 1428| 12.86%
| | |
m_OLED12832/num_0 | 49| 1370| 12.33%
| | |
m_bcd_8421/n17632 | 2| 1337| 12.04%
| | |
m_clock/n25024 | 2| 1276| 11.49%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 16 clocks:
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ; Transfers: 19
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 12
Clock Domain: sys_clk_c Source: sys_clk.PAD Loads: 262
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 1
Timing summary (Setup):
---------------
Timing errors: 11108 Score: 437665324
Cumulative negative slack: 437665324
Constraints cover 84154 paths, 61 nets, and 8103 connections (98.44% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS>.2
Fri Feb 19 19:37:55 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o ds18b20_impl1.twr -gui -msgset C:/fpga/ds18b20/promote.xml ds18b20_impl1.ncd ds18b20_impl1.prf
Design file: ds18b20_impl1.ncd
Preference file: ds18b20_impl1.prf
Device,speed: LCMXO2-4000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "sys_clk_c" 103.756000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz (626 errors)
4096 items scored, 626 timing errors detected.
FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz (0 errors) 208 items scored, 0 timing errors detected.
FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz (0 errors) 1337 items scored, 0 timing errors detected.
FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz (738 errors)
2003 items scored, 738 timing errors detected.
FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz (3 errors)
59 items scored, 3 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i14 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i15 (to sys_clk_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_616 to SLICE_616 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_616 to SLICE_616:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R16C17B.CLK to R16C17B.Q0 SLICE_616 (from sys_clk_c)
ROUTE 1 0.152 R16C17B.Q0 to R16C17B.M1 m_uart_recv/n593 (to sys_clk_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_616:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C17B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_616:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C17B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i12 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i13 (to sys_clk_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_743 to SLICE_743 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_743 to SLICE_743:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R16C20B.CLK to R16C20B.Q0 SLICE_743 (from sys_clk_c)
ROUTE 1 0.152 R16C20B.Q0 to R16C20B.M1 m_uart_recv/n595 (to sys_clk_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_743:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C20B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_743:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C20B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i10 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i11 (to sys_clk_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_942 to SLICE_942 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_942 to SLICE_942:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R16C19D.CLK to R16C19D.Q0 SLICE_942 (from sys_clk_c)
ROUTE 1 0.152 R16C19D.Q0 to R16C19D.M1 m_uart_recv/n597 (to sys_clk_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_942:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C19D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_942:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R16C19D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i0 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i1 (to sys_clk_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_943 to SLICE_943 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_943 to SLICE_943:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C19B.CLK to R14C19B.Q0 SLICE_943 (from sys_clk_c)
ROUTE 1 0.152 R14C19B.Q0 to R14C19B.M1 m_uart_recv/n607 (to sys_clk_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_943:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R14C19B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_943:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R14C19B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/temperature_buffer_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/temperature_i0_i1 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_40 to SLICE_41 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_40 to SLICE_41:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R13C4B.CLK to R13C4B.Q0 SLICE_40 (from sys_clk_c)
ROUTE 2 0.154 R13C4B.Q0 to R13C4A.M1 m_DS18B20Z/temperature_buffer_1 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_40:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R13C4B.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_41:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R13C4A.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i4 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i5 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_738 to SLICE_738 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_738 to SLICE_738:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C19D.CLK to R12C19D.Q0 SLICE_738 (from sys_clk_c)
ROUTE 4 0.154 R12C19D.Q0 to R12C19D.M1 m_uart_recv/n603 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_738:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R12C19D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_738:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R12C19D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i6 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i7 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_739 to SLICE_739 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_739 to SLICE_739:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C21C.CLK to R12C21C.Q0 SLICE_739 (from sys_clk_c)
ROUTE 3 0.154 R12C21C.Q0 to R12C21C.M1 m_uart_recv/n601 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_739:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R12C21C.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_739:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R12C21C.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/uart_rxd_d0_54 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/uart_rxd_d1_55 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_740 to SLICE_740 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_740 to SLICE_740:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C21D.CLK to R17C21D.Q0 SLICE_740 (from sys_clk_c)
ROUTE 2 0.154 R17C21D.Q0 to R17C21D.M1 m_uart_recv/uart_rxd_d0 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_740:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R17C21D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_740:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R17C21D.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i8 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i9 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_742 to SLICE_742 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_742 to SLICE_742:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R13C25A.CLK to R13C25A.Q0 SLICE_742 (from sys_clk_c)
ROUTE 3 0.154 R13C25A.Q0 to R13C25A.M1 m_uart_recv/n599 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_742:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R13C25A.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_742:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R13C25A.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart2tone/recv_done_d0_54 (from sys_clk_c +)
Destination: FF Data in m_uart2tone/recv_done_d1_55 (to sys_clk_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_851 to SLICE_851 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_851 to SLICE_851:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C21C.CLK to R14C21C.Q0 SLICE_851 (from sys_clk_c)
ROUTE 2 0.154 R14C21C.Q0 to R14C21C.M1 m_uart2tone/recv_done_d0 (to sys_clk_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_851:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R14C21C.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sys_clk to SLICE_851:
Name Fanout Delay (ns) Site Resource
ROUTE 262 1.116 C1.PADDI to R14C21C.CLK sys_clk_c
--------
1.116 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
4096 items scored, 626 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.224ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i18 (to m_uart_tx/clk_en +)
Delay: 0.374ns (62.6% logic, 37.4% route), 2 logic levels.
Constraint Details:
0.374ns physical path delay m_DS18B20Z/SLICE_862 to SLICE_324 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.224ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_862 to SLICE_324:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16A.CLK to R15C16A.Q1 m_DS18B20Z/SLICE_862 (from sys_clk_c)
ROUTE 4 0.138 R15C16A.Q1 to R15C16D.C0 temp_raw_data_1
CTOF_DEL --- 0.101 R15C16D.C0 to R15C16D.F0 SLICE_324
ROUTE 2 0.002 R15C16D.F0 to R15C16D.DI0 n13 (to m_uart_tx/clk_en)
--------
0.374 (62.6% logic, 37.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_862:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_324:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R15C16D.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.150ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i18 (to m_uart_tx/clk_en +)
Delay: 0.448ns (52.2% logic, 47.8% route), 2 logic levels.
Constraint Details:
0.448ns physical path delay m_DS18B20Z/SLICE_862 to SLICE_324 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.150ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_862 to SLICE_324:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16A.CLK to R15C16A.Q0 m_DS18B20Z/SLICE_862 (from sys_clk_c)
ROUTE 4 0.212 R15C16A.Q0 to R15C16D.A0 temp_raw_data_0
CTOF_DEL --- 0.101 R15C16D.A0 to R15C16D.F0 SLICE_324
ROUTE 2 0.002 R15C16D.F0 to R15C16D.DI0 n13 (to m_uart_tx/clk_en)
--------
0.448 (52.2% logic, 47.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_862:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_324:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R15C16D.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.112ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i15 (to m_uart_tx/clk_en +)
Delay: 0.486ns (48.1% logic, 51.9% route), 2 logic levels.
Constraint Details:
0.486ns physical path delay m_DS18B20Z/SLICE_862 to SLICE_322 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.112ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_862 to SLICE_322:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16A.CLK to R15C16A.Q0 m_DS18B20Z/SLICE_862 (from sys_clk_c)
ROUTE 4 0.250 R15C16A.Q0 to R17C18A.C0 temp_raw_data_0
CTOF_DEL --- 0.101 R17C18A.C0 to R17C18A.F0 SLICE_322
ROUTE 2 0.002 R17C18A.F0 to R17C18A.DI0 temp_unit_0 (to m_uart_tx/clk_en)
--------
0.486 (48.1% logic, 51.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_862:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_322:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C18A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.112ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i16 (to m_uart_tx/clk_en +)
Delay: 0.486ns (48.1% logic, 51.9% route), 2 logic levels.
Constraint Details:
0.486ns physical path delay m_DS18B20Z/SLICE_862 to SLICE_322 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.112ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_862 to SLICE_322:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16A.CLK to R15C16A.Q0 m_DS18B20Z/SLICE_862 (from sys_clk_c)
ROUTE 4 0.250 R15C16A.Q0 to R17C18A.C1 temp_raw_data_0
CTOF_DEL --- 0.101 R17C18A.C1 to R17C18A.F1 SLICE_322
ROUTE 2 0.002 R17C18A.F1 to R17C18A.DI1 temp_unit_1 (to m_uart_tx/clk_en)
--------
0.486 (48.1% logic, 51.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_862:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_322:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C18A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.057ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i11 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i37 (to m_uart_tx/clk_en +)
Delay: 0.541ns (61.9% logic, 38.1% route), 3 logic levels.
Constraint Details:
0.541ns physical path delay SLICE_349 to SLICE_329 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.057ns
Physical Path Details:
Data path SLICE_349 to SLICE_329:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R17C15A.CLK to R17C15A.Q1 SLICE_349 (from sys_clk_c)
ROUTE 6 0.145 R17C15A.Q1 to R17C17D.C1 temp_raw_data_11
CTOF_DEL --- 0.101 R17C17D.C1 to R17C17D.F1 SLICE_329
ROUTE 5 0.059 R17C17D.F1 to R17C17D.C0 n18
CTOF_DEL --- 0.101 R17C17D.C0 to R17C17D.F0 SLICE_329
ROUTE 14 0.002 R17C17D.F0 to R17C17D.DI0 uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
0.541 (61.9% logic, 38.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_349:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R17C15A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_329:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C17D.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.048ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i7 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i9 (to m_uart_tx/clk_en +)
Delay: 0.550ns (60.9% logic, 39.1% route), 3 logic levels.
Constraint Details:
0.550ns physical path delay SLICE_347 to SLICE_321 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.048ns
Physical Path Details:
Data path SLICE_347 to SLICE_321:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C14A.CLK to R18C14A.Q1 SLICE_347 (from sys_clk_c)
ROUTE 17 0.159 R18C14A.Q1 to R18C16D.C0 temp_raw_data_7
CTOF_DEL --- 0.101 R18C16D.C0 to R18C16D.F0 m_bcd_8421/SLICE_828
ROUTE 1 0.053 R18C16D.F0 to R18C17A.D1 m_bcd_8421/n5
CTOF_DEL --- 0.101 R18C17A.D1 to R18C17A.F1 SLICE_321
ROUTE 5 0.003 R18C17A.F1 to R18C17A.DI1 temp_ten_3 (to m_uart_tx/clk_en)
--------
0.550 (60.9% logic, 39.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to SLICE_347:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C14A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_321:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R18C17A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.037ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i3 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i15 (to m_uart_tx/clk_en +)
Delay: 0.561ns (41.7% logic, 58.3% route), 2 logic levels.
Constraint Details:
0.561ns physical path delay m_DS18B20Z/SLICE_880 to SLICE_322 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.037ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_880 to SLICE_322:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16C.CLK to R15C16C.Q1 m_DS18B20Z/SLICE_880 (from sys_clk_c)
ROUTE 5 0.325 R15C16C.Q1 to R17C18A.A0 temp_raw_data_3
CTOF_DEL --- 0.101 R17C18A.A0 to R17C18A.F0 SLICE_322
ROUTE 2 0.002 R17C18A.F0 to R17C18A.DI0 temp_unit_0 (to m_uart_tx/clk_en)
--------
0.561 (41.7% logic, 58.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_880:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16C.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_322:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C18A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.037ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i3 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i16 (to m_uart_tx/clk_en +)
Delay: 0.561ns (41.7% logic, 58.3% route), 2 logic levels.
Constraint Details:
0.561ns physical path delay m_DS18B20Z/SLICE_880 to SLICE_322 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.037ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_880 to SLICE_322:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16C.CLK to R15C16C.Q1 m_DS18B20Z/SLICE_880 (from sys_clk_c)
ROUTE 5 0.325 R15C16C.Q1 to R17C18A.A1 temp_raw_data_3
CTOF_DEL --- 0.101 R17C18A.A1 to R17C18A.F1 SLICE_322
ROUTE 2 0.002 R17C18A.F1 to R17C18A.DI1 temp_unit_1 (to m_uart_tx/clk_en)
--------
0.561 (41.7% logic, 58.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_880:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16C.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_322:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C18A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 1.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i3 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i17 (to m_uart_tx/clk_en +)
Delay: 0.596ns (39.3% logic, 60.7% route), 2 logic levels.
Constraint Details:
0.596ns physical path delay m_DS18B20Z/SLICE_880 to SLICE_323 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 1.002ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_880 to SLICE_323:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16C.CLK to R15C16C.Q1 m_DS18B20Z/SLICE_880 (from sys_clk_c)
ROUTE 5 0.360 R15C16C.Q1 to R17C19A.C0 temp_raw_data_3
CTOF_DEL --- 0.101 R17C19A.C0 to R17C19A.F0 SLICE_323
ROUTE 2 0.002 R17C19A.F0 to R17C19A.DI0 temp_unit_2 (to m_uart_tx/clk_en)
--------
0.596 (39.3% logic, 60.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_880:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16C.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_323:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C19A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
Error: The following path exceeds requirements by 0.993ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i2 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i17 (to m_uart_tx/clk_en +)
Delay: 0.605ns (38.7% logic, 61.3% route), 2 logic levels.
Constraint Details:
0.605ns physical path delay m_DS18B20Z/SLICE_880 to SLICE_323 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.611ns skew requirement (totaling 1.598ns) by 0.993ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_880 to SLICE_323:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C16C.CLK to R15C16C.Q0 m_DS18B20Z/SLICE_880 (from sys_clk_c)
ROUTE 5 0.369 R15C16C.Q0 to R17C19A.B0 temp_raw_data_2
CTOF_DEL --- 0.101 R17C19A.B0 to R17C19A.F0 SLICE_323
ROUTE 2 0.002 R17C19A.F0 to R17C19A.DI0 temp_unit_2 (to m_uart_tx/clk_en)
--------
0.605 (38.7% logic, 61.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_880:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R15C16C.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to SLICE_323:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R12C11D.CLK sys_clk_c
REG_DEL --- 0.154 R12C11D.CLK to R12C11D.Q0 m_uart_tx/SLICE_310
ROUTE 18 1.457 R12C11D.Q0 to R17C19A.CLK m_uart_tx/clk_en
--------
3.176 (19.0% logic, 81.0% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ;
208 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.380ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i6 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i6 (to m_uart_tx/clk_uart +)
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
Constraint Details:
0.367ns physical path delay m_uart_tx/SLICE_317 to m_uart_tx/SLICE_317 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
Physical Path Details:
Data path m_uart_tx/SLICE_317 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C20A.CLK to R15C20A.Q0 m_uart_tx/SLICE_317 (from m_uart_tx/clk_uart)
ROUTE 3 0.133 R15C20A.Q0 to R15C20A.A0 m_uart_tx/i_6
CTOF_DEL --- 0.101 R15C20A.A0 to R15C20A.F0 m_uart_tx/SLICE_317
ROUTE 1 0.000 R15C20A.F0 to R15C20A.DI0 m_uart_tx/n736 (to m_uart_tx/clk_uart)
--------
0.367 (63.8% logic, 36.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20A.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20A.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.381ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/state_50 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/state_50 (to m_uart_tx/clk_uart +)
Delay: 0.368ns (63.6% logic, 36.4% route), 2 logic levels.
Constraint Details:
0.368ns physical path delay m_uart_tx/SLICE_318 to m_uart_tx/SLICE_318 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.381ns
Physical Path Details:
Data path m_uart_tx/SLICE_318 to m_uart_tx/SLICE_318:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C19D.CLK to R14C19D.Q0 m_uart_tx/SLICE_318 (from m_uart_tx/clk_uart)
ROUTE 8 0.134 R14C19D.Q0 to R14C19D.A0 m_uart_tx/state
CTOF_DEL --- 0.101 R14C19D.A0 to R14C19D.F0 m_uart_tx/SLICE_318
ROUTE 1 0.000 R14C19D.F0 to R14C19D.DI0 m_uart_tx/n12343 (to m_uart_tx/clk_uart)
--------
0.368 (63.6% logic, 36.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_318:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R14C19D.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_318:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R14C19D.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.383ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i0 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i0 (to m_uart_tx/clk_uart +)
Delay: 0.370ns (63.2% logic, 36.8% route), 2 logic levels.
Constraint Details:
0.370ns physical path delay m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.383ns
Physical Path Details:
Data path m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R16C19C.CLK to R16C19C.Q0 m_uart_tx/SLICE_314 (from m_uart_tx/clk_uart)
ROUTE 33 0.136 R16C19C.Q0 to R16C19C.A0 m_uart_tx/i_0
CTOF_DEL --- 0.101 R16C19C.A0 to R16C19C.F0 m_uart_tx/SLICE_314
ROUTE 1 0.000 R16C19C.F0 to R16C19C.DI0 m_uart_tx/n27664 (to m_uart_tx/clk_uart)
--------
0.370 (63.2% logic, 36.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R16C19C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R16C19C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.383ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i1 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i1 (to m_uart_tx/clk_uart +)
Delay: 0.370ns (63.2% logic, 36.8% route), 2 logic levels.
Constraint Details:
0.370ns physical path delay m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.383ns
Physical Path Details:
Data path m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R16C19C.CLK to R16C19C.Q1 m_uart_tx/SLICE_314 (from m_uart_tx/clk_uart)
ROUTE 26 0.136 R16C19C.Q1 to R16C19C.A1 m_uart_tx/i_1
CTOF_DEL --- 0.101 R16C19C.A1 to R16C19C.F1 m_uart_tx/SLICE_314
ROUTE 1 0.000 R16C19C.F1 to R16C19C.DI1 m_uart_tx/n741 (to m_uart_tx/clk_uart)
--------
0.370 (63.2% logic, 36.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R16C19C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R16C19C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.386ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i2 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i4 (to m_uart_tx/clk_uart +)
Delay: 0.373ns (62.7% logic, 37.3% route), 2 logic levels.
Constraint Details:
0.373ns physical path delay m_uart_tx/SLICE_315 to m_uart_tx/SLICE_316 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.386ns
Physical Path Details:
Data path m_uart_tx/SLICE_315 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C20C.CLK to R15C20C.Q0 m_uart_tx/SLICE_315 (from m_uart_tx/clk_uart)
ROUTE 20 0.139 R15C20C.Q0 to R15C21B.D0 m_uart_tx/i_2
CTOF_DEL --- 0.101 R15C21B.D0 to R15C21B.F0 m_uart_tx/SLICE_316
ROUTE 1 0.000 R15C21B.F0 to R15C21B.DI0 m_uart_tx/n738 (to m_uart_tx/clk_uart)
--------
0.373 (62.7% logic, 37.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_315:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C21B.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.388ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i5 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i5 (to m_uart_tx/clk_uart +)
Delay: 0.375ns (62.4% logic, 37.6% route), 2 logic levels.
Constraint Details:
0.375ns physical path delay m_uart_tx/SLICE_316 to m_uart_tx/SLICE_316 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.388ns
Physical Path Details:
Data path m_uart_tx/SLICE_316 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C21B.CLK to R15C21B.Q1 m_uart_tx/SLICE_316 (from m_uart_tx/clk_uart)
ROUTE 5 0.141 R15C21B.Q1 to R15C21B.D1 m_uart_tx/i_5
CTOF_DEL --- 0.101 R15C21B.D1 to R15C21B.F1 m_uart_tx/SLICE_316
ROUTE 1 0.000 R15C21B.F1 to R15C21B.DI1 m_uart_tx/n737 (to m_uart_tx/clk_uart)
--------
0.375 (62.4% logic, 37.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C21B.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C21B.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.389ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i5 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i6 (to m_uart_tx/clk_uart +)
Delay: 0.376ns (62.2% logic, 37.8% route), 2 logic levels.
Constraint Details:
0.376ns physical path delay m_uart_tx/SLICE_316 to m_uart_tx/SLICE_317 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.389ns
Physical Path Details:
Data path m_uart_tx/SLICE_316 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C21B.CLK to R15C21B.Q1 m_uart_tx/SLICE_316 (from m_uart_tx/clk_uart)
ROUTE 5 0.142 R15C21B.Q1 to R15C20A.C0 m_uart_tx/i_5
CTOF_DEL --- 0.101 R15C20A.C0 to R15C20A.F0 m_uart_tx/SLICE_317
ROUTE 1 0.000 R15C20A.F0 to R15C20A.DI0 m_uart_tx/n736 (to m_uart_tx/clk_uart)
--------
0.376 (62.2% logic, 37.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_316:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C21B.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20A.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.389ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i3 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i3 (to m_uart_tx/clk_uart +)
Delay: 0.376ns (62.2% logic, 37.8% route), 2 logic levels.
Constraint Details:
0.376ns physical path delay m_uart_tx/SLICE_315 to m_uart_tx/SLICE_315 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.389ns
Physical Path Details:
Data path m_uart_tx/SLICE_315 to m_uart_tx/SLICE_315:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C20C.CLK to R15C20C.Q1 m_uart_tx/SLICE_315 (from m_uart_tx/clk_uart)
ROUTE 19 0.142 R15C20C.Q1 to R15C20C.D1 m_uart_tx/i_3
CTOF_DEL --- 0.101 R15C20C.D1 to R15C20C.F1 m_uart_tx/SLICE_315
ROUTE 1 0.000 R15C20C.F1 to R15C20C.DI1 m_uart_tx/n739 (to m_uart_tx/clk_uart)
--------
0.376 (62.2% logic, 37.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_315:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_315:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.398ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i6 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 0.385ns (59.2% logic, 40.8% route), 2 logic levels.
Constraint Details:
0.385ns physical path delay m_uart_tx/SLICE_317 to m_uart_tx/SLICE_367 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.398ns
Physical Path Details:
Data path m_uart_tx/SLICE_317 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C20A.CLK to R15C20A.Q0 m_uart_tx/SLICE_317 (from m_uart_tx/clk_uart)
ROUTE 3 0.157 R15C20A.Q0 to R15C21A.M0 m_uart_tx/i_6
MTOOFX_DEL --- 0.095 R15C21A.M0 to R15C21A.OFX0 m_uart_tx/SLICE_367
ROUTE 1 0.000 R15C21A.OFX0 to R15C21A.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
0.385 (59.2% logic, 40.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_317:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C20A.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R15C21A.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.421ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/state_50 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i1 (to m_uart_tx/clk_uart +)
FF m_uart_tx/i_i0
Delay: 0.397ns (33.5% logic, 66.5% route), 1 logic levels.
Constraint Details:
0.397ns physical path delay m_uart_tx/SLICE_318 to m_uart_tx/SLICE_314 meets
-0.024ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.024ns) by 0.421ns
Physical Path Details:
Data path m_uart_tx/SLICE_318 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R14C19D.CLK to R14C19D.Q0 m_uart_tx/SLICE_318 (from m_uart_tx/clk_uart)
ROUTE 8 0.264 R14C19D.Q0 to R16C19C.CE m_uart_tx/state (to m_uart_tx/clk_uart)
--------
0.397 (33.5% logic, 66.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_318:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R14C19D.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_uart_tx/SLICE_311 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 8 0.977 R13C31A.Q0 to R16C19C.CLK m_uart_tx/clk_uart
--------
0.977 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ;
1337 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i2 (to m_clock/clk_1ms +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay m_clock/SLICE_75 to m_clock/SLICE_75 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path m_clock/SLICE_75 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C15B.CLK to R20C15B.Q1 m_clock/SLICE_75 (from m_clock/clk_1ms)
ROUTE 1 0.130 R20C15B.Q1 to R20C15B.A1 m_clock/n14
CTOF_DEL --- 0.101 R20C15B.A1 to R20C15B.F1 m_clock/SLICE_75
ROUTE 1 0.000 R20C15B.F1 to R20C15B.DI1 m_clock/n83 (to m_clock/clk_1ms)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i1 (to m_clock/clk_1ms +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay m_clock/SLICE_75 to m_clock/SLICE_75 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path m_clock/SLICE_75 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C15B.CLK to R20C15B.Q0 m_clock/SLICE_75 (from m_clock/clk_1ms)
ROUTE 1 0.130 R20C15B.Q0 to R20C15B.A0 m_clock/n15
CTOF_DEL --- 0.101 R20C15B.A0 to R20C15B.F0 m_clock/SLICE_75
ROUTE 1 0.000 R20C15B.F0 to R20C15B.DI0 m_clock/n84 (to m_clock/clk_1ms)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i4 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i4 (to m_clock/clk_1ms +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay m_clock/SLICE_74 to m_clock/SLICE_74 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path m_clock/SLICE_74 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C15C.CLK to R20C15C.Q1 m_clock/SLICE_74 (from m_clock/clk_1ms)
ROUTE 1 0.130 R20C15C.Q1 to R20C15C.A1 m_clock/n12
CTOF_DEL --- 0.101 R20C15C.A1 to R20C15C.F1 m_clock/SLICE_74
ROUTE 1 0.000 R20C15C.F1 to R20C15C.DI1 m_clock/n81 (to m_clock/clk_1ms)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15C.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15C.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i3 (to m_clock/clk_1ms +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay m_clock/SLICE_74 to m_clock/SLICE_74 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path m_clock/SLICE_74 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C15C.CLK to R20C15C.Q0 m_clock/SLICE_74 (from m_clock/clk_1ms)
ROUTE 1 0.130 R20C15C.Q0 to R20C15C.A0 m_clock/n13
CTOF_DEL --- 0.101 R20C15C.A0 to R20C15C.F0 m_clock/SLICE_74
ROUTE 1 0.000 R20C15C.F0 to R20C15C.DI0 m_clock/n82 (to m_clock/clk_1ms)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15C.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15C.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.377ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i0 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i0 (to m_clock/clk_1ms +)
Delay: 0.364ns (64.3% logic, 35.7% route), 2 logic levels.
Constraint Details:
0.364ns physical path delay m_clock/SLICE_76 to m_clock/SLICE_76 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.377ns
Physical Path Details:
Data path m_clock/SLICE_76 to m_clock/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C15A.CLK to R20C15A.Q1 m_clock/SLICE_76 (from m_clock/clk_1ms)
ROUTE 1 0.130 R20C15A.Q1 to R20C15A.A1 m_clock/n16
CTOF_DEL --- 0.101 R20C15A.A1 to R20C15A.F1 m_clock/SLICE_76
ROUTE 1 0.000 R20C15A.F1 to R20C15A.DI1 m_clock/n85 (to m_clock/clk_1ms)
--------
0.364 (64.3% logic, 35.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15A.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C15A.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/clk_500ms_cnt_2275__i10 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/clk_500ms_cnt_2275__i10 (to m_clock/clk_1ms +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay m_clock/SLICE_77 to m_clock/SLICE_77 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path m_clock/SLICE_77 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C16B.CLK to R10C16B.Q1 m_clock/SLICE_77 (from m_clock/clk_1ms)
ROUTE 2 0.132 R10C16B.Q1 to R10C16B.A1 m_clock/clk_500ms_cnt_10
CTOF_DEL --- 0.101 R10C16B.A1 to R10C16B.F1 m_clock/SLICE_77
ROUTE 1 0.000 R10C16B.F1 to R10C16B.DI1 m_clock/n50 (to m_clock/clk_1ms)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/clk_500ms_cnt_2275__i9 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/clk_500ms_cnt_2275__i9 (to m_clock/clk_1ms +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay m_clock/SLICE_77 to m_clock/SLICE_77 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path m_clock/SLICE_77 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C16B.CLK to R10C16B.Q0 m_clock/SLICE_77 (from m_clock/clk_1ms)
ROUTE 2 0.132 R10C16B.Q0 to R10C16B.A0 m_clock/clk_500ms_cnt_9
CTOF_DEL --- 0.101 R10C16B.A0 to R10C16B.F0 m_clock/SLICE_77
ROUTE 1 0.000 R10C16B.F0 to R10C16B.DI0 m_clock/n51 (to m_clock/clk_1ms)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16B.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/clk_500ms_cnt_2275__i6 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/clk_500ms_cnt_2275__i6 (to m_clock/clk_1ms +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay m_clock/SLICE_79 to m_clock/SLICE_79 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path m_clock/SLICE_79 to m_clock/SLICE_79:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C15D.CLK to R10C15D.Q1 m_clock/SLICE_79 (from m_clock/clk_1ms)
ROUTE 2 0.132 R10C15D.Q1 to R10C15D.A1 m_clock/clk_500ms_cnt_6
CTOF_DEL --- 0.101 R10C15D.A1 to R10C15D.F1 m_clock/SLICE_79
ROUTE 1 0.000 R10C15D.F1 to R10C15D.DI1 m_clock/n54 (to m_clock/clk_1ms)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_79:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C15D.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_79:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C15D.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/clk_500ms_cnt_2275__i7 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/clk_500ms_cnt_2275__i7 (to m_clock/clk_1ms +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay m_clock/SLICE_78 to m_clock/SLICE_78 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path m_clock/SLICE_78 to m_clock/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C16A.CLK to R10C16A.Q0 m_clock/SLICE_78 (from m_clock/clk_1ms)
ROUTE 2 0.132 R10C16A.Q0 to R10C16A.A0 m_clock/clk_500ms_cnt_7
CTOF_DEL --- 0.101 R10C16A.A0 to R10C16A.F0 m_clock/SLICE_78
ROUTE 1 0.000 R10C16A.F0 to R10C16A.DI0 m_clock/n53 (to m_clock/clk_1ms)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16A.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R10C16A.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i13 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i13 (to m_clock/clk_1ms +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay m_clock/SLICE_69 to m_clock/SLICE_69 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path m_clock/SLICE_69 to m_clock/SLICE_69:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C16D.CLK to R20C16D.Q0 m_clock/SLICE_69 (from m_clock/clk_1ms)
ROUTE 2 0.132 R20C16D.Q0 to R20C16D.A0 m_clock/ms_13
CTOF_DEL --- 0.101 R20C16D.A0 to R20C16D.F0 m_clock/SLICE_69
ROUTE 1 0.000 R20C16D.F0 to R20C16D.DI0 m_clock/n72 (to m_clock/clk_1ms)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path m_clock/SLICE_278 to m_clock/SLICE_69:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C16D.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path m_clock/SLICE_278 to m_clock/SLICE_69:
Name Fanout Delay (ns) Site Resource
ROUTE 26 1.098 R2C16A.Q0 to R20C16D.CLK m_clock/clk_1ms
--------
1.098 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ;
2003 items scored, 738 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.420ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i0 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i0 (to m_clock/clk_500ms +)
Delay: 0.389ns (60.2% logic, 39.8% route), 2 logic levels.
Constraint Details:
0.389ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_282 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.420ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19D.CLK to R20C19D.Q0 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 19 0.153 R20C19D.Q0 to R19C19C.D0 time_hour_low_0
CTOF_DEL --- 0.101 R19C19C.D0 to R19C19C.F0 m_clock/SLICE_282
ROUTE 2 0.002 R19C19C.F0 to R19C19C.DI0 m_clock/hour_set_high_3_N_1581_0 (to m_clock/clk_500ms)
--------
0.389 (60.2% logic, 39.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_282:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R19C19C.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/min_set_low_i0_i2 (to m_clock/clk_500ms +)
Delay: 0.433ns (66.7% logic, 33.3% route), 2 logic levels.
Constraint Details:
0.433ns physical path delay m_clock/SLICE_356 to m_clock/SLICE_292 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.376ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_clock/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 0.144 R20C23C.Q1 to R20C24A.C0 time_min_low_1
CTOOFX_DEL --- 0.156 R20C24A.C0 to R20C24A.OFX0 m_clock/SLICE_292
ROUTE 1 0.000 R20C24A.OFX0 to R20C24A.DI0 m_clock/n2489 (to m_clock/clk_500ms)
--------
0.433 (66.7% logic, 33.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_292:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R20C24A.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.370ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i2 (to m_clock/clk_500ms +)
Delay: 0.439ns (65.8% logic, 34.2% route), 2 logic levels.
Constraint Details:
0.439ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_284 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.370ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.146 R20C19A.Q0 to R18C19D.D1 time_hour_low_2
CTOOFX_DEL --- 0.156 R18C19D.D1 to R18C19D.OFX0 m_clock/SLICE_284
ROUTE 2 0.004 R18C19D.OFX0 to R18C19D.DI0 m_clock/hour_set_high_3_N_1581_2 (to m_clock/clk_500ms)
--------
0.439 (65.8% logic, 34.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R18C19D.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.370ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i2 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i2 (to m_clock/clk_500ms +)
Delay: 0.439ns (65.8% logic, 34.2% route), 2 logic levels.
Constraint Details:
0.439ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_284 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.370ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19A.CLK to R20C19A.Q0 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.146 R20C19A.Q0 to R18C19D.D0 time_hour_low_2
CTOOFX_DEL --- 0.156 R18C19D.D0 to R18C19D.OFX0 m_clock/SLICE_284
ROUTE 2 0.004 R18C19D.OFX0 to R18C19D.DI0 m_clock/hour_set_high_3_N_1581_2 (to m_clock/clk_500ms)
--------
0.439 (65.8% logic, 34.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R18C19D.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.366ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 0.443ns (65.2% logic, 34.8% route), 2 logic levels.
Constraint Details:
0.443ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.366ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19A.CLK to R20C19A.Q1 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.150 R20C19A.Q1 to R19C19D.D1 time_hour_low_3
CTOOFX_DEL --- 0.156 R19C19D.D1 to R19C19D.OFX0 m_clock/SLICE_285
ROUTE 2 0.004 R19C19D.OFX0 to R19C19D.DI0 m_clock/hour_set_high_3_N_1581_3 (to m_clock/clk_500ms)
--------
0.443 (65.2% logic, 34.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.366ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i3 (to m_clock/clk_500ms +)
Delay: 0.443ns (65.2% logic, 34.8% route), 2 logic levels.
Constraint Details:
0.443ns physical path delay m_clock/SLICE_353 to m_clock/SLICE_285 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.366ns
Physical Path Details:
Data path m_clock/SLICE_353 to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19A.CLK to R20C19A.Q1 m_clock/SLICE_353 (from m_clock/clk_1ms)
ROUTE 14 0.150 R20C19A.Q1 to R19C19D.D0 time_hour_low_3
CTOOFX_DEL --- 0.156 R19C19D.D0 to R19C19D.OFX0 m_clock/SLICE_285
ROUTE 2 0.004 R19C19D.OFX0 to R19C19D.DI0 m_clock/hour_set_high_3_N_1581_3 (to m_clock/clk_500ms)
--------
0.443 (65.2% logic, 34.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_353:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19A.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_285:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R19C19D.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.360ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i0 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i2 (to m_clock/clk_500ms +)
Delay: 0.449ns (64.4% logic, 35.6% route), 2 logic levels.
Constraint Details:
0.449ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_284 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.360ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C19D.CLK to R20C19D.Q0 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 19 0.156 R20C19D.Q0 to R18C19D.C0 time_hour_low_0
CTOOFX_DEL --- 0.156 R18C19D.C0 to R18C19D.OFX0 m_clock/SLICE_284
ROUTE 2 0.004 R18C19D.OFX0 to R18C19D.DI0 m_clock/hour_set_high_3_N_1581_2 (to m_clock/clk_500ms)
--------
0.449 (64.4% logic, 35.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_352:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C19D.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R18C19D.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.352ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i0 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/min_set_low_i0_i0 (to m_clock/clk_500ms +)
Delay: 0.457ns (51.2% logic, 48.8% route), 2 logic levels.
Constraint Details:
0.457ns physical path delay m_clock/SLICE_356 to m_clock/SLICE_290 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.352ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_clock/SLICE_290:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C23C.CLK to R20C23C.Q0 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 16 0.223 R20C23C.Q0 to R20C25A.A0 time_min_low_0
CTOF_DEL --- 0.101 R20C25A.A0 to R20C25A.F0 m_clock/SLICE_290
ROUTE 1 0.000 R20C25A.F0 to R20C25A.DI0 m_clock/n2491 (to m_clock/clk_500ms)
--------
0.457 (51.2% logic, 48.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_290:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R20C25A.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/min_set_low_i0_i1 (to m_clock/clk_500ms +)
Delay: 0.508ns (56.9% logic, 43.1% route), 2 logic levels.
Constraint Details:
0.508ns physical path delay m_clock/SLICE_356 to m_clock/SLICE_291 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.301ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_clock/SLICE_291:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 0.219 R20C23C.Q1 to R19C23A.A1 time_min_low_1
CTOOFX_DEL --- 0.156 R19C23A.A1 to R19C23A.OFX0 m_clock/SLICE_291
ROUTE 1 0.000 R19C23A.OFX0 to R19C23A.DI0 m_clock/n2490 (to m_clock/clk_500ms)
--------
0.508 (56.9% logic, 43.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_291:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R19C23A.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
Error: The following path exceeds requirements by 1.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/min_set_low_i0_i1 (to m_clock/clk_500ms +)
Delay: 0.508ns (56.9% logic, 43.1% route), 2 logic levels.
Constraint Details:
0.508ns physical path delay m_clock/SLICE_356 to m_clock/SLICE_291 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.822ns skew requirement (totaling 1.809ns) by 1.301ns
Physical Path Details:
Data path m_clock/SLICE_356 to m_clock/SLICE_291:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C23C.CLK to R20C23C.Q1 m_clock/SLICE_356 (from m_clock/clk_1ms)
ROUTE 14 0.219 R20C23C.Q1 to R19C23A.A0 time_min_low_1
CTOOFX_DEL --- 0.156 R19C23A.A0 to R19C23A.OFX0 m_clock/SLICE_291
ROUTE 1 0.000 R19C23A.OFX0 to R19C23A.DI0 m_clock/n2490 (to m_clock/clk_500ms)
--------
0.508 (56.9% logic, 43.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_clock/SLICE_356:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R20C23C.CLK m_clock/clk_1ms
--------
2.817 (21.4% logic, 78.6% route), 2 logic levels.
Destination Clock Path sys_clk to m_clock/SLICE_291:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R2C16A.CLK sys_clk_c
REG_DEL --- 0.154 R2C16A.CLK to R2C16A.Q0 m_clock/SLICE_278
ROUTE 26 1.098 R2C16A.Q0 to R4C16D.CLK m_clock/clk_1ms
REG_DEL --- 0.154 R4C16D.CLK to R4C16D.Q0 m_clock/SLICE_279
ROUTE 15 1.668 R4C16D.Q0 to R19C23A.CLK m_clock/clk_500ms
--------
4.639 (16.3% logic, 83.7% route), 3 logic levels.
================================================================================
Preference: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ;
59 items scored, 3 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.244ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.384ns (60.9% logic, 39.1% route), 2 logic levels.
Constraint Details:
0.384ns physical path delay m_DS18B20Z/SLICE_172 to m_DS18B20Z/SLICE_171 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.244ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_172 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5D.CLK to R18C5D.Q0 m_DS18B20Z/SLICE_172 (from sys_clk_c)
ROUTE 57 0.150 R18C5D.Q0 to R18C4A.D0 m_DS18B20Z/state_0
CTOF_DEL --- 0.101 R18C4A.D0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
0.384 (60.9% logic, 39.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_172:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5D.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Error: The following path exceeds requirements by 0.028ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.589ns (49.1% logic, 50.9% route), 2 logic levels.
Constraint Details:
0.589ns physical path delay m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.024ns CE_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.617ns) by 0.028ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5A.CLK to R18C5A.Q0 m_DS18B20Z/SLICE_173 (from sys_clk_c)
ROUTE 50 0.152 R18C5A.Q0 to R18C4C.C1 m_DS18B20Z/state_1
CTOOFX_DEL --- 0.156 R18C4C.C1 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.148 R18C4C.OFX0 to R18C4A.CE m_DS18B20Z/one_wire_N_283 (to m_DS18B20Z/clk_1mhz)
--------
0.589 (49.1% logic, 50.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_173:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Error: The following path exceeds requirements by 0.008ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.620ns (54.0% logic, 46.0% route), 3 logic levels.
Constraint Details:
0.620ns physical path delay m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.008ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5A.CLK to R18C5A.Q0 m_DS18B20Z/SLICE_173 (from sys_clk_c)
ROUTE 50 0.152 R18C5A.Q0 to R18C4D.C1 m_DS18B20Z/state_1
CTOF_DEL --- 0.101 R18C4D.C1 to R18C4D.F1 m_DS18B20Z/SLICE_340
ROUTE 1 0.133 R18C4D.F1 to R18C4D.D0 m_DS18B20Z/n9
CTOF_DEL --- 0.101 R18C4D.D0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
0.620 (54.0% logic, 46.0% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_173:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.046ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_init_i0_i2 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.674ns (57.9% logic, 42.1% route), 3 logic levels.
Constraint Details:
0.674ns physical path delay m_DS18B20Z/SLICE_151 to m_DS18B20Z/SLICE_171 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.046ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_151 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R20C5C.CLK to R20C5C.Q0 m_DS18B20Z/SLICE_151 (from sys_clk_c)
ROUTE 15 0.147 R20C5C.Q0 to R18C5B.D0 m_DS18B20Z/cnt_init_2
CTOOFX_DEL --- 0.156 R18C5B.D0 to R18C5B.OFX0 m_DS18B20Z/i23960/SLICE_465
ROUTE 1 0.137 R18C5B.OFX0 to R18C4A.C0 m_DS18B20Z/n26654
CTOF_DEL --- 0.101 R18C4A.C0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
0.674 (57.9% logic, 42.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_151:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5C.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.047ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.675ns (57.8% logic, 42.2% route), 3 logic levels.
Constraint Details:
0.675ns physical path delay m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.047ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5A.CLK to R18C5A.Q0 m_DS18B20Z/SLICE_173 (from sys_clk_c)
ROUTE 50 0.148 R18C5A.Q0 to R18C5B.C0 m_DS18B20Z/state_1
CTOOFX_DEL --- 0.156 R18C5B.C0 to R18C5B.OFX0 m_DS18B20Z/i23960/SLICE_465
ROUTE 1 0.137 R18C5B.OFX0 to R18C4A.C0 m_DS18B20Z/n26654
CTOF_DEL --- 0.101 R18C4A.C0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
0.675 (57.8% logic, 42.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_173:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.047ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.675ns (57.8% logic, 42.2% route), 3 logic levels.
Constraint Details:
0.675ns physical path delay m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.047ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5A.CLK to R18C5A.Q0 m_DS18B20Z/SLICE_173 (from sys_clk_c)
ROUTE 50 0.148 R18C5A.Q0 to R18C5B.C1 m_DS18B20Z/state_1
CTOOFX_DEL --- 0.156 R18C5B.C1 to R18C5B.OFX0 m_DS18B20Z/i23960/SLICE_465
ROUTE 1 0.137 R18C5B.OFX0 to R18C4A.C0 m_DS18B20Z/n26654
CTOF_DEL --- 0.101 R18C4A.C0 to R18C4A.F0 m_DS18B20Z/SLICE_171
ROUTE 1 0.000 R18C4A.F0 to R18C4A.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
0.675 (57.8% logic, 42.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_173:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.055ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.683ns (57.1% logic, 42.9% route), 3 logic levels.
Constraint Details:
0.683ns physical path delay m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_340 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.055ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_173 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R18C5A.CLK to R18C5A.Q0 m_DS18B20Z/SLICE_173 (from sys_clk_c)
ROUTE 50 0.152 R18C5A.Q0 to R18C4C.C1 m_DS18B20Z/state_1
CTOOFX_DEL --- 0.156 R18C4C.C1 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.141 R18C4C.OFX0 to R18C4D.C0 m_DS18B20Z/one_wire_N_283
CTOF_DEL --- 0.101 R18C4D.C0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
0.683 (57.1% logic, 42.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_173:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R18C5A.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.063ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_write_i0_i1 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.691ns (48.5% logic, 51.5% route), 3 logic levels.
Constraint Details:
0.691ns physical path delay m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_340 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.063ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R19C4B.CLK to R19C4B.Q1 m_DS18B20Z/SLICE_156 (from sys_clk_c)
ROUTE 15 0.223 R19C4B.Q1 to R18C4D.A1 m_DS18B20Z/cnt_write_1
CTOF_DEL --- 0.101 R18C4D.A1 to R18C4D.F1 m_DS18B20Z/SLICE_340
ROUTE 1 0.133 R18C4D.F1 to R18C4D.D0 m_DS18B20Z/n9
CTOF_DEL --- 0.101 R18C4D.D0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
0.691 (48.5% logic, 51.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_156:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R19C4B.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.076ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_write_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.693ns (41.7% logic, 58.3% route), 2 logic levels.
Constraint Details:
0.693ns physical path delay m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_171 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.024ns CE_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.617ns) by 0.076ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_156 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R19C4B.CLK to R19C4B.Q0 m_DS18B20Z/SLICE_156 (from sys_clk_c)
ROUTE 16 0.256 R19C4B.Q0 to R18C4C.D0 m_DS18B20Z/cnt_write_0
CTOOFX_DEL --- 0.156 R18C4C.D0 to R18C4C.OFX0 m_DS18B20Z/state_2__I_0_181_i7/SLICE_463
ROUTE 2 0.148 R18C4C.OFX0 to R18C4A.CE m_DS18B20Z/one_wire_N_283 (to m_DS18B20Z/clk_1mhz)
--------
0.693 (41.7% logic, 58.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_156:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R19C4B.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4A.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Passed: The following path meets requirements by 0.077ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_write_i0_i2 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.705ns (47.5% logic, 52.5% route), 3 logic levels.
Constraint Details:
0.705ns physical path delay m_DS18B20Z/SLICE_157 to m_DS18B20Z/SLICE_340 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.641ns skew requirement (totaling 0.628ns) by 0.077ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_157 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R19C4D.CLK to R19C4D.Q0 m_DS18B20Z/SLICE_157 (from sys_clk_c)
ROUTE 15 0.147 R19C4D.Q0 to R19C4A.D1 m_DS18B20Z/cnt_write_2
CTOF_DEL --- 0.101 R19C4A.D1 to R19C4A.F1 m_DS18B20Z/SLICE_974
ROUTE 1 0.223 R19C4A.F1 to R18C4D.B0 m_DS18B20Z/n10
CTOF_DEL --- 0.101 R18C4D.B0 to R18C4D.F0 m_DS18B20Z/SLICE_340
ROUTE 1 0.000 R18C4D.F0 to R18C4D.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
0.705 (47.5% logic, 52.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path sys_clk to m_DS18B20Z/SLICE_157:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R19C4D.CLK sys_clk_c
--------
1.565 (28.7% logic, 71.3% route), 1 logic levels.
Destination Clock Path sys_clk to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.449 C1.PAD to C1.PADDI sys_clk
ROUTE 262 1.116 C1.PADDI to R20C5A.CLK sys_clk_c
REG_DEL --- 0.154 R20C5A.CLK to R20C5A.Q0 m_DS18B20Z/SLICE_145
ROUTE 12 0.487 R20C5A.Q0 to R18C4D.CLK m_DS18B20Z/clk_1mhz
--------
2.206 (27.3% logic, 72.7% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clk_c" 103.756000 | | |
MHz ; | 0.000 ns| 0.304 ns| 1
| | |
FREQUENCY NET "m_uart_tx/clk_en" | | |
112.880000 MHz ; | 0.000 ns| -1.224 ns| 2 *
| | |
FREQUENCY NET "m_uart_tx/clk_uart" | | |
203.957000 MHz ; | 0.000 ns| 0.380 ns| 2
| | |
FREQUENCY NET "m_clock/clk_1ms" | | |
217.297000 MHz ; | 0.000 ns| 0.377 ns| 2
| | |
FREQUENCY NET "m_clock/clk_500ms" | | |
136.986000 MHz ; | 0.000 ns| -1.420 ns| 2 *
| | |
FREQUENCY NET "m_DS18B20Z/clk_1mhz" | | |
293.858000 MHz ; | 0.000 ns| -0.244 ns| 2 *
| | |
----------------------------------------------------------------------------
3 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
m_clock/n25024 | 2| 192| 14.05%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 16 clocks:
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Data transfers from: