Definition at line 5291 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_8 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5309 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_9 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5327 of file Nano100Series.h.
| __IO uint32_t USBD_EP_T::MXPLD |
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | MXPLD | Maximal Payload |
| It is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). | ||
| It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. | ||
| (1). When the register is written by CPU, | ||
| For IN token, the value of MXPLD is used to define the length of data to be transmitted and indicate the data buffer is ready. | ||
| For OUT token, it means that the controller is ready to receive data from host and the value of MXPLD is the maximal data length comes from host. | ||
| (2). When the register is read by CPU, | ||
| For IN token, the value of MXPLD is indicated the length of data be transmitted to host | ||
| For OUT token, the value of MXPLD is indicated the actual length of data receiving from host. | ||
| Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. |
Definition at line 10873 of file Nano100Series.h.
| __IO uint32_t INTR_T::NMI_SEL |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | NMI_SEL | The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0] |
| The NMI_SEL bit[4:0] used to select the NMI interrupt source |
Definition at line 5009 of file Nano100Series.h.
| __IO uint32_t PWM_T::OE |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CH0_OE | PWM CH0 Output Enable Register |
| 0 = PWM CH0 output to pin Disabled. | ||
| 1 = PWM CH0 output to pin Enabled. | ||
| Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [1] | CH1_OE | PWM CH1 Output Enable Register |
| 0 = PWM CH1 output to pin Disabled. | ||
| 1 = PWM CH1 output to pin Enabled. | ||
| Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [2] | CH2_OE | PWM CH2 Output Enable Register |
| 0 = PWM CH2 output to pin Disabled. | ||
| 1 = PWM CH2 output to pin Enabled. | ||
| Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [3] | CH3_OE | PWM CH3 Output Enable Register |
| 0 = PWM CH3 output to pin Disabled. | ||
| 1 = PWM CH3 output to pin Enabled. | ||
| Note: The corresponding GPI/O pin also must be switched to PWM function (refer to GPx_MFP) |
Definition at line 6777 of file Nano100Series.h.
| __IO uint32_t GPIO_T::OFFD |
| Bits | Field | Descriptions |
|---|---|---|
| [31:16] | OFFD | GPIO Port [X] Pin [N] Digital Input Path Disable |
| Determine if the digital input path of GPIO port [x] pin [n] is disabled. | ||
| 0 = Digital input path of GPIO port [x] pin [n] Enabled. | ||
| 1 = Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low). | ||
| Note: For GPIOF_OFFD, bits [31:22] are reserved. |
Definition at line 3552 of file Nano100Series.h.
| __IO uint32_t SYS_T::PA_H_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PA8_MFP | PA.8 Pin Function Selection |
| 001 = I2C0 SDA | ||
| 011 = SmartCard0 clock | ||
| 100 = SPI2 1st slave select pin | ||
| 111 = LCD SEG 20 | ||
| Others = GPIOA[8] | ||
| [6:4] | PA9_MFP | PA.9 Pin Function Selection |
| 001 = I2C0 SCL | ||
| 011 = SmartCard0 DATA | ||
| 100 = SPI2 SCLK | ||
| 111 = LCD SEG 21 | ||
| Others = GPIOA[9] | ||
| [10:8] | PA10_MFP | PA.10 Pin Function Selection |
| 001 = I2C1 SDA | ||
| 010 = EBI nWR | ||
| 011 = SmartCard0 Power | ||
| 100 = SPI2 MISO0 | ||
| 111 = LCD SEG 22 | ||
| Others = GPIOA[10] | ||
| [14:12] | PA11_MFP | PA.11 Pin Function Selection |
| 001 = I2C1 SCL | ||
| 010 = EBI nRE | ||
| 011 = SmartCard0 RST | ||
| 100 = SPI2 MOSI0 | ||
| 111 = LCD SEG 23 | ||
| Others = GPIOA[11] | ||
| [18:16] | PA12_MFP | PA.12 Pin Function Selection |
| 001 = PWM0 Channel 0 | ||
| 010 = EBI AD[13] | ||
| 011 = Timer0 capture event | ||
| 101 = I2C0 SDA | ||
| Others = GPIOA[12] | ||
| [22:20] | PA13_MFP | PA.13 Pin Function Selection |
| 001 = PWM0 Channel 1 | ||
| 010 = EBI AD[14] | ||
| 011 = Timer1 capture event | ||
| 101 = I2C0 SCL | ||
| Others = GPIOA[13] | ||
| [26:24] | PA14_MFP | PA.14 Pin Function Selection |
| 001 = PWM0 Channel 2 | ||
| 010 = EBI AD[15] | ||
| 011 = Timer2 capture event | ||
| 110 = UART0 RX | ||
| Others = GPIOA[14] | ||
| [30:28] | PA15_MFP | PA.15 Pin Function Selection |
| 001 = PWM0 Channel 3 | ||
| 010 = I2S MCLK | ||
| 011 = Timer3 capture event | ||
| 100 = SmartCard 0 power | ||
| 110 = UART0 TX | ||
| Others = GPIOA[15] |
Definition at line 2292 of file Nano100Series.h.
| __IO uint32_t SYS_T::PA_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PA0_MFP | PA.0 Pin Function Selection |
| 001 = ADC input channel 0 | ||
| 100 = SmartCard 2 card detect | ||
| Others = GPIOA[0] | ||
| [6:4] | PA1_MFP | PA.1 Pin Function Selection |
| 001 = ADC input channel 1 | ||
| 010 = EBI AD[12] | ||
| Others = GPIOA[1] | ||
| [10:8] | PA2_MFP | PA.2 Pin Function Selection |
| 001 = ADC input channel 2 | ||
| 010 = EBI AD[11] | ||
| 101 = UART1_RXD | ||
| Others = GPIOA[2] | ||
| [14:12] | PA3_MFP | PA.3 Pin Function Selection |
| 001 = ADC input channel 3 | ||
| 010 = EBI AD[10] | ||
| 101 = UART1_TXD | ||
| Others = GPIOA[3] | ||
| [18:16] | PA4_MFP | PA.4 Pin Function Selection |
| 001 = ADC input channel 4 | ||
| 010 = EBI AD[9] | ||
| 100 = SmartCard 2 power | ||
| 101 = I2C0 SDA | ||
| 111 = LCD SEG 39 | ||
| Others = GPIOA[4] | ||
| [22:20] | PA5_MFP | PA.5 Pin Function Selection |
| 001 = ADC input channel 5 | ||
| 010 = EBI AD[8] | ||
| 100 = SmartCard2 RST | ||
| 101 = I2C0 SCL | ||
| 111 = LCD SEG 38 | ||
| Others = GPIOA[5] | ||
| [26:24] | PA6_MFP | PA.6 Pin Function Selection |
| 001 = ADC input channel 6 | ||
| 010 = EBI AD[7] | ||
| 011 = Timer 3 Capture event | ||
| 100 = SmartCard 2 clock | ||
| 101 = PWM0 Channel 3 | ||
| 111 = LCD SEG 37 | ||
| Others = GPIOA[6] | ||
| [30:28] | PA7_MFP | PA.7 Pin Function Selection |
| 001 = ADC input channel 7 | ||
| 010 = EBI AD[6] | ||
| 011 = Timer 2 capture event | ||
| 100 = SmartCard 2 data pin | ||
| 101 = PWM0 Channel 2 | ||
| 111 = LCD SEG 36 | ||
| Others = GPIOA[7] |
Definition at line 2231 of file Nano100Series.h.
| __IO uint32_t SYS_T::PB_H_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PB8_MFP | PB.8 Pin Function Selection |
| 001 = ADC external trigger | ||
| 010 = Timer0 external event input or Timer0 toggle output | ||
| 011 = External interrupt 0 | ||
| 100 = SmartCard 2 power | ||
| 111 = LCD SEG 30 | ||
| Others = GPIOB[8] | ||
| [6:4] | PB9_MFP | PB.9 Pin Function Selection |
| 001 = SPI1 2nd slave select pin | ||
| 010 = Timer1 external event input or Timer1 toggle output | ||
| 100 = SmartCard 2 RST | ||
| 101 = External interrupt 0 | ||
| 111 = LCD V1 | ||
| Others = GPIOB[9] | ||
| [10:8] | PB10_MFP | PB.10 Pin Function Selection |
| 001 = SPI0 2nd slave select pin | ||
| 010 = Timer2 external event input or Timer2 toggle output | ||
| 100 = SmartCard 2 clock | ||
| 101 = SPI0 MOSI0 | ||
| 111 = LCD V2 | ||
| Others = GPIOB[10] | ||
| [14:12] | PB11_MFP | PB.11 Pin Function Selection |
| 001 = PWM1 Channel 0 | ||
| 010 = Timer3 external event input or Timer3 toggle output | ||
| 100 = SmartCard 2 DATA | ||
| 101 = SPI0 MISO0 | ||
| 111 = LCD V3 | ||
| Others = GPIOB[11] | ||
| [18:16] | PB12_MFP | PB.12 Pin Function Selection |
| 010 = EBI AD[0] | ||
| 100 = FRQDIV_CLK | ||
| 111 = LCD SEG 24 | ||
| Others = GPIOB[12] | ||
| [22:20] | PB13_MFP | PB.13 Pin Function Selection |
| 010 = EBI AD[1] | ||
| 111 = LCD SEG 25 | ||
| Others = GPIOB[13] | ||
| [26:24] | PB14_MFP | PB.14 Pin Function Selection |
| 001 = External interrupt 0 | ||
| 011 = SmartCard 2 card detect | ||
| 100 = SPI2 2nd slave select pin | ||
| 111 = LCD SEG 26 | ||
| Others = GPIOB[14] | ||
| [30:28] | PB15_MFP | PB.15 Pin Function Selection |
| 001 = External interrupt 1 | ||
| 011 = Snooper pin | ||
| 100 = SmartCard1 card detect | ||
| 111 = LCD SEG 31 | ||
| Others = GPIOB[15] |
Definition at line 2407 of file Nano100Series.h.
| __IO uint32_t SYS_T::PB_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PB0_MFP | PB.0 Pin Function Selection |
| 001 = UART0 RX | ||
| 011 = SPI1 MOSI0 | ||
| 111 = LCD SEG 7 | ||
| Others = GPIOB[0] | ||
| [6:4] | PB1_MFP | PB.1 Pin Function Selection |
| 001 = UART0 TX | ||
| 011 = SPI1 MISO0 | ||
| 111 = LCD SEG 6 | ||
| Others = GPIOB[1] | ||
| [10:8] | PB2_MFP | PB.2 Pin Function Selection |
| 001 = UART0 RTSn | ||
| 010 = EBI nWRL | ||
| 011 = SPI1 SCLK | ||
| 111 = LCD SEG 5 | ||
| Others = GPIOB[2] | ||
| [14:12] | PB3_MFP | PB.3 Pin Function Selection |
| 001 = UART0 CTSn | ||
| 010 = EBI nWRH | ||
| 011 = SPI1 1st slave select pin | ||
| 111 = LCD SEG 4 | ||
| Others = GPIOB[3] | ||
| [18:16] | PB4_MFP | PB.4 Pin Function Selection |
| 001 = UART1 RX | ||
| 011 = SmartCard0 card detection | ||
| 100 = SPI2 1st slave select pin | ||
| 111 = LCD SEG 13 | ||
| Others = GPIOB[4] | ||
| [22:20] | PB5_MFP | PB.5 Pin Function Selection |
| 001 = UART1 TX | ||
| 011 = SmartCard0 RST | ||
| 100 = SPI2 SCLK | ||
| 111 = LCD SEG 12 | ||
| Others = GPIOB[5] | ||
| [26:24] | PB6_MFP | PB.6 Pin Function Selection |
| 001 = UART1 RTSn | ||
| 010 = EBI ALE | ||
| 100 = SPI2 MISO0 | ||
| 111 = LCD SEG 11 | ||
| Others = GPIOB[6] | ||
| [30:28] | PB7_MFP | PB.7 Pin Function Selection |
| 001 = UART1 CTSn | ||
| 010 = EBI nCS | ||
| 100 = SPI2 MOSI0 | ||
| 111 = LCD SEG 10 | ||
| Others = GPIOB[7] |
Definition at line 2348 of file Nano100Series.h.
| __IO uint32_t SYS_T::PC_H_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PC8_MFP | PC.8 Pin Function Selection |
| 001 = SPI1 1st slave select pin | ||
| 010 = EBI MCLK | ||
| 101 = I2C1 SDA | ||
| Others = GPIOC[8] | ||
| [6:4] | PC9_MFP | PC.9 Pin Function Selection |
| 001 = SPI1 SCLK | ||
| 101 = I2C1 SCL | ||
| Others = GPIOC[9] | ||
| [10:8] | PC10_MFP | PC.10 Pin Function Selection |
| 001 = SPI1 MISO0 | ||
| 101 = UART1 RX | ||
| Others = GPIOC[10] | ||
| [14:12] | PC11_MFP | PC.11 Pin Function Selection |
| 001 = SPI1 MOSI0 | ||
| 101 = UART1 TX | ||
| Others = GPIOC[11] | ||
| [18:16] | PC12_MFP | PC.12 Pin Function Selection |
| 001 = SPI1 MISO1 | ||
| 010 = PWM1 Channel 0 | ||
| 101 = External interrupt 0 | ||
| 110 = I2C0 SDA | ||
| Others = GPIOC[12] | ||
| [22:20] | PC13_MFP | PC.13 Pin Function Selection |
| 001 = SPI1 MOSI1 | ||
| 010 = PWM1 Channel 1 | ||
| 100 = Snooper pin | ||
| 101 = External interrupt 1 | ||
| 110 = I2C0 SCL | ||
| Others = GPIOC[13] | ||
| [26:24] | PC14_MFP | PC.14 Pin Function Selection |
| 010 = EBI AD[2] | ||
| 100 = PWM1 Channel 3 | ||
| 111 = LCD SEG 32 | ||
| Others = GPIOC[14] | ||
| [30:28] | PC15_MFP | PC.15 Pin Function Selection |
| 010 = EBI AD[3] | ||
| 011 = Timer0 capture event | ||
| 100 = PWM1 Channel 2 | ||
| 111 = LCD SEG 33 | ||
| Others = GPIOC[15] |
Definition at line 2513 of file Nano100Series.h.
| __IO uint32_t SYS_T::PC_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PC0_MFP | PC.0 Pin Function Selection |
| 001 = SPI0 1st slave select pin | ||
| 010 = I2S WS | ||
| 100 = SmartCard1 clock | ||
| 111 = LCD DH1 | ||
| Others = GPIOC[0] | ||
| [6:4] | PC1_MFP | PC.1 Pin Function Selection |
| 001 = SPI0 SCLK | ||
| 010 = I2S BCLK | ||
| 100 = SmartCard1 DATA | ||
| 111 = LCD DH2 | ||
| Others = GPIOC[1] | ||
| [10:8] | PC2_MFP | PC.2 Pin Function Selection |
| 001 = SPI0 MISO0 | ||
| 010 = I2S Din | ||
| 100 = SmartCard1 Power | ||
| 111 = LCD COM 0 | ||
| Others = GPIOC[2] | ||
| [14:12] | PC3_MFP | PC.3 Pin Function Selection |
| 001 = SPI0 MOSI1 | ||
| 010 = I2S Dout | ||
| 100 = SmartCard1 RST | ||
| 111 = LCD COM 1 | ||
| Others = GPIOC[3] | ||
| [18:16] | PC4_MFP | PC.4 Pin Function Selection |
| 001 = SPI0 MISO1 | ||
| 111 = LCD COM 2 | ||
| Others = GPIOC[4] | ||
| [22:20] | PC5_MFP | PC.5 Pin Function Selection |
| 001 = SPI0 MOSI1 | ||
| 111 = LCD COM 3 | ||
| Others = GPIOC[5] | ||
| [26:24] | PC6_MFP | PC.6 Pin Function Selection |
| 001 = DA out0 | ||
| 010 = EBI AD[4] | ||
| 011 = Timer0 capture event | ||
| 100 = SmartCard1 card detection | ||
| 101 = PWM0 Channel 0 | ||
| Others = GPIOC[6] | ||
| [30:28] | PC7_MFP | PC.7 Pin Function Selection |
| 001 = DA out1 | ||
| 010 = EBI AD[5] | ||
| 011 = Timer1 capture event | ||
| 101 = PWM0 Channel 1 | ||
| Others = GPIOC[7] |
Definition at line 2462 of file Nano100Series.h.
| __IO uint32_t SYS_T::PD_H_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PD8_MFP | PD.8 Pin Function Selection |
| 111 = LCD SEG 19 | ||
| Others = GPIOD[8] | ||
| [6:4] | PD9_MFP | PD.9 Pin Function Selection |
| 111 = LCD SEG 18 | ||
| Others = GPIOD[9] | ||
| [10:8] | PD10_MFP | PD.10 Pin Function Selection |
| 111 = LCD SEG 17 | ||
| Others = GPIOD[10] | ||
| [14:12] | PD11_MFP | PD.11 Pin Function Selection |
| 111 = LCD SEG 16 | ||
| Others = GPIOD[11] | ||
| [18:16] | PD12_MFP | PD.12 Pin Function Selection |
| 111 = LCD SEG 15 | ||
| Others = GPIOD[12] | ||
| [22:20] | PD13_MFP | PD.13 Pin Function Selection |
| 111 = LCD SEG 14 | ||
| Others = GPIOD[13] | ||
| [26:24] | PD14_MFP | PD.14 Pin Function Selection |
| 111 = LCD SEG 1 | ||
| Others = GPIOD[14] | ||
| [30:28] | PD15_MFP | PD.15 Pin Function Selection |
| 111 = LCD SEG 0 | ||
| Others = GPIOD[15] |
Definition at line 2600 of file Nano100Series.h.
| __IO uint32_t SYS_T::PD_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PD0_MFP | PD.0 Pin Function Selection |
| 001 = UART1 RX | ||
| 011 = SPI2 1st slave select pin | ||
| 100 = SmartCard1 clock | ||
| 101 = ADC input channel8 | ||
| Others = GPIOD[0] | ||
| [6:4] | PD1_MFP | PD.1 Pin Function Selection |
| 001 = UART1 TX | ||
| 011 = SPI2 SCLK | ||
| 100 = SmartCard1 DATA | ||
| 101 = ADC input channel9 | ||
| Others = GPIOD[1] | ||
| [10:8] | PD2_MFP | PD.2 Pin Function Selection |
| 001 = UART1 RTSn | ||
| 010 = I2S WS | ||
| 011 = SPI2 MISO0 | ||
| 100 = SmartCard1 power | ||
| 101 = ADC input channel10 | ||
| Others = GPIOD[2] | ||
| [14:12] | PD3_MFP | PD.3 Pin Function Selection |
| 001 = UART1 CTSn | ||
| 010 = I2S BCLK | ||
| 011 = SPI2 MOSI0 | ||
| 100 = SmartCard1 reset | ||
| 101 = ADC input channel11 | ||
| Others = GPIOD[3] | ||
| [18:16] | PD4_MFP | PD.4 Pin Function Selection |
| 010 = I2S Din | ||
| 011 = SPI2 MISO1 | ||
| 100 = SmartCard1 card detection | ||
| 111 = LCD SEG 35 | ||
| Others = GPIOD[4] | ||
| [22:20] | PD5_MFP | PD.5 Pin Function Selection |
| 010 = I2S Dout | ||
| 011 = SPI2 MOSI1 | ||
| 111 = LCD SEG 34 | ||
| Others = GPIOD[5] | ||
| [26:24] | PD6_MFP | PD.6 Pin Function Selection |
| 111 = LCD SEG 3 | ||
| Others = GPIOD[6] | ||
| [30:28] | PD7_MFP | PD.7 Pin Function Selection |
| 111 = LCD SEG 2 | ||
| Others = GPIOD[7] |
Definition at line 2566 of file Nano100Series.h.
| __I uint32_t SYS_T::PDID |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDID | Part Device ID |
| This register reflects device part number code. | ||
| Software can read this register to identify which device is used. |
Definition at line 2008 of file Nano100Series.h.
| __I uint32_t ADC_T::PDMA |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | AD_PDMA | ADC PDMA Current Transfer Data Register |
| When PDMA transferring, read this register can monitor current PDMA transfer data. | ||
| This is a read only register. |
Definition at line 452 of file Nano100Series.h.
| __IO uint32_t USBD_T::PDMA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PDMA_RW | PDMA_RW |
| 0 = The PDMA will read data from memory to USB buffer. | ||
| 1 = The PDMA will read data from USB buffer to memory. | ||
| [1] | PDMA_TRG | Active PDMA Function |
| 0 = The PDMA function is not active. | ||
| 1 = The PDMA function in USB is active. | ||
| This bit will be automatically cleared after PDMA transfer done. | ||
| [2] | BYTEM | CPU Access USB SRAM Size Mode Select |
| 0 = Word Mode: The size of the transfer from CPU to USB SRAM is Word order. | ||
| 1 = Byte Mode: The size of the transfer from CPU to USB SRAM is Byte order. | ||
| [3] | PDMA_RST | PDMA Reset |
| It is used to reset the USB PDMA function into default state. | ||
| 0 = No Reset PDMA Reset Disable. | ||
| 1 = Reset the PDMA function in this controller. | ||
| Note: it is auto cleared to 0 after the reset function done. |
Definition at line 11153 of file Nano100Series.h.
| __I uint32_t PWM_T::PDMACH0 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | Captureddata7_0 | PDMACH0 |
| When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0 | ||
| When CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0 | ||
| [15:8] | Captureddata15_8 | PDMACH0 |
| When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0 | ||
| When CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0 | ||
| [23:16] | Captureddata23_16 | PDMACH0 |
| When CH01CASK is disabled, this byte is 0 | ||
| When CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0 | ||
| [31:24] | Captureddata31_24 | PDMACH0 |
| When CH01CASK is disabled, this byte is 0 | ||
| When CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0 |
Definition at line 7323 of file Nano100Series.h.
| __I uint32_t PWM_T::PDMACH2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | Captureddata7_0 | PDMACH0 |
| When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2 | ||
| When CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2 | ||
| [15:8] | Captureddata15_8 | PDMACH0 |
| When CH23CASK is disabled, it is the capturing value(CFL2/CRL2) for channel 2 | ||
| When CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2 | ||
| [23:16] | Captureddata23_16 | PDMACH0 |
| When CH23CASK is disabled, this byte is 0 | ||
| When CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2 | ||
| [31:24] | Captureddata31_24 | PDMACH0 |
| When CH23CASK is disabled, this byte is 0 | ||
| When CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2 |
Definition at line 7345 of file Nano100Series.h.
| __IO uint32_t SYS_T::PE_H_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PE8_MFP | PE.8 Pin Function Selection |
| 111 = LCD SEG 9 | ||
| Others = GPIOE[8] | ||
| [6:4] | PE9_MFP | PE.9 Pin Function Selection |
| 111 = UART1 RX | ||
| Others = GPIOE[9] | ||
| [10:8] | PE10_MFP | PE.10 Pin Function Selection |
| 111 = UART1 TX | ||
| Others = GPIOE[10] | ||
| [14:12] | PE11_MFP | PE.11 Pin Function Selection |
| 111 = UART1 RTSn | ||
| Others = GPIOE[11] | ||
| [18:16] | PE12_MFP | PE.12 Pin Function Selection |
| 111 = UART1 CTSn | ||
| Others = GPIOE[12] | ||
| [22:20] | PE13_MFP | PE.13 Pin Function Selection |
| 111 = LCD SEG 27 | ||
| Others = GPIOE[13] | ||
| [26:24] | PE14_MFP | PE.14 Pin Function Selection |
| 111 = LCD SEG 28 | ||
| Others = GPIOE[14] | ||
| [30:28] | PE15_MFP | PE.15 Pin Function Selection |
| 111 = LCD SEG 2 | ||
| Others = GPIOE[15] |
Definition at line 2669 of file Nano100Series.h.
| __IO uint32_t SYS_T::PE_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PE0_MFP | PE.0 Pin Function Selection |
| 001 = PWM1 Channel 2 | ||
| 010 = I2S MCLK | ||
| Others = GPIOE[0] | ||
| [6:4] | PE1_MFP | PE.1 Pin Function Selection |
| 001 = PWM1 Channel 3 | ||
| 110 = SPI0 1st slave select pin | ||
| Others = GPIOE[1] | ||
| [10:8] | PE2_MFP | PE.2 Pin Function Selection |
| 110 = SPI0 SCLK | ||
| Others = GPIOE[2] | ||
| [14:12] | PE3_MFP | PE.3 Pin Function Selection |
| 110 = SPI0 MISO0 | ||
| Others = GPIOE[3] | ||
| [18:16] | PE4_MFP | PE.4 Pin Function Selection |
| 110 = SPI0 MOSI0 | ||
| Others = GPIOE[4] | ||
| [22:20] | PE5_MFP | PE.5 Pin Function Selection |
| 001 = PWM1 Channel 1 | ||
| Others = GPIOE[5] | ||
| [26:24] | PE6_MFP | PE.6 Pin Function Selection |
| GPIOE[6] | ||
| [30:28] | PE7_MFP | PE.7 Pin Function Selection |
| 111 = LCD SEG 8 | ||
| Others = GPIOE[7] |
Definition at line 2635 of file Nano100Series.h.
| __IO uint32_t SYS_T::PF_L_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | PF0_MFP | PF.0 Pin Function Selection |
| 101 = External interrupt 0 | ||
| 111 = ICE DATA | ||
| Others = GPIOF[1] | ||
| [6:4] | PF1_MFP | PF.1 Pin Function Selection |
| 100 = FRQDIV_CLK | ||
| 101 = External interrupt 1 | ||
| 111 = ICE CLOCK | ||
| Others = GPIOF[1] | ||
| [10:8] | PF2_MFP | PF.2 Pin Function Selection |
| 111 = HXT OUT | ||
| Others = GPIOF[2] | ||
| [14:12] | PF3_MFP | PF.3 Pin Function Selection |
| 111 = HXT IN | ||
| Others = GPIOF[3] | ||
| [18:16] | PF4_MFP | PF.4 Pin Function Selection |
| 001 = I2C0 SDA | ||
| Others = GPIOF[4] | ||
| [22:20] | PF5_MFP | PF.5 Pin Function Selection |
| 001 = I2C0 SCL | ||
| Others = GPIOF[5] |
Definition at line 2700 of file Nano100Series.h.
| __I uint32_t GPIO_T::PIN |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PIN | GPIO Port [X] Pin [N] Value |
| The value read from each of these bit reflects the actual status of the respective GPI/O pin | ||
| Note: For GPIOF_PIN, bits [15:6] are reserved. |
Definition at line 3599 of file Nano100Series.h.
| __IO uint32_t SC_T::PINCSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | POW_EN | SC_POW_EN Pin Signal |
| This bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit. | ||
| 0 = Drive SC_POW_EN pin to low. | ||
| 1 = Drive SC_POW_EN pin to high. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field When operating in these modes. | ||
| [1] | SC_RST | SC_RST Pin Signal |
| This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit. | ||
| 0 = Drive SC_RST pin to low. | ||
| 1 = Drive SC_RST pin to high. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field When operating in these modes. | ||
| [2] | CD_REM_F | Card Detect Removal Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been removal. | ||
| 0 = No effect. | ||
| 1 = Card Removal. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: Card detect engine will start after SC_CTL [SC_CEN] set. | ||
| [3] | CD_INS_F | Card Detect Insert Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been inserted. | ||
| 0 = No effect. | ||
| 1 = Card insert. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: Card detect engine will start after SC_CTL [SC_CEN] set. | ||
| [4] | CD_PIN_ST | Card Detect Status Of SC_CD Pin Status (Read Only) |
| This bit is the pin status flag of SC_CD | ||
| 0 = SC_CD pin state at low. | ||
| 1 = SC_CD pin state at high. | ||
| [6] | CLK_KEEP | SC Clock Enable |
| 0 = SC clock generation Disabled. | ||
| 1 = SC clock always keeps free running. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when operation in these modes. | ||
| [7] | ADAC_CD_EN | Auto Deactivation When Card Removal |
| 0 = Auto deactivation Disabled when hardware detected the card is removal. | ||
| 1 = Auto deactivation Enabled when hardware detected the card is removal. | ||
| Note1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting). | ||
| If this process completes. | ||
| Hardware will generate an interrupt INT_INIT to CPU. | ||
| [8] | SC_OEN_ST | SC Data Pin Output Enable Status (Read Only) |
| 0 = SC data output enable pin status is at low. | ||
| 1 = SC data output enable pin status is at high. | ||
| [9] | SC_DATA_O | Output Of SC Data Pin |
| This bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit. | ||
| 0 = Drive SC data output pin to low. | ||
| 1 = Drive SC data output pin to high. | ||
| Note: When SC is at activation, warm re set or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when SC is in these modes. | ||
| [10] | CD_LEV | Card Detect Level |
| 0 = When hardware detects the card detect pin from high to low, it indicates a card is detected. | ||
| 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
| Note: Software must select card detect level before Smart Card engine enable | ||
| [11] | POW_INV | SC_POW Pin Inverse |
| This bit is used for inverse the SC_POW pin. | ||
| There are four kinds of combination for SC_POW pin setting by POW_INV and | ||
| POW_EN(SC_PINCSR[0]). POW_INV is bit 1 and POW_EN is bit 0 for SC_POW_Pin as | ||
| high or low voltage selection. | ||
| POW_INV is 0 and POW_EN is 0, than SC_POW Pin output 0. | ||
| POW_INV is 0 and POW_EN is 1, than SC_POW Pin output 1. | ||
| POW_INV is 1 and POW_EN is 0, than SC_POW Pin output 1. | ||
| POW_INV is 1 and POW_EN is 1, than SC_POW Pin output 0. | ||
| Note: Software must select POW_INV before Smart Card is enabled by SC_CEN (SC_CTL[0]) | ||
| [16] | SC_DATA_I_ST | SC Data Input Pin Status (Read Only) |
| This bit is the pin status of SC_DATA_I | ||
| 0 = The SC_DATA_I pin is low. | ||
| 1 = The SC_DATA_I pin is high. |
Definition at line 8785 of file Nano100Series.h.
| __IO uint32_t CLK_T::PLLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | FB_DV | PLL Feedback Divider Control Pins |
| Refer to the formulas below the table. | ||
| The range of FB_DV is from 0 to 63. | ||
| [9:8] | IN_DV | PLL Input Divider Control Pins |
| Refer to the formulas below the table. | ||
| [12] | OUT_DV | PLL Output Divider Control Pins |
| Refer to the formulas below the table. This bit MUST be 0 for PLL output low deviation. | ||
| [16] | PD | Power-Down Mode |
| If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too | ||
| 0 = PLL is in normal mode. | ||
| 1 = PLL is in power-down mode (default). | ||
| [17] | PLL_SRC | PLL Source Clock Select |
| 0 = PLL source clock from HXT. | ||
| 1 = PLL source clock from HIRC. |
Definition at line 1129 of file Nano100Series.h.
| __IO uint32_t GPIO_T::PMD |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | PMD0 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [3:2] | PMD1 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [5:4] | PMD2 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [7:6] | PMD3 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [9:8] | PMD4 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [11:10] | PMD5 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [13:12] | PMD6 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [15:14] | PMD7 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [17:16] | PMD8 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [19:18] | PMD9 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [21:20] | PMD10 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [23:22] | PMD11 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [25:24] | PMD12 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [27:26] | PMD13 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [29:28] | PMD14 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. | ||
| [31:30] | PMD15 | GPIO Port [X] Pin [N] Mode Control |
| Determine the I/O type of GPIO port [x] pin [n] | ||
| 00 = GPIO port [x] pin [n] is in INPUT mode. | ||
| 01 = GPIO port [x] pin [n] is in OUTPUT mode. | ||
| 10 = GPIO port [x] pin [n] is in Open-Drain mode. | ||
| 11 = Reserved. | ||
| Note: For GPIOF_PMD, PMD6 ~ PMD15 are reserved. |
Definition at line 3537 of file Nano100Series.h.
| __IO uint32_t SYS_T::PORCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | POR_DIS_CODE | Power-On Reset Enable Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. | ||
| If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function. |
Definition at line 2716 of file Nano100Series.h.
| __IO uint32_t TIMER_T::PRECNT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PRESCALE_CNT | Pre-Scale Counter |
| Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter. | ||
| If PRESCALE_CNT =0, then there is no scaling. |
Definition at line 9898 of file Nano100Series.h.
| __IO uint32_t PWM_T::PRES |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CP01 | Clock Prescaler 0 For PWM Timer 0 & 1 |
| Clock input is divided by (CP01 + 1) before it is fed to the counter 0 & 1 | ||
| If CP01 =0, the prescaler 0 output clock will be stopped. So PWM counter 0 and 1 will be stopped also. | ||
| [15:8] | CP23 | Clock Prescaler 2 For PWM Timer 2 & 3 |
| Clock input is divided by (CP23 + 1) before it is fed to the counter 2 & 3 | ||
| If CP23=0, the prescaler 2 output clock will be stopped. So PWM counter2 and 3 will be stopped also. | ||
| [23:16] | DZ01 | Dead Zone Interval Register For CH0 And CH1 Pair |
| These 8 bits determine dead zone length. | ||
| The unit time of dead zone length is received from clock selector 0. | ||
| [31:24] | DZ23 | Dead Zone Interval Register For CH2 And CH3 Pair |
| These 8 bits determine dead zone length. | ||
| The unit time of dead zone length is received from clock selector 2. |
Definition at line 6607 of file Nano100Series.h.
| __IO uint32_t GPIO_T::PUEN |
Offset: 0x24 GPIO Port
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PUEN | GPIO Port [X] Pin [N] Pull-Up Enable Register |
| Read : | ||
| 1 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled. | ||
| 0 = GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled. | ||
| Note: For GPIOF_PUEN, bits [15:6] are reserved. |
Definition at line 3971 of file Nano100Series.h.
| __IO uint32_t ADC_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWUPRDY | ADC Power-Up Sequence Completed And Ready For Conversion |
| 0 = ADC is not ready for conversion; may be in power down state or in the progress of power up. | ||
| 1 = ADC is ready for conversion. | ||
| [1] | PWDCALEN | Power Up Calibration Function Enable |
| 1 = Power up with calibration. | ||
| 0 = Power up without calibration. | ||
| Note: This bit work together with CALFBKSEL set 1 | ||
| [3:2] | PWDMOD | Power-Down Mode |
| 00 = Power down | ||
| 01 = Reserved | ||
| 10 = Standby mode | ||
| 11 = Reserved | ||
| Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in powe down and power up |
Definition at line 475 of file Nano100Series.h.
| __IO uint32_t CLK_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXT_EN | HXT Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| The bit default value is set by flash controller user configuration register config0 [26]. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| HXT is disabled by default. | ||
| [1] | LXT_EN | LXT Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| LXT is disabled by default. | ||
| [2] | HIRC_EN | HIRC Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| HIRC is enabled by default. | ||
| [3] | LIRC_EN | LIRC Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| LIRC is enabled by default. | ||
| [4] | WK_DLY | Wake-Up Delay Counter Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable. | ||
| 0 = Delay clock cycle Disabled. | ||
| 1 = Delay clock cycle Enabled. | ||
| [5] | PD_WK_IE | Power-Down Mode Wake-Up Interrupt Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high. | ||
| [6] | PD_EN | Chip Power-Down Mode Enable Bit |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active | ||
| When chip wakes up from Power-down mode, this bit will be auto cleared. | ||
| When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode. | ||
| When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. | ||
| Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC. | ||
| In Power-down mode, flash macro power is ON. | ||
| 0 = Chip operated in Normal mode. | ||
| 1 = Chip power down Enabled. | ||
| [8] | HXT_SELXT | HXT SELXT |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = High frequency crystal loop back path Disabled. It is used for external oscillator. | ||
| 1 = High frequency crystal loop back path Enabled. It is used for external crystal. | ||
| [9] | HXT_GAIN | HXT Gain Control Bit |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Gain control is used to enlarge the gain of crystal to make sure crystal wok normally. | ||
| If gain control is enabled, crystal will consume more power than gain control off. | ||
| 0 = Gain control Disabled. It means HXT gain is always high. | ||
| For 16MHz to 24MHz crystal. | ||
| 1 = Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving. | ||
| For 4MHz to 16MHz crystal. | ||
| [10] | LXT_SCNT | LXT Stable Time Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Delay 4096 LXT before LXT output. | ||
| 1 = Delay 8192 LXT before LXT output. | ||
| [12:11] | HXT_HF_ST | HXT Frequency Selection |
| Set this bit to meet HXT frequency selection (Recommended) | ||
| 00 = HXT frequency is from 4 MHz to 12 MHz. | ||
| 01 = HXT frequency is from 12 MHz to 16 MHz. | ||
| 10 = HXT frequency is from 16 MHz to 24 MHz. | ||
| 11 = Reserved. |
Definition at line 789 of file Nano100Series.h.
| __I uint32_t SC_T::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receiving Buffer |
| By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 8289 of file Nano100Series.h.
| __I uint32_t { ... } ::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receiving Buffer |
| By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 8289 of file Nano100Series.h.
| __I uint32_t UART_T::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receiving Buffer |
| By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 10115 of file Nano100Series.h.
| __I uint32_t { ... } ::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receiving Buffer |
| By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 10115 of file Nano100Series.h.
| __IO uint32_t SYS_T::RegLockAddr |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RegUnLock | Register unlock bit |
| 0 = Protected register are Locked. Any write to the target register is ignored. | ||
| 1 = Protected registers are Unlocked. |
Definition at line 2941 of file Nano100Series.h.
| uint32_t USBD_EP_T::RESERVE |
Definition at line 10911 of file Nano100Series.h.
| uint32_t FMC_T::RESERVE0[10] |
Definition at line 1903 of file Nano100Series.h.
| uint32_t ADC_T::RESERVE0[1] |
Definition at line 438 of file Nano100Series.h.
| uint32_t DAC_T::RESERVE0[1] |
Definition at line 1541 of file Nano100Series.h.
| uint32_t DMA_CRC_T::RESERVE0[1] |
Definition at line 5632 of file Nano100Series.h.
| uint32_t PDMA_T::RESERVE0[1] |
Definition at line 6001 of file Nano100Series.h.
| uint32_t VDMA_T::RESERVE0[1] |
Definition at line 6186 of file Nano100Series.h.
| uint32_t PWM_T::RESERVE0[1] |
Definition at line 6778 of file Nano100Series.h.
| uint32_t I2C_T::RESERVE0[2] |
Definition at line 4386 of file Nano100Series.h.
| uint32_t RTC_T::RESERVE0[2] |
Definition at line 8021 of file Nano100Series.h.
| uint32_t SPI_T::RESERVE0[2] |
Definition at line 9446 of file Nano100Series.h.
| uint32_t UART_T::RESERVE0[2] |
Definition at line 10488 of file Nano100Series.h.
| uint32_t SYS_T::RESERVE0[4] |
Definition at line 2157 of file Nano100Series.h.
| uint32_t USBD_T::RESERVE0 |
Definition at line 11128 of file Nano100Series.h.
| uint32_t DAC_T::RESERVE1[1] |
Definition at line 1604 of file Nano100Series.h.
| uint32_t DMA_CRC_T::RESERVE1[1] |
Definition at line 5646 of file Nano100Series.h.
| uint32_t VDMA_T::RESERVE1[1] |
Definition at line 6262 of file Nano100Series.h.
| uint32_t PWM_T::RESERVE1[1] |
Definition at line 6829 of file Nano100Series.h.
| uint32_t SYS_T::RESERVE1[3] |
Definition at line 2172 of file Nano100Series.h.
| uint32_t SPI_T::RESERVE1[3] |
Definition at line 9480 of file Nano100Series.h.
| uint32_t I2C_T::RESERVE1[4] |
Definition at line 4420 of file Nano100Series.h.
| uint32_t SYS_T::RESERVE2[1] |
Definition at line 2701 of file Nano100Series.h.
| uint32_t DMA_CRC_T::RESERVE2[1] |
Definition at line 5660 of file Nano100Series.h.
| uint32_t PWM_T::RESERVE2[1] |
Definition at line 6880 of file Nano100Series.h.
| uint32_t PWM_T::RESERVE3[1] |
Definition at line 6931 of file Nano100Series.h.
| uint32_t DMA_CRC_T::RESERVE3[22] |
Definition at line 5714 of file Nano100Series.h.
| uint32_t SYS_T::RESERVE3[4] |
Definition at line 2839 of file Nano100Series.h.
| uint32_t SYS_T::RESERVE4[29] |
Definition at line 2927 of file Nano100Series.h.
| uint32_t PWM_T::RESERVE4[3] |
Definition at line 6980 of file Nano100Series.h.
| __I uint32_t ADC_T::RESULT[18] |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | RSLT | A/D Conversion Result |
| This field contains 12 bits conversion results. | ||
| [16] | VALID | Data Valid Flag |
| It is a mirror of VALID bit in ADC_RESULTx | ||
| [17] | OVERRUN | Over Run Flag |
| It is a mirror to OVERRUN bit in ADC_RESULTx |
Definition at line 182 of file Nano100Series.h.
| __IO uint32_t SC_T::RFTMR |
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | RFTM | SC Receiver Buffer Time-Out Register (ETU Based) |
| The time-out counter resets and starts counting whenever the RX buffer received a new data word. | ||
| Once the counter decrease to "1" and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high). | ||
| Note1: The counter is ETU based and the real count value is RFTM + 1 | ||
| Note2: Fill all "0" to this field to disable this function. |
Definition at line 8506 of file Nano100Series.h.
| __IO uint32_t RTC_T::RIER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | AIER | Alarm Interrupt Enable |
| 0 = RTC Alarm Interrupt is disabled. | ||
| 1 = RTC Alarm Interrupt is enabled. | ||
| [1] | TIER | Time Tick Interrupt And Wake-Up By Tick Enable |
| 0 = RTC Time Tick Interrupt is disabled. | ||
| 1 = RTC Time Tick Interrupt is enabled. | ||
| [2] | SNOOPIER | Snooper Pin Event Detection Interrupt Enable |
| 0 = Snooper Pin Event Detection Interrupt is disabled. | ||
| 1 = Snooper Pin Event Detection Interrupt is enabled. |
Definition at line 7966 of file Nano100Series.h.
| __IO uint32_t RTC_T::RIIR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | AIS | RTC Alarm Interrupt Status |
| RTC unit will set AIS to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. | ||
| When this bit is set and AIER is also high, RTC will generate an interrupt to CPU. | ||
| This bit is cleared by writing "1" to it through software. | ||
| 0 = RCT Alarm Interrupt condition never occurred. | ||
| 1 = RTC Alarm Interrupt is requested if RIER.AIER=1. | ||
| [1] | TIS | RTC Time Tick Interrupt Status |
| RTC unit will set TIF to high periodically in the period selected by TTR[2:0]. | ||
| When this bit is set and TIER is also high, RTC will generate an interrupt to CPU. | ||
| This bit is cleared by writing "1" to it through software. | ||
| 0 = RCT Time Tick Interrupt condition never occurred. | ||
| 1 = RTC Time Tick Interrupt is requested. | ||
| [2] | SNOOPIF | Snooper Pin Event Detection Interrupt Flag |
| When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set. | ||
| While this bit is set and SNOOPIER is also high, RTC will generate an interrupt to CPU. | ||
| Write "1" to clear this bit to "0". | ||
| 0 = Snooper pin event defined by SNOOPEDGE never detected. | ||
| 1 = Snooper pin event defined by SNOOPEDGE detected. |
Definition at line 7994 of file Nano100Series.h.
| __O uint32_t WWDT_T::RLD |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RLD | Window Watchdog Timer Reload Counter Register |
| Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. | ||
| Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP. | ||
| If SW writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal. |
Definition at line 11484 of file Nano100Series.h.
| __IO uint32_t SYS_T::RST_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RSTS_POR | The RSTS_POR Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRSTC1[0]) To Indicate The Previous Reset Source |
| 0 = No reset from POR or CHIP_RST. | ||
| 1 = Power-on Reset (POR) or CHIP_RST had issued the reset signal to reset the system. | ||
| This bit is cleared by writing 1 to itself. | ||
| [1] | RSTS_PAD | The RSTS_PAD Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source |
| 0 = No reset from /RESET pin. | ||
| 1 = The /RESET pin had issued the reset signal to reset the system. | ||
| This bit is cleared by writing 1 to itself. | ||
| [2] | RSTS_WDT | The RSTS_WDT Flag Is Set By The "Reset Signal" From The Watchdog Timer Module To Indicate The Previous Reset Source |
| 0 = No reset from Watchdog Timer. | ||
| 1 = The Watchdog Timer module had issued the reset signal to reset the system. | ||
| This bit is cleared by writing 1 to itself. | ||
| [4] | RSTS_BOD | The RSTS_BOD Flag Is Set By The "Reset Signal" From The Brown-Out-Detected Module To Indicate The Previous Reset Source |
| 0 = No reset from BOD. | ||
| 1 = Brown-out-Detected module had issued the reset signal to reset the system. | ||
| This bit is cleared by writing 1 to itself. | ||
| [5] | RSTS_SYS | The RSTS_SYS Flag Is Set By The "Reset Signal" From The Cortex_M0 Kernel To Indicate The Previous Reset Source |
| 0 = No reset from Cortex_M0. | ||
| 1 = Cortex_M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel. | ||
| This bit is cleared by writing 1 to itself. | ||
| [7] | RSTS_CPU | The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) "1" To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC) |
| 0 = No reset from CPU. | ||
| 1 = Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1. | ||
| This bit is cleared by writing 1 to itself. |
Definition at line 2042 of file Nano100Series.h.
| __I uint32_t SPI_T::RX0 |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RDATA | Receive Data FIFO Register |
| The received data can be read on it. | ||
| If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
| Note: These registers are read only. |
Definition at line 9431 of file Nano100Series.h.
| __I uint32_t SPI_T::RX1 |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RDATA | Receive Data FIFO Register |
| The received data can be read on it. | ||
| If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
| Note: These registers are read only. |
Definition at line 9445 of file Nano100Series.h.
| __I uint32_t I2S_T::RXFIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RXFIFO | Receiving FIFO Register |
| I2S contains 8 words (8x32-bit) data buffer for data receiving. | ||
| Read this register to get data in FIFO. | ||
| The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register. | ||
| This register is read only. |
Definition at line 4816 of file Nano100Series.h.
| __IO uint32_t I2C_T::SADDR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GCALL | General Call Function |
| The I2C controller supports the "General Call" function. | ||
| If the GCALL bit is set, the controller will respond to General Call address (00H). | ||
| When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode. | ||
| If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus. | ||
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | SADDR | I2C Salve Address Register |
| The content of this register is irrelevant when the device is in Master mode. | ||
| In the Slave mode, the seven most significant bits must be loaded with the device's own address. | ||
| The device will react if either of the address is matched. |
Definition at line 4364 of file Nano100Series.h.
| __IO uint32_t I2C_T::SADDR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GCALL | General Call Function |
| The I2C controller supports the "General Call" function. | ||
| If the GCALL bit is set, the controller will respond to General Call address (00H). | ||
| When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode. | ||
| If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus. | ||
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | SADDR | I2C Salve Address Register |
| The content of this register is irrelevant when the device is in Master mode. | ||
| In the Slave mode, the seven most significant bits must be loaded with the device's own address. | ||
| The device will react if either of the address is matched. |
Definition at line 4385 of file Nano100Series.h.
| __IO uint32_t I2C_T::SAMASK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | SAMASK | I2C Slave Address Mask Register |
| 0 = Mask disable (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask enable (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with two address mask registers. | ||
| When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register. |
Definition at line 4403 of file Nano100Series.h.
| __IO uint32_t I2C_T::SAMASK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | SAMASK | I2C Slave Address Mask Register |
| 0 = Mask disable (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask enable (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with two address mask registers. | ||
| When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register. |
Definition at line 4419 of file Nano100Series.h.
| __IO uint32_t PDMA_T::SAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDMA_SAR | PDMA Transfer Source Address Register |
| This field indicates a 32-bit source address of PDMA. | ||
| Note: The source address must be word alignment. |
Definition at line 5974 of file Nano100Series.h.
| __IO uint32_t VDMA_T::SAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | VDMA_SAR | VDMA Transfer Source Address Register |
| This field indicates a 32-bit source address of VDMA. |
Definition at line 6160 of file Nano100Series.h.
| __IO uint32_t VDMA_T::SASOCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | SASTOBL | VDMA Source Address Stride Offset Byte Length |
| The 16-bit register defines the source address stride transfer offset count of each row. | ||
| [31:16] | STBC | VDMA Stride Transfer Byte Count |
| The 16-bit register defines the stride transfer byte count of each row. |
Definition at line 6277 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::SEED |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CRC_SEED | CRC Seed Register |
| This field indicates the CRC seed value. |
Definition at line 5742 of file Nano100Series.h.
| __IO uint32_t ADC_T::SMPLCNT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | CH0SAMPCNT | Channel 0 Sampling Counter |
| 0000 = 0 ADC clock | ||
| 0001 = 1 ADC clock | ||
| 0010 = 2 ADC clocks | ||
| 0011 = 4 ADC clocks | ||
| 0100 = 8 ADC clocks | ||
| 0101 = 16 ADC clocks | ||
| 0110 = 32 ADC clocks | ||
| 0111 = 64 ADC clocks | ||
| 1000 = 128 ADC clocks | ||
| 1001 = 256 ADC clocks | ||
| 1010 = 512 ADC clocks | ||
| Others = 1024 ADC clocks | ||
| [7:4] | CH1SAMPCNT | Channel 1 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [11:8] | CH2SAMPCNT | Channel 2 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [15:12] | CH3SAMPCNT | Channel 3 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [19:16] | CH4SAMPCNT | Channel 4 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [23:20] | CH5SAMPCNT | Channel 5 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [27:24] | CH6SAMPCNT | Channel 6 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [31:28] | CH7SAMPCNT | Channel 7 Sampling Counter |
| The same as Channel 0 sampling counter table. |
Definition at line 550 of file Nano100Series.h.
| __IO uint32_t ADC_T::SMPLCNT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | CH8SAMPCNT | Channel 8 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [7:4] | CH9SAMPCNT | Channel 9 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [11:8] | CH10SAMPCNT | Channel 10 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [15:12] | CH11SAMPCNT | Channel 11 Sampling Counter |
| The same as Channel 0 sampling counter table. | ||
| [19:16] | INTCHSAMPCNT | Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, DAC0, DAC1) Sampling Counter |
| The same as Channel 0 sampling counter table. |
Definition at line 570 of file Nano100Series.h.
| __IO uint32_t RTC_T::SPR[20] |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | SPARE | SPARE |
| This field is used to store back-up information defined by software. | ||
| This field will be cleared by hardware automatically once a snooper pin event is detected. |
Definition at line 8062 of file Nano100Series.h.
| __IO uint32_t RTC_T::SPRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SNOOPEN | Snooper Pin Event Detection Enable |
| This bit enables the snooper pin event detection. | ||
| When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to "0" by hardware automatically. | ||
| And, the SNOOPIF will also be set. | ||
| In addition, RTC will also generate wake-up event to wake system up. | ||
| 0 = Snooper pin event detection function Disabled. | ||
| 1 = Snooper pin event detection function Enabled. | ||
| [1] | SNOOPEDGE | Snooper Active Edge Selection |
| This bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers. | ||
| 0 = Rising edge of snooper pin generates snooper pin detected event. | ||
| 1 = Falling edge of snooper pin generates snooper pin detected event. | ||
| [7] | SPRRDY | SPR Register Ready |
| This bit indicates if the registers SPR0 ~ SPR19 are ready to read. | ||
| After CPU writing registers SPR0 ~ SPR19, polling this bit to check if SP0 ~ SPR19 are updated done is necessary. | ||
| This it is read only and any write to this bit won't take any effect. | ||
| 0 = SPR0 ~ SPR19 updating is in progress. | ||
| 1 = SPR0 ~ SPR19 are updated done and ready to read. |
Definition at line 8049 of file Nano100Series.h.
| __IO uint32_t ADC_T::SR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADF | A/D Conversion End Flag |
| A status flag that indicates the end of A/D conversion. | ||
| ADF is set to 1 at these two conditions: | ||
| When A/D conversion ends in single mode | ||
| When A/D conversion ends on all specified channels in scan mode. | ||
| This flag can be cleared by writing 1 to it. | ||
| [1] | CMPF0 | Compare Flag |
| When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. | ||
| And it is cleared by writing 1 to self. | ||
| 0 = Conversion result in ADC_RESULTx does not meet ADCMPR0setting. | ||
| 1 = Conversion result in ADC_RESULTx meets ADCMPR0setting. | ||
| This flag can be cleared by writing 1 to it. | ||
| Note: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0 | ||
| [2] | CMPF1 | Compare Flag |
| When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. | ||
| And it is cleared by writing 1 to self. | ||
| 0 = Conversion result in ADC_RESULTx does not meet ADCMPR1 setting. | ||
| 1 = Conversion result in ADC_RESULTx meets ADCMPR1 setting. | ||
| This flag can be cleared by writing 1 to it. | ||
| Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1 | ||
| [3] | BUSY | BUSY/IDLE |
| 0 = A/D converter is in idle state. | ||
| 1 = A/D converter is busy at conversion. | ||
| This bit is a mirror of ADST bit in ADCR. That is to say if ADST = 1,then BUSY is 1 and vice versa. | ||
| It is read only. | ||
| [8:4] | CHANNEL | Current Conversion Channel |
| This filed reflects current conversion channel when BUSY=1. | ||
| When BUSY=0, it shows the next channel to be converted. | ||
| It is read only. | ||
| [16] | INITRDY | ADC Power-Up Sequence Completed |
| 0 = ADC not powered up after system reset. | ||
| 1 = ADC has been powered up since the last system reset. | ||
| Note: This bit will be set after system reset occurred and automatically cleared by power-up event. |
Definition at line 437 of file Nano100Series.h.
| __IO uint32_t SPI_T::SSR |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | SSR | Slave Select Active Register (Master Only) |
| If AUTOSS bit is cleared, writing "1" to SSR[0] bit sets the SPISS[0] line to an active state and writing "0" sets the line back to inactive state.(the same as SSR[1] for SPISS[1]) | ||
| If AUTOSS bit is set, writing "1" to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time. | ||
| (The active level of SPISS[1:0] is specified in SS_LVL). | ||
| Note: | ||
| 1. This interface can only drive one device/slave at a given time. | ||
| Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. | ||
| 2. SPISS[0] is also defined as device/slave select input in Slave mode. | ||
| And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. | ||
| [2] | SS_LVL | Slave Select Active Level |
| It defines the active level of device/slave select signal (SPISS[1:0]). | ||
| 0 = The SPI_SS slave select signal is active Low. | ||
| 1 = The SPI_SS slave select signal is active High. | ||
| [3] | AUTOSS | Automatic Slave Selection (Master Only) |
| 0 = If this bit is set as "0", slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register. | ||
| 1 = If this bit is set as "1", SPISS[1:0] signals are generated automatically. | ||
| It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done. | ||
| [4] | SS_LTRIG | Slave Select Level Trigger |
| 0 = The input slave select signal is edge-trigger. | ||
| 1 = The slave select signal will be level-trigger. | ||
| It depends on SS_LVL to decide the signal is active low or active high. | ||
| [5] | NOSLVSEL | No Slave Selected In Slave Mode |
| This is used to ignore the slave select signal in Slave mode. | ||
| The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. | ||
| 0 = The controller is 4-wire bi-direction interface. | ||
| 1 = The controller is 3-wire bi-direction interface in Slave mode. | ||
| When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input. | ||
| Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be set as "1". | ||
| [8] | SLV_ABORT | Abort In Slave Mode With No Slave Selected |
| In normal operation, there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN. | ||
| If the received bits are less than the requirement and there is no more serial clock input over the time period which is defined by user in slave mode with no slave select, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. | ||
| Note: It is auto cleared to "0" by hardware when the abort event is active. | ||
| [9] | SSTA_INTEN | Slave Start Interrupt Enable |
| It is used to enable interrupt when the transfer has started in Slave mode with no slave select. | ||
| If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done. | ||
| 0 = Tansfer start interrupt Disabled. | ||
| 1 = Transaction start interrupt Enabled. | ||
| It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear). | ||
| [16] | SS_INT_OPT | Slave Select Interrupt Option |
| It is used to enable the interrupt when the transfer has done in slave mode. | ||
| 0 = No any interrupt, even there is slave select inactive event. | ||
| 1 = There is interrupt event when the slave select is inactive. | ||
| It is used to inform the user the transaction has finished and the slave select into the inactive state. |
Definition at line 9417 of file Nano100Series.h.
| __I uint32_t I2C_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | STATUS | I2C Status Register |
| This is a read only register. | ||
| The three least significant bits are always 0. | ||
| The five most significant bits contain the status code. | ||
| When each of these states is entered, a status interrupt and I2C_STS are requested (I2C_STS = 1 and STAINTSTS = 1). | ||
| A valid status code is present in STATUS one machine cycle after I2C_STS is set by hardware and is still present one machine cycle after I2C_STS has been reset by software. | ||
| In addition, states 00H stands for a 'Bus Error'. | ||
| A 'Bus Error' occurs when a START or STOP condition is present at an illegal position in the formation frame. | ||
| Example of illegal position: a data byte or an acknowledge bit is present during the serial transfer of an address byte. | ||
| To recover I2C from bus error, STOP should be set and I2C_STS should be cleared to enter not addressed Slave mode. | ||
| Then clear STOP to release the bus and to wait new communication. | ||
| I2C bus can not recognize stop condition during this action when bus error occurs. |
Definition at line 4291 of file Nano100Series.h.
| __IO uint32_t I2S_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SINT | I2S Interrupt Flag |
| 0 = No I2S interrupt. | ||
| 1 = I2S interrupt occurred. | ||
| It is wire-OR of I2STXINT and I2SRXINT bits. | ||
| This bit is read only. | ||
| [1] | I2SRXINT | I2S Receiving Interrupt |
| 0 = No receiving interrupt occurred. | ||
| 1 = Receiving interrupt occurred. | ||
| This bit is read only | ||
| [2] | I2STXINT | I2S Transmit Interrupt |
| 0 = No transmit interrupt occurred. | ||
| 1 = Transmit interrupt occurred. | ||
| This bit is read only | ||
| [3] | RIGHT | Right Channel |
| This bit indicates the current transmitting data is belong to right channel | ||
| 0 = Left channel. | ||
| 1 = Right channel. | ||
| This bit is read only | ||
| [8] | RXUDF | Receiving FIFO Underflow Flag |
| Read the receiving FIFO when it is empty, this bit set to "1" indicate underflow occur. | ||
| 0 = No underflow occurred. | ||
| 1 = Underflow occurred. | ||
| This bit is cleared by writing 1. | ||
| [9] | RXOVF | Receiving FIFO Overflow Flag |
| When the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to "1". | ||
| Data in 1st buffer is overwritten. | ||
| 0 = No overflow occurred. | ||
| 1 = Overflow occurred. | ||
| This bit is cleared by writing 1. | ||
| [10] | RXTHF | Receiving FIFO Threshold Flag |
| When data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0], the RXTHF bit becomes to "1". | ||
| It keeps at "1" till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from the RXFIFO register. | ||
| 0 = Data word(s) in receiving FIFO is lower than threshold level. | ||
| 1 = Data word(s) in receiving FIFO is equal to or higher than threshold level. | ||
| This bit is read only | ||
| [11] | RXFULL | Receiving FIFO Full |
| This bit reflect data word number in the receiving FIFO is 8 | ||
| 0 = Not full. | ||
| 1 = Full. | ||
| This bit is read only | ||
| [12] | RXEMPTY | Receiving FIFO Empty |
| This bit reflect data word number in the receiving FIFO is zero | ||
| 0 = Empty. | ||
| 1 = Not empty. | ||
| This bit is read only. | ||
| [16] | TXUDF | Transmitting FIFO Underflow Flag |
| When the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to "1". | ||
| 0 = No underflow. | ||
| 1 = Underflow. | ||
| This bit is cleared by writing 1. | ||
| [17] | TXOVF | Transmit FIFO Overflow Flag |
| Write data to the transmitting FIFO when it is full and this bit will set to "1" | ||
| 0 = No overflow. | ||
| 1 = Overflow. | ||
| This bit is cleared by writing 1. | ||
| [18] | TXTHF | Transmitting FIFO Threshold Flag |
| When data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0],the TXTHF bit becomes to "1". | ||
| It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes data into the TXFIFO register. | ||
| 0 = Data word(s) in transmitting FIFO is higher than threshold level. | ||
| 1 = Data word(s) in transmitting FIFO is equal to or lower than threshold level. | ||
| This bit is read only | ||
| [19] | TXFULL | Transmitting FIFO Full |
| This bit reflect data word number in the transmitting FIFO is 8 | ||
| 0 = Full. | ||
| 1 = Not full. | ||
| This bit is read only | ||
| [20] | TXEMPTY | Transmitting FIFO Empty |
| This bit reflect data word number in the transmitting FIFO is zero | ||
| 0 = Empty. | ||
| 1 = Not empty. | ||
| This bit is read only. | ||
| [21] | TXBUSY | Transmitting Busy |
| This bit is cleared to 0 when all data in the transmitting FIFO and shift buffer is shifted out. | ||
| Set this bit to 1 when 1st data is loading to shift buffer. | ||
| 0 = Transmit shift buffer is empty. | ||
| 1 = Transmit shift buffer is busy. | ||
| This bit is read only. | ||
| [22] | RZCF | Right Channel Zero Cross Flag |
| It indicates the data sign of right channel next sample data is changed or all data bits are zero. | ||
| 0 = No zero cross. | ||
| 1 = Right channel zero cross is detected. | ||
| This bit is cleared by writing 1. | ||
| [23] | LZCF | Left Channel Zero Cross Flag |
| It indicates the next sample data sign bit of left channel is changed or all data bits are zero. | ||
| 0 = No zero cross. | ||
| 1 = Left channel zero cross is detected. | ||
| This bit is cleared by writing 1. | ||
| [27:24] | RX_LEVEL | Receive FIFO Level |
| These bits indicate the number of word(s) in the receiving FIFO | ||
| [31:28] | TX_LEVEL | Transmitting FIFO Level |
| These bits indicate the number of word(s) in the transmitting FIFO |
Definition at line 4786 of file Nano100Series.h.
| __IO uint32_t SPI_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_EMPTY | Received FIFO_EMPTY Status |
| 0 = Received data FIFO is not empty in the dual FIFO mode. | ||
| 1 = Received data FIFO is empty in the dual FIFO mode. | ||
| [1] | RX_FULL | Received FIFO_FULL Status |
| 0 = Received data FIFO is not full in dual FIFO mode. | ||
| 1 = Received data FIFO is full in the dual FIFO mode. | ||
| [2] | TX_EMPTY | Transmitted FIFO_EMPTY Status |
| 0 = Transmitted data FIFO is not empty in the dual FIFO mode. | ||
| 1 =Transmitted data FIFO is empty in the dual FIFO mode. | ||
| [3] | TX_FULL | Transmitted FIFO_FULL Status |
| 0 = Transmitted data FIFO is not full in the dual FIFO mode. | ||
| 1 = Transmitted data FIFO is full in the dual FIFO mode. | ||
| [4] | LTRIG_FLAG | Level Trigger Accomplish Flag |
| In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. | ||
| 0 = The transferred bit length of one transaction does not meet the specified requirement. | ||
| 1 = The transferred bit length meets the specified requirement which defined in TX_BIT_LEN. | ||
| Note: This bit is READ only. | ||
| As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. | ||
| In FIFO mode, this bit is unmeaning. | ||
| [6] | SLV_START_INTSTS | Slave Start Interrupt Status |
| It is used to dedicate that the transfer has started in Slave mode with no slave select. | ||
| 0 = Slave started transfer no active. | ||
| 1 = Transfer has started in Slave mode with no slave select. | ||
| It is auto clear by transfer done or writing one clear. | ||
| [7] | INTSTS | Interrupt Status |
| 0 = Transfer is not finished yet. | ||
| 1 = Transfer is done. The interrupt is requested when the INTEN bit is enabled. | ||
| Note: This bit is read only, but can be cleared by writing "1" to this bit. | ||
| [8] | RXINT_STS | RX FIFO Threshold Interrupt Status (Read Only) |
| 0 = RX valid data counts small or equal than RXTHRESHOLD. | ||
| 1 = RX valid data counts bigger than RXTHRESHOLD. | ||
| Note: If RXINT_EN = 1 and RX_INTSTS = 1, SPI will generate interrupt. | ||
| [9] | RX_OVER_RUN | RX FIFO Over Run Status |
| If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will dropped. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [10] | TXINT_STS | TX FIFO Threshold Interrupt Status (Read Only) |
| 0 = TX valid data counts bigger than TXTHRESHOLD. | ||
| 1 = TX valid data counts small or equal than TXTHRESHOLD. | ||
| [12] | TIME_OUT_STS | TIMEOUT Interrupt Flag |
| 0 = There is not timeout event on the received buffer. | ||
| 1 = RX FIFO is not empty and there is not be read over the 64 SPI_CLK period in master mode and over the 576 ECLK period in slave mode. | ||
| When the received FIFO is read by user, the timeout status will be cleared automatically. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [19:16] | RX_FIFO_CNT | Data counts in RX FIFO (Read Only) |
| [23:20] | TX_FIFO_CNT | Data counts in TX FIFO (Read Only) |
Definition at line 9346 of file Nano100Series.h.
| __IO uint32_t WWDT_T::STS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | IF | WWDT Compare Match Interrupt Flag |
| When WWCMP match the WWDT counter, then this bit is set to 1. | ||
| This bit will be cleared by software write 1 to this bit. | ||
| [1] | RF | WWDT Reset Flag |
| When WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. | ||
| Software can write 1 to clear this bit to 0. |
Definition at line 11538 of file Nano100Series.h.
| __IO uint32_t DAC_T::STS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DACIFG | DAC Interrupt Flag |
| 0 = No interrupt pending. | ||
| 1 = Interrupt pending. | ||
| Note: This bit is read only. | ||
| [1] | DACSTFG | DAC Start Flag |
| 0 = DAC is not start yet. | ||
| 1 = DAC has been started. | ||
| Note: this bit is read only. | ||
| [2] | BUSY | BUSY Bit |
| 0 = DAC is not busy. | ||
| 1 = DAC is busy. |
Definition at line 1540 of file Nano100Series.h.
| __IO uint32_t DAC_T::STS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DACIFG | DAC Interrupt Flag |
| 0 = No interrupt pending. | ||
| 1 = Interrupt pending. | ||
| Note: This bit is read only. | ||
| [1] | DACSTFG | DAC Start Flag |
| 0 = DAC is not start yet. | ||
| 1 = DAC has been started. | ||
| Note: this bit is read only. | ||
| [2] | BUSY | BUSY Bit |
| 0 = DAC is not busy. | ||
| 1 = DAC is busy. |
Definition at line 1603 of file Nano100Series.h.
| __IO uint32_t RTC_T::TAR |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | 1SEC | 1 Sec Time Digit of Alarm Setting (0~9) |
| [6:4] | 10SEC | 10 Sec Time Digit of Alarm Setting (0~5) |
| [11:8] | 1MIN | 1 Min Time Digit of Alarm Setting (0~9) |
| [14:12] | 10MIN | 10 Min Time Digit of Alarm Setting (0~5) |
| [19:16] | 1HR | 1 Hour Time Digit of Alarm Setting (0~9) |
| [21:20] | 10HR | 10 Hour Time Digit of Alarm Setting (0~2) |
Definition at line 7918 of file Nano100Series.h.
| __I uint32_t TIMER_T::TCAP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CAP | Timer Capture Data Register |
| When TCAP_EN is set, TCAP_MODE is 0, and the transition of external pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. | ||
| User can read this register for the counter value. |
Definition at line 9989 of file Nano100Series.h.
| __IO uint32_t PDMA_T::TCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PDMA_TCR | PDMA Timer Count Setting Register |
| Each PDMA channel contains an internal counter. | ||
| The internal counter loads the value of PDAM_TCR and starts counting down when setting PDMA_CSRx [TO_EN] register. | ||
| PDMA will request interrupt when this internal counter reaches zero and PDMA_IERx[TO_IE] is high. | ||
| This internal counter will reload and start counting when completing each peripheral request service. |
Definition at line 6109 of file Nano100Series.h.
| __I uint32_t SC_T::TDRA |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TDR0 | Timer0 Current Data Register (Read Only) |
| This field indicates the current count values of timer0. |
Definition at line 8869 of file Nano100Series.h.
| __I uint32_t SC_T::TDRB |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | TDR1 | Timer1 Current Data Register (Read Only) |
| This field indicates the current count values of timer1. | ||
| [15:8] | TDR2 | Timer2 Current Data Register (Read Only) |
| This field indicates the current count values of timer2. |
Definition at line 8883 of file Nano100Series.h.
| __IO uint32_t SYS_T::TEMPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VTEMP_EN | Temperature Sensor Enable |
| 0 = Temperature sensor function Disabled (default). | ||
| 1 = Temperature sensor function Enabled. |
Definition at line 2171 of file Nano100Series.h.
| __O uint32_t SC_T::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Buffer |
| By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 8300 of file Nano100Series.h.
| __O uint32_t { ... } ::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Buffer |
| By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 8300 of file Nano100Series.h.
| __O uint32_t UART_T::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Buffer |
| By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 10128 of file Nano100Series.h.
| __O uint32_t { ... } ::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Buffer |
| By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 10128 of file Nano100Series.h.
| __IO uint32_t UART_T::TLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | DATA_LEN | Data Length |
| 00 = 5 bits. | ||
| 01 = 6 bits. | ||
| 10 = 7 bits. | ||
| 11 = 8 bits. | ||
| [2] | NSB | Number Of STOP Bit Length |
| 1 = 1.5 "STOP bit" is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit" is generated when 6, 7 and 8 bits data length is selected. | ||
| 0 = 1 " STOP bit" is generated in the transmitted data. | ||
| [3] | PBE | Parity Bit Enable |
| 1 = Parity bit is generated or checked bet"een the "last data"word "it" and "stop bit" of the serial data. | ||
| 0 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
| [4] | EPE | Even Parity Enable |
| 1 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| 0 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| Note: This bit has effect only when PBE bit (parity bit enable) is set. | ||
| [5] | SPE | Stick Parity Enable |
| 1 = When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as "0". | ||
| When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as "1". | ||
| In RS-485 mode, PBE, EPE and SPE can control bit 9. | ||
| 0 = Stick parity Disabled. | ||
| [6] | BCB | Break Control Bit |
| When this bit is set to logic "1", the serial data output (TX) is forced to the Spacing State (logic "0"). | ||
| This bit acts only on TX pin and has no effect on the transmitter logic. | ||
| [9:8] | RFITL | RX-FIFO Interrupt (INT_RDA) Trigger Level |
| When the number of bytes in the receiving FIFO is equal to the RFITL then the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated) | ||
| 00 = INTR_RDA Trigger Level 1 byte. | ||
| 01 = INTR_RDA Trigger Level 4 byte. | ||
| 10 = INTR_RDA Trigger Level 8 byte. | ||
| 11 = INTR_RDA Trigger Level 14 byte. | ||
| Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to "0". | ||
| [13:12] | RTS_TRI_LEV | RTSn Trigger Level (For Auto-Flow Control Use) |
| 00 = Trigger level 1 byte. | ||
| 01 = Trigger level 4 bytes. | ||
| 10 = Trigger level 8 bytes. | ||
| 11 = Trigger level 14 bytes. | ||
| Note: This field is used for auto RTSn flow control. |
Definition at line 10233 of file Nano100Series.h.
| __IO uint32_t RTC_T::TLR |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | 1SEC | 1 Sec Time Digit (0~9) |
| [6:4] | 10SEC | 10 Sec Time Digit (0~5) |
| [11:8] | 1MIN | 1 Min Time Digit (0~9) |
| [14:12] | 10MIN | 10 Min Time Digit (0~5) |
| [19:16] | 1HR | 1 Hour Time Digit (0~9) |
| [21:20] | 10HR | 10 Hour Time Digit (0~2) |
Definition at line 7854 of file Nano100Series.h.
| __IO uint32_t UART_T::TMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | TOIC | Time-Out Comparator |
| The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX-FIFO receives a new data word. | ||
| Once the content of time-out counter (TOUT_CNT) is equal to time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if UART_IER [RTO_IEN]. | ||
| A new incoming data word or RX-FIFO empty clears INT_TOUT. | ||
| Note1: Fill all "0" to this field indicates to disable this function. | ||
| Note2: The real time-out value is TOIC + 1. | ||
| Note3: The counting clock is baud rate clock. | ||
| Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to filled this field great than 0xA. | ||
| [23:16] | DLY | TX Delay Time Value |
| This field is use to program the transfer delay time between the last stop bit leaving the TX-FIFO and the de-assertion of by setting UART_TMCTL [DLY] register. | ||
| Note1: Fill all "0" to this field indicates to disable this function. | ||
| Note2: The real delay value is DLY. | ||
| Note3: The counting clock is baud rate clock. |
Definition at line 10471 of file Nano100Series.h.
| __IO uint32_t SC_T::TMR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer 0 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 0 Operation Mode Selection |
| This field indicates the internal 24 bit timer operation selection. |
Definition at line 8799 of file Nano100Series.h.
| __IO uint32_t SC_T::TMR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 1 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 1 Operation Mode Selection |
| This field indicates the internal 8 bit timer operation selection. |
Definition at line 8813 of file Nano100Series.h.
| __IO uint32_t SC_T::TMR2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 2 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 2 Operation Mode Selection |
| This field indicates the internal 8 bit timer operation selection. |
Definition at line 8827 of file Nano100Series.h.
| __IO uint32_t I2C_T::TOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TOUTEN | Time-Out Counter Enable/Disable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When set this bit to enable, the 14 bits time-out counter will start counting when STAINTSTS is cleared. | ||
| Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after STAINTSTS is cleared. | ||
| [1] | DIV4 | Time-Out Counter Input Clock Divider By 4 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set enabled, the Time-Out period is prolonging 4 times. |
Definition at line 4323 of file Nano100Series.h.
| __IO uint32_t SC_T::TRSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_OVER_F | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX buffer overflow. | ||
| If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: The overwrite data will be ignored. | ||
| [1] | RX_EMPTY_F | Receiver Buffer Empty Status Flag(Read Only) |
| This bit indicates RX buffer empty or not. | ||
| When the last byte of RX buffer has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when SC receives any new data. | ||
| [2] | RX_FULL_F | Receiver Buffer Full Status Flag (Read Only) |
| This bit indicates RX buffer full or not. | ||
| This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. | ||
| [4] | RX_EPA_F | Receiver Parity Error Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "parity bit". | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [5] | RX_EFR_F | Receiver Frame Error Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"). | ||
| Note1: This bit is read only, but can be cleared by writing "1" to it. | ||
| Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [6] | RX_EBR_F | Receiver Break Error Status Flag (Read Only) |
| This bit is set to a logic "1" whenever the received data input (RX) held in the "spacing state" (logic "0") is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [8] | TX_OVER_F | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX buffer is full (TX_FULL_F = "1"), an additional write data to SC_THR will cause this bit to logic "1". | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: The additional write data will be ignored. | ||
| [9] | TX_EMPTY_F | Transmit Buffer Empty Status Flag (Read Only) |
| This bit indicates TX buffer empty or not. | ||
| When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into SC_THR (TX buffer not empty). | ||
| [10] | TX_FULL_F | Transmit Buffer Full Status Flag (Read Only) |
| This bit indicates TX buffer full or not. | ||
| This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. | ||
| [18:16] | RX_POINT_F | Receiver Buffer Pointer Status Flag (Read Only) |
| This field indicates the RX buffer pointer status flag. | ||
| When SC receives one byte from external device, RX_POINT_F increases one. | ||
| When one byte of RX buffer is read by CPU, RX_POINT_F decreases one. | ||
| [21] | RX_REERR | Receiver Retry Error (Read Only) |
| This bit is set by hardware when RX has any error and retries transfer. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2 This bit is a flag and can not generate any interrupt to CPU. | ||
| Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F). | ||
| [22] | RX_OVER_ERETRY | Receiver Over Retry Error (Read Only) |
| This bit is set by hardware when RX transfer error retry over retry number limit. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F). | ||
| [23] | RX_ATV | Receiver In Active Status Flag (Read Only) |
| This bit is set by hardware when RX transfer is in active. | ||
| This bit is cleared automatically when RX transfer is finished. | ||
| [26:24] | TX_POINT_F | Transmit Buffer Pointer Status Flag (Read Only) |
| This field indicates the TX buffer pointer status flag. | ||
| When CPU writes data into SC_THR, TX_POINT_F increases one. | ||
| When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one. | ||
| [29] | TX_REERR | Transmitter Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2 This bit is a flag and can not generate any interrupt to CPU. | ||
| [30] | TX_OVER_ERETRY | Transmitter Over Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits over retry number limitation. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [31] | TX_ATV | Transmit In Active Status Flag (Read Only) |
| This bit is set by hardware when TX transfer is in active or the last byte transmission has not completed. | ||
| This bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted. |
Definition at line 8709 of file Nano100Series.h.
| __IO uint32_t UART_T::TRSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RS485_ADDET_F | RS-485 Address Byte Detection Status Flag (Read Only) |
| This bit is set to logic "1" and set UART_ALT_CTL [RS-485_ADD_EN] whenever in RS-485 mode the receiver detected any address byte character (bit 9 ='1') bit". | ||
| This bit is reset whenever the CPU writes "1" to this bit. | ||
| Note1: This field is used for RS-485 mode. | ||
| Note2: This bit is read only, but can be cleared by writing "1" to it. | ||
| [1] | ABAUD_F | Auto-Baud Rate Interrupt (Read Only) |
| This bit is set to logic "1" when auto-baud rate detect function finished. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [2] | ABAUD_TOUT_F | Auto-Baud Rate Time-Out Interrupt (Read Only) |
| This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [3] | LIN_TX_F | LIN TX Interrupt Flag (Read Only) |
| This bit is set to logic "1" when LIN transmitted header field. | ||
| The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", it can be choose by setting UART_ALT_CTL[LIN_HEAD_SEL] register. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [4] | LIN_RX_F | LIN RX Interrupt Flag (Read Only) |
| This bit is set to logic "1" when received LIN header field. | ||
| The header may be "break field" or "break field + sync field" or "break field + sync field + PID field", and it can be choose by setting UART_ALT_CTL [LIN_HEAD_SEL] register. | ||
| If the field includes "break field", when the receiver received break field then the LIN_RX_F will be set. | ||
| The controller will receive next data and put it in FIFO. | ||
| If the field includes "break field + sync field", hardware will wait for the flag LIN_RX_F in UART_TRSR to check RX received break field and sync field. | ||
| If the break and sync field is received, hardware will set UART_TRSR [LIN_RX_F] flag, and if the break is received but the sync field does not equal 0x55, then hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag. | ||
| The break and sync data (equals 0x55 or not) will not be stored in FIFO. | ||
| If the field includes "break field + sync field + PID field", In this operation mode, hardware will control data automatically. | ||
| Hardware will ignore any data until received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value (break + sync + PID will not be stored in FIFO). | ||
| When received break + sync (0x55) + PID value match the UART_ALT_CTL [ADDR_MATCH] value, hardware will set UART_TRSR [LIN_RX_F] and the following all data will be accepted and stored in the RX-FIFO until detect next break field. | ||
| If the receiver received break + wrong sync (not equal 0x55) + PID value, hardware will set UART_TRSR [LIN_RX_F] and UART_TRSR [LIN_RX_SYNC_ERR_F] flag and the receiver will be disabled. | ||
| If the receiver received break + sync (0x55) + wrong PID value, hardware will set UART_TRSR [LIN_RX_F] flag and the receiver will be disabled. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [5] | BIT_ERR_F | Bit Error Detect Status Flag (Read Only) |
| At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set. | ||
| When occur bit error, hardware will generate an interrupt to CPU (INT_LIN). | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: This bit is only valid when enabling the bit error detection function (UART_ALT_CTL [BIT_ERR_EN] = "1"). | ||
| [8] | LIN_RX_SYNC_ERR_F | LIN RX SYNC Error Flag (Read Only) |
| This bit is set to logic "1" when LIN received incorrect SYNC field. | ||
| User can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register. | ||
| If the field includes "break field + sync field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored. | ||
| The controller will receive next data and put it in FIFO. | ||
| If the field includes "break field + sync field + PID field" and if the sync data does not equal 0x55, the LIN_RX_F and LIN_RX_SYNC_ERR_F will be set and the wrong sync data will be ignored. | ||
| The controller will receive next data and put it in FIFO. | ||
| Note: This bit is read only, but can be cleared by writing "1" to LIN_RX_F. |
Definition at line 10370 of file Nano100Series.h.
| __IO uint32_t RTC_T::TSSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | 24hr_12hr | 24-Hour / 12-Hour Mode Selection |
| It indicates that TLR and TAR are in 24-hour mode or 12-hour mode | ||
| 0 = select 12-hour time scale with AM and PM indication. | ||
| 1 = select 24-hour time scale. |
Definition at line 7884 of file Nano100Series.h.
| __IO uint32_t RTC_T::TTR |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | TTR | Time Tick Register |
| The RTC time tick period for Periodic Time Tick Interrupt request. | ||
| 000 = 1 tick/second. | ||
| 001 = 1/2 tick/second. | ||
| 010 = 1/4 tick/second. | ||
| 011 = 1/8 tick/second. | ||
| 100 = 1/16 tick/second. | ||
| 101 = 1/32 tick/second. | ||
| 110 = 1/64 tick/second. | ||
| 111 = 1/128 tick/second. | ||
| Note: This register can be read back after the RTC is active by AER. | ||
| [3] | TWKE | RTC Timer Wake-Up CPU Function Enable Bit |
| If TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit. | ||
| 0 = Time Tick wake-up CPU function Disabled. | ||
| 1 = Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick. | ||
| Note: Tick timer setting follows the TTR description. |
Definition at line 8020 of file Nano100Series.h.
| __O uint32_t SPI_T::TX0 |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TDATA | Transmit Data FIFO Register |
| The Data Transmit Registers hold the data to be transmitted in the next transfer. | ||
| The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
| For example, if TX_BIT_LEN is set to 0x08, the bit SPI_TX[7:0] will be transmitted in next transfer. | ||
| If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer. | ||
| Note: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1 |
Definition at line 9463 of file Nano100Series.h.
| __O uint32_t SPI_T::TX1 |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TDATA | Transmit Data FIFO Register |
| The Data Transmit Registers hold the data to be transmitted in the next transfer. | ||
| The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
| For example, if TX_BIT_LEN is set to 0x08, the bit SPI_TX[7:0] will be transmitted in next transfer. | ||
| If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer. | ||
| Note: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1 |
Definition at line 9479 of file Nano100Series.h.
| __O uint32_t I2S_T::TXFIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TXFIFO | Transmitting FIFO Register |
| I2S contains 8 words (8x32-bit) data buffer for data transmitting. | ||
| Write data to this register in order to prepare data for transmitting. | ||
| The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS register. | ||
| This register is write only. |
Definition at line 4801 of file Nano100Series.h.
| __IO uint32_t SC_T::UACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UA_MODE_EN | UART Mode Enable |
| 0 = Smart Card mode. | ||
| 1 = UART mode. | ||
| Note1: When operating in UART mode, user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to "0". | ||
| Note2: When operating in smart card mode, user must set SCx_UACTL [7:0] register to "0". | ||
| Note3: When UART is enabled, hardware will generate a reset to reset internal buffer and internal state machine. | ||
| [5:4] | DATA_LEN | Data Length |
| 00 = 8 bits | ||
| 01 = 7 bits | ||
| 10 = 6 bits | ||
| 11 = 5 bits | ||
| Note: In Smart Card mode, this field must be '00' | ||
| [6] | PBDIS | Parity Bit Disable |
| 0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. | ||
| 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
| Note: In Smart Card mode, this field must be '0' (default setting is with parity bit) | ||
| [7] | OPE | Odd Parity Enable |
| 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| Note: This bit has effect only when PBDIS bit is '0'. |
Definition at line 8857 of file Nano100Series.h.
| __I uint32_t WWDT_T::VAL |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | VAL | WWDT Counter Value |
| This register reflects the counter value of window watchdog. This register is read only |
Definition at line 11550 of file Nano100Series.h.
| __IO uint32_t SPI_T::VARCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | VARCLK | Variable Clock Pattern Flag |
| The value in this field is the frequency patterns of the SPICLK. | ||
| If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER1. | ||
| If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. | ||
| Note: It is used for CLKP = 0 only. |
Definition at line 9496 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::WDATA |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CRC_WDATA | CRC Write Data Register |
| When operating in CPU PIO (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0) mode, software can write data to this field to perform CRC operation;. | ||
| When operating in CRC DMA mode (CRC_CTL [CRCCEN] = 1, CRC_CTL [TRIG_EN] = 0), this field will be used for DMA internal buffer. | ||
| Note1: When operating in CRC DMA mode, so don't filled any data in this field. | ||
| Note2:The CRC_CTL [WDATA_COM] and CRC_CTL [WDATA_RVS] bit setting will affected this field; For example, if WDATA_RVS = 1, if the write data in CRC_WDATA register is 0xAABBCCDD, the read data from CRC_WDATA register will be 0x55DD33BB |
Definition at line 5730 of file Nano100Series.h.
| __IO uint32_t CLK_T::WK_INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PD_WK_IS | Wake-Up Interrupt Status In Chip Power-Down Mode |
| This bit indicates that some event resumes chip from Power-down mode | ||
| The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred. | ||
| Write 1 to clear this bit. |
Definition at line 1203 of file Nano100Series.h.
| __IO uint32_t I2C_T::WKUPCON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKUPEN | I2C Wake-Up Function Enable |
| 0 = I2C wake-up function Disabled. | ||
| 1 = I2C wake-up function Enabled. |
Definition at line 4434 of file Nano100Series.h.
| __IO uint32_t I2C_T::WKUPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKUPIF | Wake-Up Interrupt Flag |
| 0 = Wake-up flag inactive. | ||
| 1 = Wake-up flag active. | ||
| Software can write 1 to clear this flag |
Definition at line 4448 of file Nano100Series.h.