| 0 = EBI write buffer Disabled. | ||
| 1 = EBI write buffer Enabled. | ||
| Note: This bit only available in EBI_CTL0 register |
| PWM_T::CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CNTTYPEn | PWM Counter Behavior Type |
| Each bit n controls corresponding PWM channel n. | ||
| 00 = Up counter type (supports in capture mode). | ||
| 01 = Down count type (supports in capture mode). | ||
| 10 = Up-down counter type. | ||
| 11 = Reserved. | ||
| [21:16] | CNTMODEn | PWM Counter Mode |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Auto-reload mode. | ||
| 1 = One-shot mode. | ||
| [26:24] | OUTMODEn | PWM Output Mode |
| Each bit n controls the | ||
| output mode of | ||
| corresponding PWM channel n. | ||
| 0 = PWM independent mode. | ||
| 1 = PWM complementary mode. | ||
| Note: When operating in group function, these bits must all set to the same mode. |
| EADC_T::CURDAT |
| PDMA_T::CURSCAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CURADDR | PDMA Current Description Address Register (Read Only) |
| This field indicates a 32-bit current external description address of PDMA controller. | ||
| Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. |
| DSCT_T::DA |
| EADC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | RESULT | A/D Conversion Result |
| This field contains 12 bits conversion result. | ||
| When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. | ||
| When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. | ||
| [16] | OV | Overrun Flag |
| If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. | ||
| 0 = Data in RESULT[11:0] is recent conversion result. | ||
| 1 = Data in RESULT[11:0] is overwrite. | ||
| Note: It is cleared by hardware after EADC_DAT register is read. | ||
| [17] | VALID | Valid Flag |
| This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. | ||
| 0 = Data in RESULT[11:0] bits is not valid. | ||
| 1 = Data in RESULT[11:0] bits is valid. |
| CRC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DATA | CRC Write Data Bits |
| User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. | ||
| Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. |
| I2C_T::DAT |
| SC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | Receiving/ Transmit Holding Buffer |
| Write Operation: | ||
| By writing data to DAT, the SC will send out an 8-bit data. | ||
| Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed. | ||
| Read Operation: | ||
| By reading DAT, the SC will return an 8-bit received data. |
| UART_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | Receiving/Transmit Buffer |
| Write Operation: | ||
| By writing one byte to this register, the data byte will be stored in transmitter FIFO. | ||
| The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. | ||
| Read Operation: | ||
| By reading this register, the UART will return an 8-bit data received from receiving FIFO. |
| GPIO_T::DATMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | DMASKn | Port A-F Pin[n] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| GPIO_DBCTL_T::DBCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DBCLKSEL | De-Bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clocks. | ||
| 0001 = Sample interrupt input once per 2 clocks. | ||
| 0010 = Sample interrupt input once per 4 clocks. | ||
| 0011 = Sample interrupt input once per 8 clocks. | ||
| 0100 = Sample interrupt input once per 16 clocks. | ||
| 0101 = Sample interrupt input once per 32 clocks. | ||
| 0110 = Sample interrupt input once per 64 clocks. | ||
| 0111 = Sample interrupt input once per 128 clocks. | ||
| 1000 = Sample interrupt input once per 256 clocks. | ||
| 1001 = Sample interrupt input once per 2*256 clocks. | ||
| 1010 = Sample interrupt input once per 4*256 clocks. | ||
| 1011 = Sample interrupt input once per 8*256 clocks. | ||
| 1100 = Sample interrupt input once per 16*256 clocks. | ||
| 1101 = Sample interrupt input once per 32*256 clocks. | ||
| 1110 = Sample interrupt input once per 64*256 clocks. | ||
| 1111 = Sample interrupt input once per 128*256 clocks. | ||
| [4] | DBCLKSRC | De-Bounce Counter Clock Source Selection |
| 0 = De-bounce counter clock source is the HCLK. | ||
| 1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator. | ||
| [5] | ICLKON | Interrupt Clock On Mode |
| 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. | ||
| 1 = All I/O pins edge detection circuit is always active after reset. | ||
| Note: It is recommended to disable this bit to save system power if no special application concern. |
| GPIO_T::DBEN |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | DBENn | Port A-F Pin[n] Input Signal De-Bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| EADC_T::DDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | RESULT | A/D Conversion Results |
| This field contains 12 bits conversion results. | ||
| When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. | ||
| When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. | ||
| [16] | OV | Overrun Flag |
| 0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. | ||
| 1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. | ||
| If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after EADC_DDAT register is read. | ||
| [17] | VALID | Valid Flag |
| 0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. | ||
| 1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. | ||
| This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read. | ||
| (n=0~3). |
| FMC_T::DFBA |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DFBA | Data Flash Base Address |
| This register indicates Data Flash start address. It is a read only register. | ||
| The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 | ||
| This register is valid when DFEN (CONFIG0[0]) =0 . |
| GPIO_T::DINOFF |
| Bits | Field | Descriptions |
|---|---|---|
| [n+16] | DINOFFn | Port A-F Pin[n] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| GPIO_T::DOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | DOUTn | Port A-F Pin[n] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| GPIO_T::DRVCTL |
| PDMA_T::DSCT |
| PWM_T::DTCTL0_1 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-Time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-Time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM_CLK. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::DTCTL2_3 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-Time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-Time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM_CLK. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::DTCTL4_5 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-Time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-Time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM_CLK. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::EADCTS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | TRGSEL0 | PWM_CH0 Trigger EADC Source Select |
| 0000 = PWM_CH0 zero point. | ||
| 0001 = PWM_CH0 period point. | ||
| 0010 = PWM_CH0 zero or period point. | ||
| 0011 = PWM_CH0 up-count CMPDAT point. | ||
| 0100 = PWM_CH0 down-count CMPDAT point. | ||
| 0101 = PWM_CH1 zero point. | ||
| 0110 = PWM_CH1 period point. | ||
| 0111 = PWM_CH1 zero or period point. | ||
| 1000 = PWM_CH1 up-count CMPDAT point. | ||
| 1001 = PWM_CH1 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [7] | TRGEN0 | PWM_CH0 Trigger EADC enable bit |
| [11:8] | TRGSEL1 | PWM_CH1 Trigger EADC Source Select |
| 0000 = PWM_CH0 zero point. | ||
| 0001 = PWM_CH0 period point. | ||
| 0010 = PWM_CH0 zero or period point. | ||
| 0011 = PWM_CH0 up-count CMPDAT point. | ||
| 0100 = PWM_CH0 down-count CMPDAT point. | ||
| 0101 = PWM_CH1 zero point. | ||
| 0110 = PWM_CH1 period point. | ||
| 0111 = PWM_CH1 zero or period point. | ||
| 1000 = PWM_CH1 up-count CMPDAT point. | ||
| 1001 = PWM_CH1 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [15] | TRGEN1 | PWM_CH1 Trigger EADC enable bit |
| [19:16] | TRGSEL2 | PWM_CH2 Trigger EADC Source Select |
| 0000 = PWM_CH2 zero point. | ||
| 0001 = PWM_CH2 period point. | ||
| 0010 = PWM_CH2 zero or period point. | ||
| 0011 = PWM_CH2 up-count CMPDAT point. | ||
| 0100 = PWM_CH2 down-count CMPDAT point. | ||
| 0101 = PWM_CH3 zero point. | ||
| 0110 = PWM_CH3 period point. | ||
| 0111 = PWM_CH3 zero or period point. | ||
| 1000 = PWM_CH3 up-count CMPDAT point. | ||
| 1001 = PWM_CH3 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [23] | TRGEN2 | PWM_CH2 Trigger EADC enable bit |
| [27:24] | TRGSEL3 | PWM_CH3 Trigger EADC Source Select |
| 0000 = PWM_CH2 zero point. | ||
| 0001 = PWM_CH2 period point. | ||
| 0010 = PWM_CH2 zero or period point. | ||
| 0011 = PWM_CH2 up-count CMPDAT point. | ||
| 0100 = PWM_CH2 down-count CMPDAT point. | ||
| 0101 = PWM_CH3 zero point. | ||
| 0110 = PWM_CH3 period point. | ||
| 0111 = PWM_CH3 zero or period point. | ||
| 1000 = PWM_CH3 up-count CMPDAT point. | ||
| 1001 = PWM_CH3 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [31] | TRGEN3 | PWM_CH3 Trigger EADC enable bit |
| PWM_T::EADCTS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | TRGSEL4 | PWM_CH4 Trigger EADC Source Select |
| 0000 = PWM_CH4 zero point. | ||
| 0001 = PWM_CH4 period point. | ||
| 0010 = PWM_CH4 zero or period point. | ||
| 0011 = PWM_CH4 up-count CMPDAT point. | ||
| 0100 = PWM_CH4 down-count CMPDAT point. | ||
| 0101 = PWM_CH5 zero point. | ||
| 0110 = PWM_CH5 period point. | ||
| 0111 = PWM_CH5 zero or period point. | ||
| 1000 = PWM_CH5 up-count CMPDAT point. | ||
| 1001 = PWM_CH5 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [7] | TRGEN4 | PWM_CH4 Trigger EADC enable bit |
| [11:8] | TRGSEL5 | PWM_CH5 Trigger EADC Source Select |
| 0000 = PWM_CH4 zero point. | ||
| 0001 = PWM_CH4 period point. | ||
| 0010 = PWM_CH4 zero or period point. | ||
| 0011 = PWM_CH4 up-count CMPDAT point. | ||
| 0100 = PWM_CH4 down-count CMPDAT point. | ||
| 0101 = PWM_CH5 zero point. | ||
| 0110 = PWM_CH5 period point. | ||
| 0111 = PWM_CH5 zero or period point. | ||
| 1000 = PWM_CH5 up-count CMPDAT point. | ||
| 1001 = PWM_CH5 down-count CMPDAT point. | ||
| 1010 = PWM_CH0 up-count free CMPDAT point. | ||
| 1011 = PWM_CH0 down-count free CMPDAT point. | ||
| 1100 = PWM_CH2 up-count free CMPDAT point. | ||
| 1101 = PWM_CH2 down-count free CMPDAT point. | ||
| 1110 = PWM_CH4 up-count free CMPDAT point. | ||
| 1111 = PWM_CH4 down-count free CMPDAT point. | ||
| [15] | TRGEN5 | PWM_CH5 Trigger EADC enable bit |
| SC_T::EGT |
| TIMER_T::EINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPIF | Timer External Capture Interrupt Flag |
| This bit indicates the timer external capture interrupt flag status. | ||
| 0 = Tx_EXT (x= 0~3) pin interrupt did not occur. | ||
| 1 = Tx_EXT (x= 0~3) pin interrupt occurred. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. | ||
| Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. | ||
| If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. |
| USBD_T::EPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [7] | OV | Overrun |
| It indicates that the received data is over the maximum payload number or not. | ||
| 0 = No overrun. | ||
| 1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. | ||
| [10:8] | EPSTS0 | Endpoint 0 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [13:11] | EPSTS1 | Endpoint 1 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [16:14] | EPSTS2 | Endpoint 2 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [19:17] | EPSTS3 | Endpoint 3 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [22:20] | EPSTS4 | Endpoint 4 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [25:23] | EPSTS5 | Endpoint 5 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [28:26] | EPSTS6 | Endpoint 6 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. | ||
| [31:29] | EPSTS7 | Endpoint 7 Bus Status |
| These bits are used to indicate the current status of this endpoint | ||
| 000 = In ACK. | ||
| 001 = In NAK. | ||
| 010 = Out Packet Data0 ACK. | ||
| 110 = Out Packet Data1 ACK. | ||
| 011 = Setup ACK. | ||
| 111 = Isochronous transfer end. |
| SC_T::ETUCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ETURDIV | ETU Rate Divider |
| The field indicates the clock rate divider. | ||
| The real ETU is ETURDIV + 1. | ||
| Note: | ||
| Software can configure this field, but this field must be greater than 0x004. | ||
| [15] | CMPEN | Compensation Mode Enable Bit |
| This bit enables clock compensation function. | ||
| When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV . | ||
| 0 = Compensation function Disabled. | ||
| 1 = Compensation function Enabled. |
| TIMER_T::EXTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTPHASE | Timer External Count Phase |
| This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3). | ||
| 0 = A Falling edge of external counting pin will be counted. | ||
| 1 = A Rising edge of external counting pin will be counted. | ||
| [2:1] | CAPEDGE | Timer External Capture Pin Edge Detect |
| 00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 11 = Reserved. | ||
| [3] | CAPEN | Timer External Capture Pin Enable |
| This bit enables the Tx_EXT pin. | ||
| 0 =Tx_EXT (x= 0~3) pin Disabled. | ||
| 1 =Tx_EXT (x= 0~3) pin Enabled. | ||
| [4] | CAPFUNCS | Capture Function Selection |
| 0 = External Capture Mode Enabled. | ||
| 1 = External Reset Mode Enabled. | ||
| Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value. | ||
| Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value. | ||
| [5] | CAPIEN | Timer External Capture Interrupt Enable |
| 0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled. | ||
| 1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled. | ||
| Note: CAPIEN is used to enable timer external interrupt. | ||
| If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. | ||
| For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. | ||
| [6] | CAPDBEN | Timer External Capture Pin De-Bounce Enable |
| 0 = Tx_EXT (x= 0~3) pin de-bounce Disabled. | ||
| 1 = Tx_EXT (x= 0~3) pin de-bounce Enabled. | ||
| Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. | ||
| [7] | CNTDBEN | Timer Counter Pin De-Bounce Enable |
| 0 = Tx_CNT (x= 0~3) pin de-bounce Disabled. | ||
| 1 = Tx_CNT (x= 0~3) pin de-bounce Enabled. | ||
| Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit. |
| USBD_T::FADDR |
| PWM_T::FAILBRK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CSSBRKEN | Clock Security System Detection Trigger PWM Brake Function 0 Enable |
| 0 = Brake Function triggered by CSS detection Disabled. | ||
| 1 = Brake Function triggered by CSS detection Enabled. | ||
| [1] | BODBRKEN | Brown-Out Detection Trigger PWM Brake Function 0 Enable |
| 0 = Brake Function triggered by BOD Disabled. | ||
| 1 = Brake Function triggered by BOD Enabled. | ||
| [3] | CORBRKEN | Core Lockup Detection Trigger PWM Brake Function 0 Enable |
| 0 = Brake Function triggered by Core lockup detection Disabled. | ||
| 1 = Brake Function triggered by Core lockup detection Enabled. |
| PWM_T::FCAPDAT0 |
| PWM_T::FCAPDAT1 |
| PWM_T::FCAPDAT2 |
| PWM_T::FCAPDAT3 |
| PWM_T::FCAPDAT4 |
| PWM_T::FCAPDAT5 |
| UART_T::FIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RXRST | RX Field Software Reset |
| When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will automatically clear at least 3 UART peripheral clock cycles. | ||
| [2] | TXRST | TX Field Software Reset |
| When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will automatically clear at least 3 UART peripheral clock cycles. | ||
| [7:4] | RFITL | RX FIFO Interrupt Trigger Level |
| When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). | ||
| 0000 = RX FIFO Interrupt Trigger Level is 1 byte. | ||
| 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. | ||
| 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. | ||
| 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. | ||
| Others = Reserved. | ||
| [8] | RXOFF | Receiver Disable |
| The receiver is disabled or not (set 1 to disable receiver) | ||
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| Note: This bit is used for RS-485 Normal Multi-drop mode. | ||
| It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. | ||
| [19:16] | RTSTRGLV | nRTS Trigger Level For Auto-Flow Control Use |
| 0000 = nRTS Trigger Level is 1 bytes. | ||
| 0001 = nRTS Trigger Level is 4bytes. | ||
| 0010 = nRTS Trigger Level is 8 bytes. | ||
| 0011 = nRTS Trigger Level is 14 bytes. | ||
| Others = Reserved. | ||
| Note: This field is used for auto nRTS flow control. |
| SPI_T::FIFOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXRST | Receive Reset |
| 0 = No effect. | ||
| 1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1. | ||
| User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not. | ||
| Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. | ||
| [1] | TXRST | Transmit Reset |
| 0 = No effect. | ||
| 1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1. | ||
| User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not. | ||
| Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. | ||
| [2] | RXTHIEN | Receive FIFO Threshold Interrupt Enable Bit |
| 0 = RX FIFO threshold interrupt Disabled. | ||
| 1 = RX FIFO threshold interrupt Enabled. | ||
| [3] | TXTHIEN | Transmit FIFO Threshold Interrupt Enable Bit |
| 0 = TX FIFO threshold interrupt Disabled. | ||
| 1 = TX FIFO threshold interrupt Enabled. | ||
| [4] | RXTOIEN | Slave Receive Time-Out Interrupt Enable Bit |
| 0 = Receive time-out interrupt Disabled. | ||
| 1 = Receive time-out interrupt Enabled. | ||
| [5] | RXOVIEN | Receive FIFO Overrun Interrupt Enable Bit |
| 0 = Receive FIFO overrun interrupt Disabled. | ||
| 1 = Receive FIFO overrun interrupt Enabled. | ||
| [6] | TXUFPOL | TX Underflow Data Polarity |
| 0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. | ||
| 1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. | ||
| Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active. | ||
| [7] | TXUFIEN | TX Underflow Interrupt Enable Bit |
| In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1. | ||
| 0 = Slave TX underflow interrupt Disabled. | ||
| 1 = Slave TX underflow interrupt Enabled. | ||
| [8] | RXFBCLR | Receive FIFO Buffer Clear |
| 0 = No effect. | ||
| 1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. | ||
| Note: The RX shift register will not be cleared. | ||
| [9] | TXFBCLR | Transmit FIFO Buffer Clear |
| 0 = No effect. | ||
| 1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. | ||
| Note: The TX shift register will not be cleared. | ||
| [26:24] | RXTH | Receive FIFO Threshold |
| If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. | ||
| In SPI0, RXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[25:24]). | ||
| [30:28] | TXTH | Transmit FIFO Threshold |
| If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. | ||
| In SPI0, TXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[29:28]). |
| UART_T::FIFOSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOVIF | RX Overflow Error Interrupt Flag (Read Only) |
| This bit is set when RX FIFO overflow. | ||
| If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set. | ||
| 0 = RX FIFO is not overflow. | ||
| 1 = RX FIFO is overflow. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [1] | ABRDIF | Auto-Baud Rate Detect Interrupt (Read Only) |
| 0 = Auto-baud rate detect function is not finished. | ||
| 1 = Auto-baud rate detect function is finished. | ||
| This bit is set to logic "1" when auto-baud rate detect function is finished. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [2] | ABRDTOIF | Auto-Baud Rate Time-Out Interrupt (Read Only) |
| 0 = Auto-baud rate counter is underflow. | ||
| 1 = Auto-baud rate counter is overflow. | ||
| Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow. | ||
| Note2: This bit is read only, but can be cleared by writing "1" to it. | ||
| [3] | ADDRDETF | RS-485 Address Byte Detect Flag (Read Only) |
| 0 = Receiver detects a data that is not an address bit (bit 9 ='0'). | ||
| 1 = Receiver detects a data that is an address bit (bit 9 ='1'). | ||
| Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode . | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [4] | PEF | Parity Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "parity bit". | ||
| 0 = No parity error is generated. | ||
| 1 = Parity error is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [5] | FEF | Framing Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). | ||
| 0 = No framing error is generated. | ||
| 1 = Framing error is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [6] | BIF | Break Interrupt Flag (Read Only) |
| This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). | ||
| 0 = No Break interrupt is generated. | ||
| 1 = Break interrupt is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [13:8] | RXPTR | RX FIFO Pointer (Read Only) |
| This field indicates the RX FIFO Buffer Pointer. | ||
| When UART receives one byte from external device, RXPTR increases one. | ||
| When one byte of RX FIFO is read by CPU, RXPTR decreases one. | ||
| The Maximum value shown in RXPTR is 15. | ||
| When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. | ||
| As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. | ||
| [14] | RXEMPTY | Receiver FIFO Empty (Read Only) |
| This bit initiate RX FIFO empty or not. | ||
| 0 = RX FIFO is not empty. | ||
| 1 = RX FIFO is empty. | ||
| Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when UART receives any new data. | ||
| [15] | RXFULL | Receiver FIFO Full (Read Only) |
| This bit initiates RX FIFO full or not. | ||
| 0 = RX FIFO is not full. | ||
| 1 = RX FIFO is full. | ||
| Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [21:16] | TXPTR | TX FIFO Pointer (Read Only) |
| This field indicates the TX FIFO Buffer Pointer. | ||
| When CPU writes one byte into UART_DAT, TXPTR increases one. | ||
| When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. | ||
| The Maximum value shown in TXPTR is 15. | ||
| When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. | ||
| As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. | ||
| [22] | TXEMPTY | Transmitter FIFO Empty (Read Only) |
| This bit indicates TX FIFO empty or not. | ||
| 0 = TX FIFO is not empty. | ||
| 1 = TX FIFO is empty. | ||
| Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into DAT (TX FIFO not empty). | ||
| [23] | TXFULL | Transmitter FIFO Full (Read Only) |
| This bit indicates TX FIFO full or not. | ||
| 0 = TX FIFO is not full. | ||
| 1 = TX FIFO is full. | ||
| Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [24] | TXOVIF | TX Overflow Error Interrupt Flag (Read Only) |
| If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. | ||
| 0 = TX FIFO is not overflow. | ||
| 1 = TX FIFO is overflow. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [28] | TXEMPTYF | Transmitter Empty Flag (Read Only) |
| This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. | ||
| 0 = TX FIFO is not empty. | ||
| 1 = TX FIFO is empty. | ||
| Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. |
| RTC_T::FREQADJ |
| PWM_T::FTCBUF0_1 |
| PWM_T::FTCBUF2_3 |
| PWM_T::FTCBUF4_5 |
| PWM_T::FTCI |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | FTCMUn | PWM FTCMPDAT Up Indicator |
| Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit. | ||
| Each bit n controls the corresponding PWM channel n. | ||
| [10:8] | FTCMDn | PWM FTCMPDAT Down Indicator |
| Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit. | ||
| Each bit n controls the corresponding PWM channel n. |
| PWM_T::FTCMPDAT0_1 |
| PWM_T::FTCMPDAT2_3 |
| PWM_T::FTCMPDAT4_5 |
| FMC_T::FTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [6:4] | FOM | Frequency Optimization Mode (Write Protect) |
| The NuMicro M4521 support adjustable flash access timing to optimize the flash access cycles in different working frequency. | ||
| 001 = Frequency <= 12MHz. | ||
| 010 = Frequency <= 36MHz. | ||
| 100 = Frequency <= 60MHz. | ||
| Others = Frequency <= 72MHz. |
| UART_T::FUNCSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | FUNCSEL | Function Select |
| 00 = UART function. | ||
| 01 = LIN function (Only Available in UART0/UART1 Channel). | ||
| 10 = IrDA function. | ||
| 11 = RS-485 function. | ||
| Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time. |
| SYS_T::GPA_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PA8MFP | PA.8 Multi-function Pin Selection |
| [7:4] | PA9MFP | PA.9 Multi-function Pin Selection |
| [11:8] | PA10MFP | PA.10 Multi-function Pin Selection |
| [15:12] | PA11MFP | PA.11 Multi-function Pin Selection |
| [19:16] | PA12MFP | PA.12 Multi-function Pin Selection |
| [23:20] | PA13MFP | PA.13 Multi-function Pin Selection |
| [27:24] | PA14MFP | PA.14 Multi-function Pin Selection |
| [31:28] | PA15MFP | PA.15 Multi-function Pin Selection |
| SYS_T::GPA_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PA0MFP | PA.0 Multi-function Pin Selection |
| [7:4] | PA1MFP | PA.1 Multi-function Pin Selection |
| [11:8] | PA2MFP | PA.2 Multi-function Pin Selection |
| [15:12] | PA3MFP | PA.3 Multi-function Pin Selection |
| [19:16] | PA4MFP | PA.4 Multi-function Pin Selection |
| [23:20] | PA5MFP | PA.5 Multi-function Pin Selection |
| [27:24] | PA6MFP | PA.6 Multi-function Pin Selection |
| [31:28] | PA7MFP | PA.7 Multi-function Pin Selection |
| SYS_T::GPB_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PB8MFP | PB.8 Multi-function Pin Selection |
| [7:4] | PB9MFP | PB.9 Multi-function Pin Selection |
| [11:8] | PB10MFP | PB.10 Multi-function Pin Selection |
| [15:12] | PB11MFP | PB.11 Multi-function Pin Selection |
| [19:16] | PB12MFP | PB.12 Multi-function Pin Selection |
| [23:20] | PB13MFP | PB.13 Multi-function Pin Selection |
| [27:24] | PB14MFP | PB.14 Multi-function Pin Selection |
| [31:28] | PB15MFP | PB.15 Multi-function Pin Selection |
| SYS_T::GPB_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PB0MFP | PB.0 Multi-function Pin Selection |
| [7:4] | PB1MFP | PB.1 Multi-function Pin Selection |
| [11:8] | PB2MFP | PB.2 Multi-function Pin Selection |
| [15:12] | PB3MFP | PB.3 Multi-function Pin Selection |
| [19:16] | PB4MFP | PB.4 Multi-function Pin Selection |
| [23:20] | PB5MFP | PB.5 Multi-function Pin Selection |
| [27:24] | PB6MFP | PB.6 Multi-function Pin Selection |
| [31:28] | PB7MFP | PB.7 Multi-function Pin Selection |
| SYS_T::GPC_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PC8MFP | PC.8 Multi-function Pin Selection |
| [7:4] | PC9MFP | PC.9 Multi-function Pin Selection |
| [11:8] | PC10MFP | PC.10 Multi-function Pin Selection |
| [15:12] | PC11MFP | PC.11 Multi-function Pin Selection |
| [19:16] | PC12MFP | PC.12 Multi-function Pin Selection |
| [23:20] | PC13MFP | PC.13 Multi-function Pin Selection |
| [27:24] | PC14MFP | PC.14 Multi-function Pin Selection |
| [31:28] | PC15MFP | PC.15 Multi-function Pin Selection |
| SYS_T::GPC_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PC0MFP | PC.0 Multi-function Pin Selection |
| [7:4] | PC1MFP | PC.1 Multi-function Pin Selection |
| [11:8] | PC2MFP | PC.2 Multi-function Pin Selection |
| [15:12] | PC3MFP | PC.3 Multi-function Pin Selection |
| [19:16] | PC4MFP | PC.4 Multi-function Pin Selection |
| [23:20] | PC5MFP | PC.5 Multi-function Pin Selection |
| [27:24] | PC6MFP | PC.6 Multi-function Pin Selection |
| [31:28] | PC7MFP | PC.7 Multi-function Pin Selection |
| SYS_T::GPD_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PD8MFP | PD.8 Multi-function Pin Selection |
| [7:4] | PD9MFP | PD.9 Multi-function Pin Selection |
| [11:8] | PD10MFP | PD.10 Multi-function Pin Selection |
| [15:12] | PD11MFP | PD.11 Multi-function Pin Selection |
| [19:16] | PD12MFP | PD.12 Multi-function Pin Selection |
| [23:20] | PD13MFP | PD.13 Multi-function Pin Selection |
| [27:24] | PD14MFP | PD.14 Multi-function Pin Selection |
| [31:28] | PD15MFP | PD.15 Multi-function Pin Selection |
| SYS_T::GPD_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PD0MFP | PD.0 Multi-function Pin Selection |
| [7:4] | PD1MFP | PD.1 Multi-function Pin Selection |
| [11:8] | PD2MFP | PD.2 Multi-function Pin Selection |
| [15:12] | PD3MFP | PD.3 Multi-function Pin Selection |
| [19:16] | PD4MFP | PD.4 Multi-function Pin Selection |
| [23:20] | PD5MFP | PD.5 Multi-function Pin Selection |
| [27:24] | PD6MFP | PD.6 Multi-function Pin Selection |
| [31:28] | PD7MFP | PD.7 Multi-function Pin Selection |
| SYS_T::GPE_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PE8MFP | PE.8 Multi-function Pin Selection |
| [7:4] | PE9MFP | PE.9 Multi-function Pin Selection |
| [11:8] | PE10MFP | PE.10 Multi-function Pin Selection |
| [15:12] | PE11MFP | PE.11 Multi-function Pin Selection |
| [19:16] | PE12MFP | PE.12 Multi-function Pin Selection |
| [23:20] | PE13MFP | PE.13 Multi-function Pin Selection |
| [27:24] | PE14_MFP | PE.14 Multi-function Pin Selection |
| SYS_T::GPE_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PE0MFP | PE.0 Multi-function Pin Selection |
| [7:4] | PE1MFP | PE.1 Multi-function Pin Selection |
| [11:8] | PE2MFP | PE.2 Multi-function Pin Selection |
| [15:12] | PE3MFP | PE.3 Multi-function Pin Selection |
| [19:16] | PE4MFP | PE.4 Multi-function Pin Selection |
| [23:20] | PE5MFP | PE.5 Multi-function Pin Selection |
| [27:24] | PE6MFP | PE.6 Multi-function Pin Selection |
| [31:28] | PE7MFP | PE.7 Multi-function Pin Selection |
| SYS_T::GPF_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PF0MFP | PF.0 Multi-function Pin Selection |
| [7:4] | PF1MFP | PF.1 Multi-function Pin Selection |
| [11:8] | PF2MFP | PF.2 Multi-function Pin Selection |
| [15:12] | PF3MFP | PF.3 Multi-function Pin Selection |
| [19:16] | PF4MFP | PF.4 Multi-function Pin Selection |
| [23:20] | PF5MFP | PF.5 Multi-function Pin Selection |
| [27:24] | PF6MFP | PF.6 Multi-function Pin Selection |
| [31:28] | PF7MFP | PF.7 Multi-function Pin Selection |
| USBH_T::HcBulkCurrentED |
| USBH_T::HcBulkHeadED |
| USBH_T::HcCommandStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HCR | Host Controller Reset |
| This bit is set to initiate the software reset of Host Controller. | ||
| This bit is cleared by the Host Controller, upon completed of the reset operation. | ||
| This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. | ||
| 0 = Host Controller is not in software reset state. | ||
| 1 = Host Controller is in software reset state. | ||
| [1] | CLF | Control List Filled |
| Set high to indicate there is an active TD on the Control List. | ||
| It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. | ||
| 0 = No active TD found or Host Controller begins to process the head of the Control list. | ||
| 1 = An active TD added or found on the Control list. | ||
| [2] | BLF | Bulk List Filled |
| Set high to indicate there is an active TD on the Bulk list. | ||
| This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. | ||
| 0 = No active TD found or Host Controller begins to process the head of the Bulk list. | ||
| 1 = An active TD added or found on the Bulk list. | ||
| [17:16] | SOC | Schedule Overrun Count |
| These bits are incremented on each scheduling overrun error. | ||
| It is initialized to 00b and wraps around at 11b. | ||
| This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set. |
| USBH_T::HcControl |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | CBSR | Control Bulk Service Ratio |
| This specifies the service ratio between Control and Bulk EDs. | ||
| Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. | ||
| The internal count will be retained when crossing the frame boundary. | ||
| In case of reset, HCD is responsible for restoring this. | ||
| Value. | ||
| 00 = Number of Control EDs over Bulk EDs served is 1:1. | ||
| 01 = Number of Control EDs over Bulk EDs served is 2:1. | ||
| 10 = Number of Control EDs over Bulk EDs served is 3:1. | ||
| 11 = Number of Control EDs over Bulk EDs served is 4:1. | ||
| [2] | PLE | Periodic List Enable Bit |
| When set, this bit enables processing of the Periodic (interrupt and Isochronous) list. | ||
| The Host Controller checks this bit prior to attempting any periodic transfers in a frame. | ||
| 0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame). | ||
| 1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame. | ||
| Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. | ||
| [3] | IE | Isochronous List Enable Bit |
| Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. | ||
| Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. | ||
| 0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame). | ||
| 1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too. | ||
| [4] | CLE | Control List Enable Bit |
| 0 = Disable processing of the Control list after next SOF (Start-Of-Frame). | ||
| 1 = Enable processing of the Control list in the next frame. | ||
| [5] | BLE | Bulk List Enable Bit |
| 0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame). | ||
| 1 = Enable processing of the Bulk list in the next frame. | ||
| [7:6] | HCFS | Host Controller Functional State |
| This field sets the Host Controller state. | ||
| The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. | ||
| States are: | ||
| 00 = USBSUSPEND. | ||
| 01 = USBRESUME. | ||
| 10 = USBOPERATIONAL. | ||
| 11 = USBRESET. |
| USBH_T::HcControlCurrentED |
| USBH_T::HcControlHeadED |
| USBH_T::HcDoneHead |
| USBH_T::HcFmInterval |
| Bits | Field | Descriptions |
|---|---|---|
| [13:0] | FI | Frame Interval |
| This field specifies the length of a frame as (bit times - 1). | ||
| For 12,000 bit times in a frame, a value of 11,999 is stored here. | ||
| [30:16] | FSMPS | FS Largest Data Packet |
| This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. | ||
| [31] | FIT | Frame Interval Toggle |
| This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]). | ||
| 0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]). | ||
| 1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]). |
| USBH_T::HcFmNumber |
| USBH_T::HcFmRemaining |
| Bits | Field | Descriptions |
|---|---|---|
| [13:0] | FR | Frame Remaining |
| When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. | ||
| When the count reaches 0, (end of frame) the counter reloads with Frame Interval. | ||
| In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. | ||
| [31] | FRT | Frame Remaining Toggle |
| This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0. |
| USBH_T::HcHCCA |
| USBH_T::HcInterruptDisable |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to SO (HcIntSts[0]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to SO (HcIntSts[0]) disabled. | ||
| 1 = Interrupt generation due to SO (HcIntSts[0]) enabled. | ||
| [1] | WDH | Write Back Done Head Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to WDH (HcIntSts[1]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to WDH (HcIntSts[1]) disabled. | ||
| 1 = Interrupt generation due to WDH (HcIntSts[1]) enabled. | ||
| [2] | SF | Start Of Frame Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to SF (HcIntSts[2]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to SF (HcIntSts[2]) disabled. | ||
| 1 = Interrupt generation due to SF (HcIntSts[2]) enabled. | ||
| [3] | RD | Resume Detected Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to RD (HcIntSts[3]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RD (HcIntSts[3]) disabled. | ||
| 1 = Interrupt generation due to RD (HcIntSts[3]) enabled. | ||
| [5] | FNO | Frame Number Overflow Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to FNO (HcIntSts[5]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to FNO (HcIntSts[5]) disabled. | ||
| 1 = Interrupt generation due to FNO (HcIntSts[5]) enabled. | ||
| [6] | RHSC | Root Hub Status Change Disable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to RHSC (HcIntSts[6]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled. | ||
| 1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled. | ||
| [31] | MIE | Master Interrupt Disable Bit |
| Global interrupt disable. Writing '1' to disable all interrupts. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high. | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high. | ||
| 1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high. |
| USBH_T::HcInterruptEnable |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to SO (HcIntSts[0]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to SO (HcIntSts[0]) disabled. | ||
| 1 = Interrupt generation due to SO (HcIntSts[0]) enabled. | ||
| [1] | WDH | Write Back Done Head Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to WDH (HcIntSts[1]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to WDH (HcIntSts[1]) disabled. | ||
| 1 = Interrupt generation due to WDH (HcIntSts[1]) enabled. | ||
| [2] | SF | Start Of Frame Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to SF (HcIntSts[2]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to SF (HcIntSts[2]) disabled. | ||
| 1 = Interrupt generation due to SF (HcIntSts[2]) enabled. | ||
| [3] | RD | Resume Detected Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to RD (HcIntSts[3]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RD (HcIntSts[3]) disabled. | ||
| 1 = Interrupt generation due to RD (HcIntSts[3]) enabled. | ||
| [5] | FNO | Frame Number Overflow Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to FNO (HcIntSts[5]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to FNO (HcIntSts[5]) disabled. | ||
| 1 = Interrupt generation due to FNO (HcIntSts[5]) enabled. | ||
| [6] | RHSC | Root Hub Status Change Enable Bit |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to RHSC (HcIntSts[6]). | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled. | ||
| 1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled. | ||
| [31] | MIE | Master Interrupt Enable Bit |
| This bit is a global interrupt enable. | ||
| A write of '1' allows interrupts to be enabled via the specific enable bits listed above. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high. | ||
| Read Operation: | ||
| 0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high. | ||
| 1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high. |
| USBH_T::HcInterruptStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun |
| Set when the List Processor determines a Schedule Overrun has occurred. | ||
| 0 = Schedule Overrun didn't occur. | ||
| 1 = Schedule Overrun has occurred. | ||
| [1] | WDH | Write Back Done Head |
| Set after the Host Controller has written HcDoneHead to HccaDoneHead. | ||
| Further updates of the HccaDoneHead will not occur until this bit has been cleared. | ||
| 0 =.Host Controller didn't update HccaDoneHead. | ||
| 1 =.Host Controller has written HcDoneHead to HccaDoneHead. | ||
| [2] | SF | Start Of Frame |
| Set when the Frame Management functional block signals a 'Start of Frame' event. | ||
| Host Control generates a SOF token at the same time. | ||
| 0 =.Not the start of a frame. | ||
| 1 =.Indicate the start of a frame and Host Controller generates a SOF token. | ||
| [3] | RD | Resume Detected |
| Set when Host Controller detects resume signaling on a downstream port. | ||
| 0 = No resume signaling detected on a downstream port. | ||
| 1 = Resume signaling detected on a downstream port. | ||
| [5] | FNO | Frame Number Overflow |
| This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. | ||
| 0 = The bit 15 of Frame Number didn't change. | ||
| 1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. | ||
| [6] | RHSC | Root Hub Status Change |
| This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed. | ||
| 0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change. | ||
| 1 = The content of HcRhSts or the content of HcRhPrt1 register has changed. |
| USBH_T::HcLSThreshold |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | LST | Low-Speed Threshold |
| This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction. | ||
| The transaction is started only if FR (HcFmRem[13:0]) >= this field. | ||
| The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. |
| USBH_T::HcMiscControl |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | ABORT | AHB Bus ERROR Response |
| This bit indicates there is an ERROR response received in AHB bus. | ||
| 0 = No ERROR response received. | ||
| 1 = ERROR response received. | ||
| [3] | OCAL | Over Current Active Low |
| This bit controls the polarity of over current flag from external power IC. | ||
| 0 = Over current flag is high active. | ||
| 1 = Over current flag is low active. | ||
| [16] | DPRT1 | Disable Port 1 |
| This bit controls if the connection between USB host controller and transceiver of port 1 is disabled. | ||
| If the connection is disabled, the USB host controller will not recognize any event of USB bus. | ||
| Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. | ||
| 0 = The connection between USB host controller and transceiver of port 1 is enabled. | ||
| 1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode. |
| USBH_T::HcPeriodCurrentED |
| USBH_T::HcPeriodicStart |
| USBH_T::HcPhyControl |
| Bits | Field | Descriptions |
|---|---|---|
| [27] | STBYEN | USB Transceiver Standby Enable Bit |
| This bit controls if USB transceiver could enter the standby mode to reduce power consumption. | ||
| 0 = The USB transceiver would never enter the standby mode. | ||
| 1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). |
| USBH_T::HcRevision |
| USBH_T::HcRhDescriptorA |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | NDP | Number Downstream Ports |
| USB host control supports two downstream ports and only one port is available in this series of chip. | ||
| [8] | PSM | Power Switching Mode |
| This bit is used to specify how the power switching of the Root Hub ports is controlled. | ||
| 0 = Global Switching. | ||
| 1 = Individual Switching. | ||
| [11] | OCPM | Over Current Protection Mode |
| This bit describes how the over current status for the Root Hub ports reported. | ||
| This bit is only valid when NOCP (HcRhDeA[12]) is cleared. | ||
| 0 = Global Over current. | ||
| 1 = Individual Over current. | ||
| [12] | NOCP | No Over Current Protection |
| This bit describes how the over current status for the Root Hub ports reported. | ||
| 0 = Over current status is reported. | ||
| 1 = Over current status is not reported. |
| USBH_T::HcRhDescriptorB |
| Bits | Field | Descriptions |
|---|---|---|
| [31:16] | PPCM | Port Power Control Mask |
| Global power switching. | ||
| This field is only valid if PowerSwitchingMode is set (individual port switching). | ||
| When set, the port only responds to individual port power switching commands (Set/ClearPortPower). | ||
| When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). | ||
| 0 = Port power controlled by global power switching. | ||
| 1 = Port power controlled by port power switching. | ||
| Note: PPCM[15:2] and PPCM[0] are reserved. |
| USBH_T::HcRhPortStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CCS | CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write) |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Clear port enable. | ||
| Read Operation: | ||
| 0 = No device connected. | ||
| 1 = Device connected. | ||
| [1] | PES | Port Enable Status |
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Set port enable. | ||
| Read Operation: | ||
| 0 = Port Disabled. | ||
| 1 = Port Enabled. | ||
| [2] | PSS | Port Suspend Status |
| This bit indicates the port is suspended | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Set port suspend. | ||
| Read Operation: | ||
| 0 = Port is not suspended. | ||
| 1 = Port is selectively suspended. | ||
| [3] | POCI | Port Over Current Indicator (Read) Or Clear Port Suspend (Write) |
| This bit reflects the state of the over current status pin dedicated to this port. | ||
| This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set. | ||
| This bit is also used to initiate the selective result sequence for the port. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Clear port suspend. | ||
| Read Operation: | ||
| 0 = No over current condition. | ||
| 1 = Over current condition. | ||
| [4] | PRS | Port Reset Status |
| This bit reflects the reset state of the port. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Set port reset. | ||
| Read Operation | ||
| 0 = Port reset signal is not active. | ||
| 1 = Port reset signal is active. | ||
| [8] | PPS | Port Power Status |
| This bit reflects the power state of the port regardless of the power switching mode. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Port Power Enabled. | ||
| Read Operation: | ||
| 0 = Port power is Disabled. | ||
| 1 = Port power is Enabled. | ||
| [9] | LSDA | Low Speed Device Attached (Read) Or Clear Port Power (Write) |
| This bit defines the speed (and bud idle) of the attached device. | ||
| It is only valid when CCS (HcRhPrt1[0]) is set. | ||
| This bit is also used to clear port power. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Clear PPS (HcRhPrt1[8]). | ||
| Read Operation: | ||
| 0 = Full Speed device. | ||
| 1 = Low-speed device. | ||
| [16] | CSC | Connect Status Change |
| This bit indicates connect or disconnect event has been detected (CCS | ||
| (HcRhPrt1[0]) changed). | ||
| Write 1 to clear this bit to zero. | ||
| 0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change). | ||
| 1 = Hardware detection of connect/disconnect event (CCS | ||
| (HcRhPrt1[0]) changed). | ||
| [17] | PESC | Port Enable Status Change |
| This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event. | ||
| Write 1 to clear this bit to zero. | ||
| 0 = PES (HcRhPrt1[1]) didn't change. | ||
| 1 = PES (HcRhPrt1[1]) changed. | ||
| [18] | PSSC | Port Suspend Status Change |
| This bit indicates the completion of the selective resume sequence for the port. | ||
| Write 1 to clear this bit to zero. | ||
| 0 = Port resume is not completed. | ||
| 1 = Port resume completed. | ||
| [19] | OCIC | Port Over Current Indicator Change |
| This bit is set when POCI (HcRhPrt1[3]) changes. | ||
| Write 1 to clear this bit to zero. | ||
| 0 = POCI (HcRhPrt1[3]) didn't change. | ||
| 1 = POCI (HcRhPrt1[3]) changes. | ||
| [20] | PRSC | Port Reset Status Change |
| This bit indicates that the port reset signal has completed. | ||
| Write 1 to clear this bit to zero. | ||
| 0 = Port reset is not complete. | ||
| 1 = Port reset is complete. |
| USBH_T::HcRhStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | LPS | Clear Global Power |
| In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power. | ||
| This bit always read as zero. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Clear global power. | ||
| [1] | OCI | Over Current Indicator |
| This bit reflects the state of the over current status pin. | ||
| This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. | ||
| 0 = No over current condition. | ||
| 1 = Over current condition. | ||
| [15] | DRWE | Device Remote Wakeup Enable Bit |
| This bit controls if port's Connect Status Change as a remote wake-up event. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Enable Connect Status Change as a remote wake-up event. | ||
| Read Operation: | ||
| 0 = Connect Status Change as a remote wake-up event disabled. | ||
| 1 = Connect Status Change as a remote wake-up event enabled. | ||
| [16] | LPSC | Set Global Power |
| In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports. | ||
| This bit always read as zero. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Set global power. | ||
| [17] | OCIC | Over Current Indicator Change |
| This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]). | ||
| Write 1 to clear this bit to zero. | ||
| 0 = OCI (HcRhSts[1]) didn't change. | ||
| 1 = OCI (HcRhSts[1]) change. | ||
| [31] | CRWE | Clear Remote Wake-up Enable Bit |
| This bit is use to clear DRWE (HcRhSts[15]). | ||
| This bit always read as zero. | ||
| Write Operation: | ||
| 0 = No effect. | ||
| 1 = Clear DRWE (HcRhSts[15]). |
| SPI_T::I2SCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MCLKDIV | Master Clock Divider |
| If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. | ||
| The master clock rate, F_MCLK, is determined by the following expressions. | ||
| If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)). | ||
| If MCLKDIV = 0, F_MCLK = F_I2SCLK. | ||
| F_I2SCLK is the frequency of I2S peripheral clock. | ||
| In general, the master clock rate is 256 times sampling clock rate. | ||
| [16:8] | BCLKDIV | Bit Clock Divider |
| The I2S controller will generate bit clock in Master mode. | ||
| The bit clock rate, F_BCLK, is determined by the following expression. | ||
| F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock. |
| SPI_T::I2SCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SEN | I2S Controller Enable Bit |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: If enable this bit, I2Sn_BCLK will start to output in master mode. | ||
| [1] | TXEN | Transmit Enable Bit |
| 0 = Data transmit Disabled. | ||
| 1 = Data transmit Enabled. | ||
| [2] | RXEN | Receive Enable Bit |
| 0 = Data receiving Disabled. | ||
| 1 = Data receiving Enabled. | ||
| [3] | MUTE | Transmit Mute Enable Bit |
| 0 = Transmit data is shifted from buffer. | ||
| 1= Transmit channel zero. | ||
| [5:4] | WDWIDTH | Word Width |
| 00 = data is 8-bit. | ||
| 01 = data is 16-bit. | ||
| 10 = data is 24-bit. | ||
| 11 = data is 32-bit. | ||
| [6] | MONO | Monaural Data |
| 0 = Data is stereo format. | ||
| 1 = Data is monaural format. | ||
| [7] | ORDER | Stereo Data Order In FIFO |
| 0 = Left channel data at high byte. | ||
| 1 = Left channel data at low byte. | ||
| [8] | SLAVE | Slave Mode |
| I2S can operate as master or slave. | ||
| For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M4521 to Audio CODEC chip. | ||
| In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip. | ||
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [15] | MCLKEN | Master Clock Enable Bit |
| If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices. | ||
| 0 = Master clock Disabled. | ||
| 1 = Master clock Enabled. | ||
| [16] | RZCEN | Right Channel Zero Cross Detection Enable Bit |
| If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1. | ||
| This function is only available in transmit operation. | ||
| 0 = Right channel zero cross detection Disabled. | ||
| 1 = Right channel zero cross detection Enabled. | ||
| [17] | LZCEN | Left Channel Zero Cross Detection Enable Bit |
| If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1. | ||
| This function is only available in transmit operation. | ||
| 0 = Left channel zero cross detection Disabled. | ||
| 1 = Left channel zero cross detection Enabled. | ||
| [23] | RXLCH | Receive Left Channel Enable Bit |
| When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. | ||
| 0 = Receive right channel data in Mono mode. | ||
| 1 = Receive left channel data in Mono mode. | ||
| [24] | RZCIEN | Right Channel Zero-Cross Interrupt Enable Bit |
| Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [25] | LZCIEN | Left Channel Zero-Cross Interrupt Enable Bit |
| Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [29:28] | FORMAT | Data Format Selection |
| 00 = I2S data format. | ||
| 01 = MSB justified data format. | ||
| 10 = PCM mode A. | ||
| 11 = PCM mode B. |
| SPI_T::I2SSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [4] | RIGHT | Right Channel (Read Only) |
| This bit indicates the current transmit data is belong to which channel. | ||
| 0 = Left channel. | ||
| 1 = Right channel. | ||
| [8] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = Receive FIFO buffer is not empty. | ||
| 1 = Receive FIFO buffer is empty. | ||
| [9] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) |
| 0 = Receive FIFO buffer is not full. | ||
| 1 = Receive FIFO buffer is full. | ||
| [10] | RXTHIF | Receive FIFO Threshold Interrupt Flag (Read Only) |
| 0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH. | ||
| 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. | ||
| Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. | ||
| [11] | RXOVIF | Receive FIFO Overrun Interrupt Flag |
| When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [12] | RXTOIF | Receive Time-Out Interrupt Flag |
| 0 = No receive FIFO time-out event. | ||
| 1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. | ||
| When the received FIFO buffer is read by software, the time-out status will be cleared automatically. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [15] | I2SENSTS | I2S Enable Status (Read Only) |
| 0 = The SPI/I2S control logic is disabled. | ||
| 1 = The SPI/I2S control logic is enabled. | ||
| Note: The SPI peripheral clock is asynchronous with the system clock. | ||
| In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user. | ||
| [16] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = Transmit FIFO buffer is not empty. | ||
| 1 = Transmit FIFO buffer is empty. | ||
| [17] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = Transmit FIFO buffer is not full. | ||
| 1 = Transmit FIFO buffer is full. | ||
| [18] | TXTHIF | Transmit FIFO Threshold Interrupt Flag (Read Only) |
| 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. | ||
| 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. | ||
| Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request. | ||
| [19] | TXUFIF | Transmit FIFO Underflow Interrupt Flag |
| When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, | ||
| the output data depends on the setting of TXUFPOL and this bit will be set to 1. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [20] | RZCIF | Right Channel Zero Cross Interrupt Flag |
| 0 = No zero cross event occurred on right channel. | ||
| 1 = Zero cross event occurred on right channel. | ||
| [21] | LZCIF | Left Channel Zero Cross Interrupt Flag |
| 0 = No zero cross event occurred on left channel. | ||
| 1 = Zero cross event occurred on left channel. | ||
| [23] | TXRXRST | TX or RX Reset Status (Read Only) |
| 0 = The reset function of TXRST or RXRST is done. | ||
| 1 = Doing the reset function of TXRST or RXRST. | ||
| Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles. | ||
| User can check the status of this bit to monitor the reset function is doing or done. | ||
| [26:24] | RXCNT | Receive FIFO Data Count (Read Only) |
| This bit field indicates the valid data count of receive FIFO buffer. | ||
| [30:28] | TXCNT | Transmit FIFO Data Count (Read Only) |
| This bit field indicates the valid data count of transmit FIFO buffer. |
| PWM_T::IFA |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | IFCNT0_1 | PWM_CH0 And PWM_CH1 Interrupt Flag Counter |
| The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. | ||
| PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period. | ||
| [6:4] | IFSEL0_1 | PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select |
| 000 = CNT equal to Zero in channel 0. | ||
| 001 = CNT equal to PERIOD in channel 0. | ||
| 010 = CNT equal to CMPU in channel 0. | ||
| 011 = CNT equal to CMPD in channel 0. | ||
| 100 = CNT equal to Zero in channel 1. | ||
| 101 = CNT equal to PERIOD in channel 1. | ||
| 110 = CNT equal to CMPU in channel 1. | ||
| 111 = CNT equal to CMPD in channel 1. | ||
| [7] | IFAEN0_1 | PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable |
| 0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable. | ||
| 1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable. | ||
| [11:8] | IFCNT2_3 | PWM_CH2 And PWM_CH3 Interrupt Flag Counter |
| The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. | ||
| PWM flag will be set in every IFCNT2_3[3:0] times of PWM period. | ||
| [14:12] | IFSEL2_3 | PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select |
| 000 = CNT equal to Zero in channel 2. | ||
| 001 = CNT equal to PERIOD in channel 2. | ||
| 010 = CNT equal to CMPU in channel 2. | ||
| 011 = CNT equal to CMPD in channel 2. | ||
| 100 = CNT equal to Zero in channel 3. | ||
| 101 = CNT equal to PERIOD in channel 3. | ||
| 110 = CNT equal to CMPU in channel 3. | ||
| 111 = CNT equal to CMPD in channel 3. | ||
| [15] | IFAEN2_3 | PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable |
| 0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable. | ||
| 1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable. | ||
| [19:16] | IFCNT4_5 | PWM_CH4 And PWM_CH5 Interrupt Flag Counter |
| The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. | ||
| PWM flag will be set in every IFCNT4_5[3:0] times of PWM period. | ||
| [22:20] | IFSEL4_5 | PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select |
| 000 = CNT equal to Zero in channel 4. | ||
| 001 = CNT equal to PERIOD in channel 4. | ||
| 010 = CNT equal to CMPU in channel 4. | ||
| 011 = CNT equal to CMPD in channel 4. | ||
| 100 = CNT equal to Zero in channel 5. | ||
| 101 = CNT equal to PERIOD in channel 5. | ||
| 110 = CNT equal to CMPU in channel 5. | ||
| 111 = CNT equal to CMPD in channel 5. | ||
| [23] | IFAEN4_5 | PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable |
| 0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable. | ||
| 1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable. |
| RTC_T::INIT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INIT[0]/ACTIVE | RTC Active Status (Read Only) |
| 0 = RTC is at reset state. | ||
| 1 = RTC is at normal active state. | ||
| [31:1] | INIT[31:1] | RTC Initiation |
| When RTC block is powered on, RTC is at reset state. | ||
| User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. | ||
| Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. | ||
| The INIT is a write-only field and read value will be always 0. |
| GPIO_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | FLIENn | Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| PDMA_T::INTEN |
| RTC_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ALMIEN | Alarm Interrupt Enable Bit |
| 0 = RTC Alarm interrupt Disabled. | ||
| 1 = RTC Alarm interrupt Enabled. | ||
| [1] | TICKIEN | Time Tick Interrupt Enable Bit |
| 0 = RTC Time Tick interrupt Disabled. | ||
| 1 = RTC Time Tick interrupt Enabled. | ||
| [2] | SNPDIEN | Snoop Detection Interrupt Enable Bit |
| 0 = Snoop detected interrupt Disabled. | ||
| 1 = Snoop detected interrupt Enabled. |
| SC_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIEN | Receive Data Reach Interrupt Enable Bit |
| This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable. | ||
| 0 = Receive data reach trigger level interrupt Disabled. | ||
| 1 = Receive data reach trigger level interrupt Enabled. | ||
| [1] | TBEIEN | Transmit Buffer Empty Interrupt Enable Bit |
| This field is used for transmit buffer empty interrupt enable. | ||
| 0 = Transmit buffer empty interrupt Disabled. | ||
| 1 = Transmit buffer empty interrupt Enabled. | ||
| [2] | TERRIEN | Transfer Error Interrupt Enable Bit |
| This field is used for transfer error interrupt enable. | ||
| The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). | ||
| 0 = Transfer error interrupt Disabled. | ||
| 1 = Transfer error interrupt Enabled. | ||
| [3] | TMR0IEN | Timer0 Interrupt Enable Bit |
| This field is used to enable TMR0 interrupt enable. | ||
| 0 = Timer0 interrupt Disabled. | ||
| 1 = Timer0 interrupt Enabled. | ||
| [4] | TMR1IEN | Timer1 Interrupt Enable Bit |
| This field is used to enable the TMR1 interrupt. | ||
| 0 = Timer1 interrupt Disabled. | ||
| 1 = Timer1 interrupt Enabled. | ||
| [5] | TMR2IEN | Timer2 Interrupt Enable Bit |
| This field is used for TMR2 interrupt enable. | ||
| 0 = Timer2 interrupt Disabled. | ||
| 1 = Timer2 interrupt Enabled. | ||
| [6] | BGTIEN | Block Guard Time Interrupt Enable Bit |
| This field is used for block guard time interrupt enable. | ||
| 0 = Block guard time Disabled. | ||
| 1 = Block guard time Enabled. | ||
| [7] | CDIEN | Card Detect Interrupt Enable Bit |
| This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) | ||
| 0 = Card detect interrupt Disabled. | ||
| 1 = Card detect interrupt Enabled. | ||
| [8] | INITIEN | Initial End Interrupt Enable Bit |
| This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable. | ||
| 0 = Initial end interrupt Disabled. | ||
| 1 = Initial end interrupt Enabled. | ||
| [9] | RXTOIF | Receiver Buffer Time-Out Interrupt Enable Bit |
| This field is used for receiver buffer time-out interrupt enable. | ||
| 0 = Receiver buffer time-out interrupt Disabled. | ||
| 1 = Receiver buffer time-out interrupt Enabled. | ||
| [10] | ACERRIEN | Auto Convention Error Interrupt Enable Bit |
| This field is used for auto-convention error interrupt enable. | ||
| 0 = Auto-convention error interrupt Disabled. | ||
| 1 = Auto-convention error interrupt Enabled. |
| UART_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIEN | Receive Data Available Interrupt Enable Bit |
| 0 = Receive data available interrupt Disabled. | ||
| 1 = Receive data available interrupt Enabled. | ||
| [1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit |
| 0 = Transmit holding register empty interrupt Disabled. | ||
| 1 = Transmit holding register empty interrupt Enabled. | ||
| [2] | RLSIEN | Receive Line Status Interrupt Enable Bit |
| 0 = Receive Line Status interrupt Disabled. | ||
| 1 = Receive Line Status interrupt Enabled. | ||
| [3] | MODEMIEN | Modem Status Interrupt Enable Bit |
| 0 = Modem status interrupt Disabled. | ||
| 1 = Modem status interrupt Enabled. | ||
| [4] | RXTOIEN | RX Time-Out Interrupt Enable Bit |
| 0 = RX time-out interrupt Disabled. | ||
| 1 = RX time-out interrupt Enabled. | ||
| [5] | BUFERRIEN | Buffer Error Interrupt Enable Bit |
| 0 = Buffer error interrupt Disabled. | ||
| 1 = Buffer error interrupt Enabled. | ||
| [8] | LINIEN | LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3) |
| 0 = LIN bus interrupt Disabled. | ||
| 1 = LIN bus interrupt Enabled. | ||
| Note: This bit is used for LIN function mode. | ||
| [9] | WKCTSIEN | nCTS Wake-Up Interrupt Enable Bit |
| 0 = nCTS wake-up system function Disabled. | ||
| 1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode. | ||
| [10] | WKDATIEN | Incoming Data Wake-Up Interrupt Enable Bit |
| 0 = Incoming data wake-up system function Disabled. | ||
| 1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode. | ||
| Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable | ||
| [11] | TOCNTEN | Time-Out Counter Enable Bit |
| 0 = Time-out counter Disabled. | ||
| 1 = Time-out counter Enabled. | ||
| [12] | ATORTSEN | nRTS Auto-Flow Control Enable Bit |
| 0 = nRTS auto-flow control Disabled. | ||
| 1 = nRTS auto-flow control Enabled. | ||
| Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. | ||
| [13] | ATOCTSEN | nCTS Auto-Flow Control Enable Bit |
| 0 = nCTS auto-flow control Disabled. | ||
| 1 = nCTS auto-flow control Enabled. | ||
| Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). | ||
| [14] | TXPDMAEN | TX DMA Enable Bit |
| This bit can enable or disable TX DMA service. | ||
| 0 = TX DMA Disabled. | ||
| 1 = TX DMA Enabled. | ||
| [15] | RXPDMAEN | RX DMA Enable Bit |
| This bit can enable or disable RX DMA service. | ||
| 0 = RX DMA Disabled. | ||
| 1 = RX DMA Enabled. | ||
| [18] | ABRIEN | Auto-Baud Rate Interrupt Enable Bit |
| 0 = Auto-baud rate interrupt Disabled. | ||
| 1 = Auto-baud rate interrupt Enabled. |
| USBD_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSIEN | Bus Event Interrupt Enable |
| 0 = BUS event interrupt Disabled. | ||
| 1 = BUS event interrupt Enabled. | ||
| [1] | USBIEN | USB Event Interrupt Enable |
| 0 = USB event interrupt Disabled. | ||
| 1 = USB event interrupt Enabled. | ||
| [2] | VBDETIEN | VBUS Detection Interrupt Enable |
| 0 = Floating detection Interrupt Disabled. | ||
| 1 = Floating detection Interrupt Enabled. | ||
| [3] | NEVWKIEN | USB No-Event-Wake-Up Interrupt Enable |
| 0 = No-Event-Wake-up Interrupt Disabled. | ||
| 1 = No-Event-Wake-up Interrupt Enabled. | ||
| [8] | WKEN | Wake-Up Function Enable |
| 0 = USB wake-up function Disabled. | ||
| 1 = USB wake-up function Enabled. | ||
| [15] | INNAKEN | Active NAK Function And Its Status In IN Token |
| 0 = When device responds NAK after receiving IN token, IN NAK status will not be | ||
| updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted. | ||
| 1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event | ||
| will be asserted, when the device responds NAK after receiving IN token. |
| PWM_T::INTEN0 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | ZIENn | PWM Zero Point Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Zero point interrupt Disabled. | ||
| 1 = Zero point interrupt Enabled. | ||
| Note: Odd channels will read always 0 at complementary mode. | ||
| [7] | IFAIEN0_1 | PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable |
| 0 = Interrupt Flag accumulator interrupt Disabled. | ||
| 1 = Interrupt Flag accumulator interrupt Enabled. | ||
| [13:8] | PIENn | PWM Period Point Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Period point interrupt Disabled. | ||
| 1 = Period point interrupt Enabled. | ||
| Note1: When up-down counter type period point means center point. | ||
| Note2: Odd channels will read always 0 at complementary mode. | ||
| [15] | IFAIEN2_3 | PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable |
| 0 = Interrupt Flag accumulator interrupt Disabled. | ||
| 1 = Interrupt Flag accumulator interrupt Enabled. | ||
| [21:16] | CMPUIENn | PWM Compare Up Count Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Compare up count interrupt Disabled. | ||
| 1 = Compare up count interrupt Enabled. | ||
| Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. | ||
| [23] | IFAIEN4_5 | PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable |
| 0 = Interrupt Flag accumulator interrupt Disabled. | ||
| 1 = Interrupt Flag accumulator interrupt Enabled. | ||
| [29:24] | CMPDIENn | PWM Compare Down Count Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Compare down count interrupt Disabled. | ||
| 1 = Compare down count interrupt Enabled. | ||
| Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
| PWM_T::INTEN1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKEIEN0_1 | PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel0/1 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel0/1 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [1] | BRKEIEN2_3 | PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel2/3 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel2/3 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [2] | BRKEIEN4_5 | PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel4/5 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel4/5 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [8] | BRKLIEN0_1 | PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel0/1 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel0/1 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [9] | BRKLIEN2_3 | PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel2/3 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel2/3 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [10] | BRKLIEN4_5 | PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel4/5 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel4/5 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| EADC_T::INTSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SPLIE0 | Sample Module 0 Interrupt Enable Bit |
| 0 = Sample Module 0 interrupt Disabled. | ||
| 1 = Sample Module 0 interrupt Enabled. | ||
| [1] | SPLIE1 | Sample Module 1 Interrupt Enable Bit |
| 0 = Sample Module 1 interrupt Disabled. | ||
| 1 = Sample Module 1 interrupt Enabled. | ||
| [2] | SPLIE2 | Sample Module 2 Interrupt Enable Bit |
| 0 = Sample Module 2 interrupt Disabled. | ||
| 1 = Sample Module 2 interrupt Enabled. | ||
| [3] | SPLIE3 | Sample Module 3 Interrupt Enable Bit |
| 0 = Sample Module 3 interrupt Disabled. | ||
| 1 = Sample Module 3 interrupt Enabled. | ||
| [4] | SPLIE4 | Sample Module 4 Interrupt Enable Bit |
| 0 = Sample Module 4 interrupt Disabled. | ||
| 1 = Sample Module 4 interrupt Enabled. | ||
| [5] | SPLIE5 | Sample Module 5 Interrupt Enable Bit |
| 0 = Sample Module 5 interrupt Disabled. | ||
| 1 = Sample Module 5 interrupt Enabled. | ||
| [6] | SPLIE6 | Sample Module 6 Interrupt Enable Bit |
| 0 = Sample Module 6 interrupt Disabled. | ||
| 1 = Sample Module 6 interrupt Enabled. | ||
| [7] | SPLIE7 | Sample Module 7 Interrupt Enable Bit |
| 0 = Sample Module 7 interrupt Disabled. | ||
| 1 = Sample Module 7 interrupt Enabled. | ||
| [8] | SPLIE8 | Sample Module 8 Interrupt Enable Bit |
| 0 = Sample Module 8 interrupt Disabled. | ||
| 1 = Sample Module 8 interrupt Enabled. | ||
| [9] | SPLIE9 | Sample Module 9 Interrupt Enable Bit |
| 0 = Sample Module 9 interrupt Disabled. | ||
| 1 = Sample Module 9 interrupt Enabled. | ||
| [10] | SPLIE10 | Sample Module 10 Interrupt Enable Bit |
| 0 = Sample Module 10 interrupt Disabled. | ||
| 1 = Sample Module 10 interrupt Enabled. | ||
| [11] | SPLIE11 | Sample Module 11 Interrupt Enable Bit |
| 0 = Sample Module 11 interrupt Disabled. | ||
| 1 = Sample Module 11 interrupt Enabled. | ||
| [12] | SPLIE12 | Sample Module 12 Interrupt Enable Bit |
| 0 = Sample Module 12 interrupt Disabled. | ||
| 1 = Sample Module 12 interrupt Enabled. | ||
| [13] | SPLIE13 | Sample Module 13 Interrupt Enable Bit |
| 0 = Sample Module 13 interrupt Disabled. | ||
| 1 = Sample Module 13 interrupt Enabled. | ||
| [14] | SPLIE14 | Sample Module 14 Interrupt Enable Bit |
| 0 = Sample Module 14 interrupt Disabled. | ||
| 1 = Sample Module 14 interrupt Enabled. | ||
| [15] | SPLIE15 | Sample Module 15 Interrupt Enable Bit |
| 0 = Sample Module 15 interrupt Disabled. | ||
| 1 = Sample Module 15 interrupt Enabled. | ||
| [16] | SPLIE16 | Sample Module 16 Interrupt Enable Bit |
| 0 = Sample Module 16 interrupt Disabled. | ||
| 1 = Sample Module 16 interrupt Enabled. | ||
| [17] | SPLIE17 | Sample Module 17 Interrupt Enable Bit |
| 0 = Sample Module 17 interrupt Disabled. | ||
| 1 = Sample Module 17 interrupt Enabled. | ||
| [18] | SPLIE18 | Sample Module 18 Interrupt Enable Bit |
| 0 = Sample Module 18 interrupt Disabled. | ||
| 1 = Sample Module 18 interrupt Enabled. |
| GPIO_T::INTSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | INTSRCn | Port A-F Pin[n] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| PDMA_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ABTIF | PDMA Read/Write Target Abort Interrupt Flag (Read-Only) |
| This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. | ||
| 0 = No AHB bus ERROR response received. | ||
| 1 = AHB bus ERROR response received. | ||
| [1] | TDIF | Transfer Done Interrupt Flag (Read Only) |
| This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. | ||
| 0 = Not finished yet. | ||
| 1 = PDMA channel has finished transmission. | ||
| [2] | TEIF | Table Empty Interrupt Flag (Read Only) |
| This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode. | ||
| User can read TEIF register to indicate which channel finished transfer. | ||
| 0 = PDMA channel transfer is not finished. | ||
| 1 = PDMA channel transfer is finished and the operation is in idle state. | ||
| [8:15] | REQTOFn | Request Time-out Flag For Each Channel [N] |
| This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits. | ||
| 0 = No request time-out. | ||
| 1 = Peripheral request time-out. |
| RTC_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ALMIF | RTC Alarm Interrupt Flag |
| When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. | ||
| Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode. | ||
| 0 = Alarm condition is not matched. | ||
| 1 = Alarm condition is matched. | ||
| Note: Write 1 to clear this bit. | ||
| [1] | TICKIF | RTC Time Tick Interrupt Flag |
| When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. | ||
| Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode. | ||
| 0 = Tick condition does not occur. | ||
| 1 = Tick condition occur. | ||
| Note: Write 1 to clear to clear this bit. | ||
| [2] | SNPDIF | Snoop Detect Interrupt Flag |
| When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. | ||
| Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled. | ||
| 0 = No snoop event is detected. | ||
| 1 = Snoop event is detected. | ||
| Note: Write 1 to clear this bit. |
| SC_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIF | Receive Data Reach Interrupt Status Flag (Read Only) |
| This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. | ||
| Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). | ||
| If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. | ||
| [1] | TBEIF | Transmit Buffer Empty Interrupt Status Flag (Read Only) |
| This field is used for transmit buffer empty interrupt status flag. | ||
| Note: This field is the status flag of transmit buffer empty state. | ||
| If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. | ||
| [2] | TERRIF | Transfer Error Interrupt Status Flag (Read Only) |
| This field is used for transfer error interrupt status flag. | ||
| The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]). | ||
| Note: This field is the status flag of | ||
| BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]). | ||
| So, if software wants to clear this bit, software must write 1 to each field. | ||
| [3] | TMR0IF | Timer0 Interrupt Status Flag (Read Only) |
| This field is used for TMR0 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [4] | TMR1IF | Timer1 Interrupt Status Flag (Read Only) |
| This field is used for TMR1 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [5] | TMR2IF | Timer2 Interrupt Status Flag (Read Only) |
| This field is used for TMR2 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [6] | BGTIF | Block Guard Time Interrupt Status Flag (Read Only) |
| This field is used for block guard time interrupt status flag. | ||
| Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. | ||
| Note2: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [7] | CDIF | Card Detect Interrupt Status Flag (Read Only) |
| This field is used for card detect interrupt status flag. | ||
| The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]). | ||
| Note: | ||
| This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. | ||
| So if software wants to clear this bit, software must write 1 to this field. | ||
| [8] | INITIF | Initial End Interrupt Status Flag (Read Only) |
| This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [9] | RBTOIF | Receiver Buffer Time-Out Interrupt Status Flag (Read Only) |
| This field is used for receiver buffer time-out interrupt status flag. | ||
| Note: This field is the status flag of receiver buffer time-out state. | ||
| If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,. | ||
| [10] | ACERRIF | Auto Convention Error Interrupt Status Flag (Read Only) |
| This field indicates auto convention sequence error. | ||
| If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. |
| TIMER_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TIF | Timer Interrupt Flag |
| This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. | ||
| 0 = No effect. | ||
| 1 = CNT value matches the CMPDAT value. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [1] | TWKF | Timer Wake-Up Flag |
| This bit indicates the interrupt wake-up flag status of timer. | ||
| 0 = Timer does not cause CPU wake-up. | ||
| 1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. |
| UART_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIF | Receive Data Available Interrupt Flag (Read Only) |
| When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. | ||
| If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. | ||
| 0 = No RDA interrupt flag is generated. | ||
| 1 = RDA interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])). | ||
| [1] | THREIF | Transmit Holding Register Empty Interrupt Flag (Read Only) |
| This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. | ||
| If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. | ||
| 0 = No THRE interrupt flag is generated. | ||
| 1 = THRE interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). | ||
| [2] | RLSIF | Receive Line Interrupt Flag (Read Only) |
| This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). | ||
| If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. | ||
| 0 = No RLS interrupt flag is generated. | ||
| 1 = RLS interrupt flag is generated. | ||
| Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit. | ||
| At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. | ||
| Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. | ||
| Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. | ||
| [3] | MODEMIF | MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. |
| 0 = No Modem interrupt flag is generated. | ||
| 1 = Modem interrupt flag is generated. | ||
| Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). | ||
| [4] | RXTOIF | Time-Out Interrupt Flag (Read Only) |
| This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. | ||
| If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. | ||
| 0 = No Time-out interrupt flag is generated. | ||
| 1 = Time-out interrupt flag is generated. | ||
| Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. | ||
| [5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only) |
| This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). | ||
| When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. | ||
| If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated. | ||
| 0 = No buffer error interrupt flag is generated. | ||
| 1 = Buffer error interrupt flag is generated. | ||
| Note: This bit is read only. | ||
| This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). | ||
| [6] | WKIF | UART Wake-up Interrupt Flag (Read Only) |
| This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1. | ||
| 0 = No DATWKIF and CTSWKIF are generated. | ||
| 1 = DATWKIF or CTSWKIF. | ||
| Note: This bit is read only. | ||
| This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). | ||
| [7] | LINIF | LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel) |
| This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])). | ||
| If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. | ||
| 0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. | ||
| 1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. | ||
| Note: This bit is read only. | ||
| This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared. | ||
| [8] | RDAINT | Receive Data Available Interrupt Indicator (Read Only) |
| This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. | ||
| 0 = No RDA interrupt is generated. | ||
| 1 = RDA interrupt is generated. | ||
| [9] | THREINT | Transmit Holding Register Empty Interrupt Indicator (Read Only) |
| This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1. | ||
| 0 = No DATE interrupt is generated. | ||
| 1 = DATE interrupt is generated. | ||
| [10] | RLSINT | Receive Line Status Interrupt Indicator (Read Only) |
| This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. | ||
| 0 = No RLS interrupt is generated. | ||
| 1 = RLS interrupt is generated. | ||
| [11] | MODEMINT | MODEM Status Interrupt Indicator (Read Only) |
| This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1 | ||
| 0 = No Modem interrupt is generated. | ||
| 1 = Modem interrupt is generated. | ||
| [12] | RXTOINT | Time-Out Interrupt Indicator (Read Only) |
| This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. | ||
| 0 = No Tout interrupt is generated. | ||
| 1 = Tout interrupt is generated. | ||
| [13] | BUFERRINT | Buffer Error Interrupt Indicator (Read Only) |
| This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1. | ||
| 0 = No buffer error interrupt is generated. | ||
| 1 = Buffer error interrupt is generated. | ||
| [15] | LININT | LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel) |
| This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1. | ||
| 0 = No LIN Bus interrupt is generated. | ||
| 1 = The LIN Bus interrupt is generated. | ||
| [16] | CTSWKIF | nCTS Wake-Up Interrupt Flag (Read Only) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by nCTS wake-up. | ||
| Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [17] | DATWKIF | Data Wake-Up Interrupt Flag (Read Only) |
| This bit is set if chip wake-up from power-down state by data wake-up. | ||
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by data wake-up. | ||
| Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [18] | HWRLSIF | In DMA Mode, Receive Line Status Flag (Read Only) |
| This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). | ||
| If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. | ||
| 0 = No RLS interrupt flag is generated. | ||
| 1 = RLS interrupt flag is generated. | ||
| Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit. | ||
| Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. | ||
| Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared | ||
| [19] | HWMODIF | In DMA Mode, MODEM Interrupt Flag (Read Only) |
| This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)). | ||
| If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. | ||
| 0 = No Modem interrupt flag is generated. | ||
| 1 = Modem interrupt flag is generated. | ||
| Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]). | ||
| [20] | HWTOIF | In DMA Mode, Time-Out Interrupt Flag (Read Only) |
| This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). | ||
| If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. | ||
| 0 = No Time-out interrupt flag is generated. | ||
| 1 = Time-out interrupt flag is generated. | ||
| Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. | ||
| [21] | HWBUFEIF | In DMA Mode, Buffer Error Interrupt Flag (Read Only) |
| This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). | ||
| When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. | ||
| If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. | ||
| 0 = No buffer error interrupt flag is generated. | ||
| 1 = Buffer error interrupt flag is generated. | ||
| Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. | ||
| [26] | HWRLSINT | In DMA Mode, Receive Line Status Interrupt Indicator (Read Only) |
| This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1. | ||
| 0 = No RLS interrupt is generated in DMA mode. | ||
| 1 = RLS interrupt is generated in DMA mode. | ||
| [27] | HWMODINT | In DMA Mode, MODEM Status Interrupt Indicator (Read Only) |
| This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1. | ||
| 0 = No Modem interrupt is generated in DMA mode. | ||
| 1 = Modem interrupt is generated in DMA mode. | ||
| [28] | HWTOINT | In DMA Mode, Time-Out Interrupt Indicator (Read Only) |
| This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1. | ||
| 0 = No Tout interrupt is generated in DMA mode. | ||
| 1 = Tout interrupt is generated in DMA mode. | ||
| [29] | HWBUFEINT | In DMA Mode, Buffer Error Interrupt Indicator (Read Only) |
| This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1. | ||
| 0 = No buffer error interrupt is generated in DMA mode. | ||
| 1 = Buffer error interrupt is generated in DMA mode. |
| USBD_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSIF | BUS Interrupt Status |
| The BUS event means that there is one of the suspense or the resume function in the bus. | ||
| 0 = No BUS event occurred. | ||
| 1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]. | ||
| [1] | USBIF | USB Event Interrupt Status |
| The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. | ||
| 0 = No USB event occurred. | ||
| 1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred. | ||
| Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]). | ||
| [2] | VBDETIF | VBUS Detection Interrupt Status |
| 0 = There is not attached/detached event in the USB. | ||
| 1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]. | ||
| [3] | NEVWKIF | USB No-Event-Wake-Up Interrupt Status |
| 0 = No Wake-up event occurred. | ||
| 1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]. | ||
| [4] | SOFIF | Start of Frame Interrupt Status |
| 0 = SOF event does not occur. | ||
| 1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. | ||
| [16] | EPEVT0 | Endpoint 0's USB Event Status |
| 0 = No event occurred on endpoint 0. | ||
| 1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]. | ||
| [17] | EPEVT1 | Endpoint 1's USB Event Status |
| 0 = No event occurred on endpoint 1. | ||
| 1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]. | ||
| [18] | EPEVT2 | Endpoint 2's USB Event Status |
| 0 = No event occurred on endpoint 2. | ||
| 1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]. | ||
| [19] | EPEVT3 | Endpoint 3's USB Event Status |
| 0 = No event occurred on endpoint 3. | ||
| 1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]. | ||
| [20] | EPEVT4 | Endpoint 4's USB Event Status |
| 0 = No event occurred on endpoint 4. | ||
| 1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]. | ||
| [21] | EPEVT5 | Endpoint 5's USB Event Status |
| 0 = No event occurred on endpoint 5. | ||
| 1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]. | ||
| [22] | EPEVT6 | Endpoint 6's USB Event Status |
| 0 = No event occurred on endpoint 6. | ||
| 1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1]. | ||
| [23] | EPEVT7 | Endpoint 7's USB Event Status |
| 0 = No event occurred on endpoint 7. | ||
| 1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1]. | ||
| [31] | SETUP | Setup Event Status |
| 0 = No Setup event. | ||
| 1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31]. |
| PWM_T::INTSTS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | ZIFn | PWM Zero Point Interrupt Flag |
| Each bit n controls the corresponding PWM channel n. | ||
| This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. | ||
| [7] | IFAIF0_1 | PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag |
| Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it. | ||
| [13:8] | PIFn | PWM Period Point Interrupt Flag |
| This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero. | ||
| Each bit n controls the corresponding PWM channel n. | ||
| [15] | IFAIF2_3 | PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag |
| Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it. | ||
| [21:16] | CMPUIFn | PWM Compare Up Count Interrupt Flag |
| Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. | ||
| Each bit n controls the corresponding PWM channel n. | ||
| Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. | ||
| Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. | ||
| [23] | IFAIF4_5 | PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag |
| Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it. | ||
| [29:24] | CMPDIFn | PWM Compare Down Count Interrupt Flag |
| Each bit n controls the corresponding PWM channel n. | ||
| Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. | ||
| Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. | ||
| Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
| PWM_T::INTSTS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKEIF0 | PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel0 edge-detect brake event do not happened. | ||
| 1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [1] | BRKEIF1 | PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel1 edge-detect brake event do not happened. | ||
| 1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [2] | BRKEIF2 | PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel2 edge-detect brake event do not happened. | ||
| 1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [3] | BRKEIF3 | PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel3 edge-detect brake event do not happened. | ||
| 1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [4] | BRKEIF4 | PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel4 edge-detect brake event do not happened. | ||
| 1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKEIF5 | PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel5 edge-detect brake event do not happened. | ||
| 1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [8] | BRKLIF0 | PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel0 level-detect brake event do not happened. | ||
| 1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [9] | BRKLIF1 | PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel1 level-detect brake event do not happened. | ||
| 1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [10] | BRKLIF2 | PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel2 level-detect brake event do not happened. | ||
| 1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [11] | BRKLIF3 | PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel3 level-detect brake event do not happened. | ||
| 1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKLIF4 | PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel4 level-detect brake event do not happened. | ||
| 1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKLIF5 | PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM channel5 level-detect brake event do not happened. | ||
| 1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | BRKESTS0 | PWM Channel0 Edge-Detect Brake Status |
| 0 = PWM channel0 edge-detect brake state is released. | ||
| 1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear. | ||
| [17] | BRKESTS1 | PWM Channel1 Edge-Detect Brake Status |
| 0 = PWM channel1 edge-detect brake state is released. | ||
| 1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear. | ||
| [18] | BRKESTS2 | PWM Channel2 Edge-Detect Brake Status |
| 0 = PWM channel2 edge-detect brake state is released. | ||
| 1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear. | ||
| [19] | BRKESTS3 | PWM Channel3 Edge-Detect Brake Status |
| 0 = PWM channel3 edge-detect brake state is released. | ||
| 1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear. | ||
| [20] | BRKESTS4 | PWM Channel4 Edge-Detect Brake Status |
| 0 = PWM channel4 edge-detect brake state is released. | ||
| 1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear. | ||
| [21] | BRKESTS5 | PWM Channel5 Edge-Detect Brake Status |
| 0 = PWM channel5 edge-detect brake state is released. | ||
| 1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear. | ||
| [24] | BRKLSTS0 | PWM Channel0 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel0 level-detect brake state is released. | ||
| 1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. | ||
| [25] | BRKLSTS1 | PWM Channel1 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel1 level-detect brake state is released. | ||
| 1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. | ||
| [26] | BRKLSTS2 | PWM Channel2 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel2 level-detect brake state is released. | ||
| 1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. | ||
| [27] | BRKLSTS3 | PWM Channel3 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel3 level-detect brake state is released. | ||
| 1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. | ||
| [28] | BRKLSTS4 | PWM Channel4 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel4 level-detect brake state is released. | ||
| 1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. | ||
| [29] | BRKLSTS5 | PWM Channel5 Level-Detect Brake Status (Read Only) |
| 0 = PWM channel5 level-detect brake state is released. | ||
| 1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware. | ||
| When enabled brake source return to high level, PWM will release brake state until current PWM period finished. | ||
| The PWM waveform will start output from next full PWM period. |
| GPIO_T::INTTYPE |
| Bits | Field | Descriptions |
|---|---|---|
| [n] | TYPEn | Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note: | ||
| n=0~15 for port A/B/C/D. | ||
| n=0~14 for port E. | ||
| n=0~7 for port F. |
| SYS_T::IPRST0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHIPRST | Chip One-Shot Reset (Write Protect) |
| Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. | ||
| The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. | ||
| About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2 | ||
| 0 = Chip normal operation. | ||
| 1 = Chip one shot reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | CPURST | Processor Core One-Shot Reset (Write Protect) |